2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/ioport.h>
23 #include <linux/spinlock.h>
25 #include <linux/module.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
29 #include <linux/of_mtd.h>
30 #include <linux/of_device.h>
31 #include <linux/mtd/nand.h>
33 #include <linux/platform_data/mtd-nand-omap2.h>
35 #include <asm/mach-types.h>
39 #include "omap_device.h"
41 #include "gpmc-nand.h"
43 #define DEVICE_NAME "omap-gpmc"
45 /* GPMC register offsets */
46 #define GPMC_REVISION 0x00
47 #define GPMC_SYSCONFIG 0x10
48 #define GPMC_SYSSTATUS 0x14
49 #define GPMC_IRQSTATUS 0x18
50 #define GPMC_IRQENABLE 0x1c
51 #define GPMC_TIMEOUT_CONTROL 0x40
52 #define GPMC_ERR_ADDRESS 0x44
53 #define GPMC_ERR_TYPE 0x48
54 #define GPMC_CONFIG 0x50
55 #define GPMC_STATUS 0x54
56 #define GPMC_PREFETCH_CONFIG1 0x1e0
57 #define GPMC_PREFETCH_CONFIG2 0x1e4
58 #define GPMC_PREFETCH_CONTROL 0x1ec
59 #define GPMC_PREFETCH_STATUS 0x1f0
60 #define GPMC_ECC_CONFIG 0x1f4
61 #define GPMC_ECC_CONTROL 0x1f8
62 #define GPMC_ECC_SIZE_CONFIG 0x1fc
63 #define GPMC_ECC1_RESULT 0x200
64 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
65 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
66 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
67 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
69 /* GPMC ECC control settings */
70 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
71 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
72 #define GPMC_ECC_CTRL_ECCREG1 0x001
73 #define GPMC_ECC_CTRL_ECCREG2 0x002
74 #define GPMC_ECC_CTRL_ECCREG3 0x003
75 #define GPMC_ECC_CTRL_ECCREG4 0x004
76 #define GPMC_ECC_CTRL_ECCREG5 0x005
77 #define GPMC_ECC_CTRL_ECCREG6 0x006
78 #define GPMC_ECC_CTRL_ECCREG7 0x007
79 #define GPMC_ECC_CTRL_ECCREG8 0x008
80 #define GPMC_ECC_CTRL_ECCREG9 0x009
82 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
83 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
84 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
85 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
86 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
87 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
89 #define GPMC_CS0_OFFSET 0x60
90 #define GPMC_CS_SIZE 0x30
91 #define GPMC_BCH_SIZE 0x10
93 #define GPMC_MEM_START 0x00000000
94 #define GPMC_MEM_END 0x3FFFFFFF
95 #define BOOT_ROM_SPACE 0x100000 /* 1MB */
97 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
98 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
100 #define CS_NUM_SHIFT 24
101 #define ENABLE_PREFETCH (0x1 << 7)
102 #define DMA_MPU_MODE 2
104 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
105 #define GPMC_REVISION_MINOR(l) (l & 0xf)
107 #define GPMC_HAS_WR_ACCESS 0x1
108 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
110 /* XXX: Only NAND irq has been considered,currently these are the only ones used
112 #define GPMC_NR_IRQ 2
114 struct gpmc_client_irq {
119 /* Structure to save gpmc cs context */
120 struct gpmc_cs_config {
132 * Structure to save/restore gpmc context
133 * to support core off on OMAP3
135 struct omap3_gpmc_regs {
140 u32 prefetch_config1;
141 u32 prefetch_config2;
142 u32 prefetch_control;
143 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
146 static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
147 static struct irq_chip gpmc_irq_chip;
148 static unsigned gpmc_irq_start;
150 static struct resource gpmc_mem_root;
151 static struct resource gpmc_cs_mem[GPMC_CS_NUM];
152 static DEFINE_SPINLOCK(gpmc_mem_lock);
153 static unsigned int gpmc_cs_map; /* flag for cs which are initialized */
154 static struct device *gpmc_dev;
156 static resource_size_t phys_base, mem_size;
157 static unsigned gpmc_capability;
158 static void __iomem *gpmc_base;
160 static struct clk *gpmc_l3_clk;
162 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
164 static void gpmc_write_reg(int idx, u32 val)
166 __raw_writel(val, gpmc_base + idx);
169 static u32 gpmc_read_reg(int idx)
171 return __raw_readl(gpmc_base + idx);
174 void gpmc_cs_write_reg(int cs, int idx, u32 val)
176 void __iomem *reg_addr;
178 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
179 __raw_writel(val, reg_addr);
182 u32 gpmc_cs_read_reg(int cs, int idx)
184 void __iomem *reg_addr;
186 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
187 return __raw_readl(reg_addr);
190 /* TODO: Add support for gpmc_fck to clock framework and use it */
191 unsigned long gpmc_get_fclk_period(void)
193 unsigned long rate = clk_get_rate(gpmc_l3_clk);
196 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
201 rate = 1000000000 / rate; /* In picoseconds */
206 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
208 unsigned long tick_ps;
210 /* Calculate in picosecs to yield more exact results */
211 tick_ps = gpmc_get_fclk_period();
213 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
216 unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
218 unsigned long tick_ps;
220 /* Calculate in picosecs to yield more exact results */
221 tick_ps = gpmc_get_fclk_period();
223 return (time_ps + tick_ps - 1) / tick_ps;
226 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
228 return ticks * gpmc_get_fclk_period() / 1000;
231 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
233 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
235 return ticks * gpmc_get_fclk_period() / 1000;
238 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
240 return ticks * gpmc_get_fclk_period();
243 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
245 unsigned long ticks = gpmc_ps_to_ticks(time_ps);
247 return ticks * gpmc_get_fclk_period();
250 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
254 l = gpmc_cs_read_reg(cs, reg);
259 gpmc_cs_write_reg(cs, reg, l);
262 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
264 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
265 GPMC_CONFIG1_TIME_PARA_GRAN,
266 p->time_para_granularity);
267 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
268 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
269 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
270 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
271 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
272 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
273 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
274 GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
275 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
276 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
277 p->cycle2cyclesamecsen);
278 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
279 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
280 p->cycle2cyclediffcsen);
284 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
285 int time, const char *name)
287 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
292 int ticks, mask, nr_bits;
297 ticks = gpmc_ns_to_ticks(time);
298 nr_bits = end_bit - st_bit + 1;
299 if (ticks >= 1 << nr_bits) {
301 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
302 cs, name, time, ticks, 1 << nr_bits);
307 mask = (1 << nr_bits) - 1;
308 l = gpmc_cs_read_reg(cs, reg);
311 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
312 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
313 (l >> st_bit) & mask, time);
315 l &= ~(mask << st_bit);
316 l |= ticks << st_bit;
317 gpmc_cs_write_reg(cs, reg, l);
323 #define GPMC_SET_ONE(reg, st, end, field) \
324 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
325 t->field, #field) < 0) \
328 #define GPMC_SET_ONE(reg, st, end, field) \
329 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
333 int gpmc_calc_divider(unsigned int sync_clk)
338 l = sync_clk + (gpmc_get_fclk_period() - 1);
339 div = l / gpmc_get_fclk_period();
348 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
353 div = gpmc_calc_divider(t->sync_clk);
357 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
358 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
359 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
361 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
362 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
363 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
365 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
366 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
367 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
368 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
370 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
371 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
372 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
374 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
376 GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
377 GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
379 GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
380 GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
382 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
383 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
384 if (gpmc_capability & GPMC_HAS_WR_ACCESS)
385 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
387 /* caller is expected to have initialized CONFIG1 to cover
388 * at least sync vs async
390 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
391 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
393 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
394 cs, (div * gpmc_get_fclk_period()) / 1000, div);
398 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
401 gpmc_cs_bool_timings(cs, &t->bool_timings);
406 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
411 mask = (1 << GPMC_SECTION_SHIFT) - size;
412 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
414 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
416 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
417 l |= GPMC_CONFIG7_CSVALID;
418 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
421 static void gpmc_cs_disable_mem(int cs)
425 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
426 l &= ~GPMC_CONFIG7_CSVALID;
427 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
430 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
435 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
436 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
437 mask = (l >> 8) & 0x0f;
438 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
441 static int gpmc_cs_mem_enabled(int cs)
445 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
446 return l & GPMC_CONFIG7_CSVALID;
449 int gpmc_cs_set_reserved(int cs, int reserved)
451 if (cs > GPMC_CS_NUM)
454 gpmc_cs_map &= ~(1 << cs);
455 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
460 int gpmc_cs_reserved(int cs)
462 if (cs > GPMC_CS_NUM)
465 return gpmc_cs_map & (1 << cs);
468 static unsigned long gpmc_mem_align(unsigned long size)
472 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
473 order = GPMC_CHUNK_SHIFT - 1;
482 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
484 struct resource *res = &gpmc_cs_mem[cs];
487 size = gpmc_mem_align(size);
488 spin_lock(&gpmc_mem_lock);
490 res->end = base + size - 1;
491 r = request_resource(&gpmc_mem_root, res);
492 spin_unlock(&gpmc_mem_lock);
497 static int gpmc_cs_delete_mem(int cs)
499 struct resource *res = &gpmc_cs_mem[cs];
502 spin_lock(&gpmc_mem_lock);
503 r = release_resource(&gpmc_cs_mem[cs]);
506 spin_unlock(&gpmc_mem_lock);
511 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
513 struct resource *res = &gpmc_cs_mem[cs];
516 if (cs > GPMC_CS_NUM)
519 size = gpmc_mem_align(size);
520 if (size > (1 << GPMC_SECTION_SHIFT))
523 spin_lock(&gpmc_mem_lock);
524 if (gpmc_cs_reserved(cs)) {
528 if (gpmc_cs_mem_enabled(cs))
529 r = adjust_resource(res, res->start & ~(size - 1), size);
531 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
536 gpmc_cs_enable_mem(cs, res->start, resource_size(res));
538 gpmc_cs_set_reserved(cs, 1);
540 spin_unlock(&gpmc_mem_lock);
543 EXPORT_SYMBOL(gpmc_cs_request);
545 void gpmc_cs_free(int cs)
547 spin_lock(&gpmc_mem_lock);
548 if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
549 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
551 spin_unlock(&gpmc_mem_lock);
554 gpmc_cs_disable_mem(cs);
555 release_resource(&gpmc_cs_mem[cs]);
556 gpmc_cs_set_reserved(cs, 0);
557 spin_unlock(&gpmc_mem_lock);
559 EXPORT_SYMBOL(gpmc_cs_free);
562 * gpmc_cs_configure - write request to configure gpmc
563 * @cs: chip select number
565 * @wval: value to write
566 * @return status of the operation
568 int gpmc_cs_configure(int cs, int cmd, int wval)
574 case GPMC_ENABLE_IRQ:
575 gpmc_write_reg(GPMC_IRQENABLE, wval);
578 case GPMC_SET_IRQ_STATUS:
579 gpmc_write_reg(GPMC_IRQSTATUS, wval);
583 regval = gpmc_read_reg(GPMC_CONFIG);
585 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
587 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
588 gpmc_write_reg(GPMC_CONFIG, regval);
591 case GPMC_CONFIG_RDY_BSY:
592 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
594 regval |= WR_RD_PIN_MONITORING;
596 regval &= ~WR_RD_PIN_MONITORING;
597 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
600 case GPMC_CONFIG_DEV_SIZE:
601 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
603 /* clear 2 target bits */
604 regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
606 /* set the proper value */
607 regval |= GPMC_CONFIG1_DEVICESIZE(wval);
609 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
612 case GPMC_CONFIG_DEV_TYPE:
613 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
614 regval |= GPMC_CONFIG1_DEVICETYPE(wval);
615 if (wval == GPMC_DEVICETYPE_NOR)
616 regval |= GPMC_CONFIG1_MUXADDDATA;
617 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
621 printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
627 EXPORT_SYMBOL(gpmc_cs_configure);
629 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
633 reg->gpmc_status = gpmc_base + GPMC_STATUS;
634 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
635 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
636 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
637 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
638 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
639 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
640 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
641 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
642 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
643 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
644 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
645 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
646 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
647 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
649 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
650 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
652 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
654 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
656 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
661 int gpmc_get_client_irq(unsigned irq_config)
665 if (hweight32(irq_config) > 1)
668 for (i = 0; i < GPMC_NR_IRQ; i++)
669 if (gpmc_client_irq[i].bitmask & irq_config)
670 return gpmc_client_irq[i].irq;
675 static int gpmc_irq_endis(unsigned irq, bool endis)
680 for (i = 0; i < GPMC_NR_IRQ; i++)
681 if (irq == gpmc_client_irq[i].irq) {
682 regval = gpmc_read_reg(GPMC_IRQENABLE);
684 regval |= gpmc_client_irq[i].bitmask;
686 regval &= ~gpmc_client_irq[i].bitmask;
687 gpmc_write_reg(GPMC_IRQENABLE, regval);
694 static void gpmc_irq_disable(struct irq_data *p)
696 gpmc_irq_endis(p->irq, false);
699 static void gpmc_irq_enable(struct irq_data *p)
701 gpmc_irq_endis(p->irq, true);
704 static void gpmc_irq_noop(struct irq_data *data) { }
706 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
708 static int gpmc_setup_irq(void)
716 gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
717 if (IS_ERR_VALUE(gpmc_irq_start)) {
718 pr_err("irq_alloc_descs failed\n");
719 return gpmc_irq_start;
722 gpmc_irq_chip.name = "gpmc";
723 gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
724 gpmc_irq_chip.irq_enable = gpmc_irq_enable;
725 gpmc_irq_chip.irq_disable = gpmc_irq_disable;
726 gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
727 gpmc_irq_chip.irq_ack = gpmc_irq_noop;
728 gpmc_irq_chip.irq_mask = gpmc_irq_noop;
729 gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
731 gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
732 gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
734 for (i = 0; i < GPMC_NR_IRQ; i++) {
735 gpmc_client_irq[i].irq = gpmc_irq_start + i;
736 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
737 &gpmc_irq_chip, handle_simple_irq);
738 set_irq_flags(gpmc_client_irq[i].irq,
739 IRQF_VALID | IRQF_NOAUTOEN);
742 /* Disable interrupts */
743 gpmc_write_reg(GPMC_IRQENABLE, 0);
745 /* clear interrupts */
746 regval = gpmc_read_reg(GPMC_IRQSTATUS);
747 gpmc_write_reg(GPMC_IRQSTATUS, regval);
749 return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
752 static int gpmc_free_irq(void)
757 free_irq(gpmc_irq, NULL);
759 for (i = 0; i < GPMC_NR_IRQ; i++) {
760 irq_set_handler(gpmc_client_irq[i].irq, NULL);
761 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
762 irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
765 irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
770 static void gpmc_mem_exit(void)
774 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
775 if (!gpmc_cs_mem_enabled(cs))
777 gpmc_cs_delete_mem(cs);
782 static int gpmc_mem_init(void)
785 unsigned long boot_rom_space = 0;
787 /* never allocate the first page, to facilitate bug detection;
788 * even if we didn't boot from ROM.
790 boot_rom_space = BOOT_ROM_SPACE;
791 /* In apollon the CS0 is mapped as 0x0000 0000 */
792 if (machine_is_omap_apollon())
794 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
795 gpmc_mem_root.end = GPMC_MEM_END;
797 /* Reserve all regions that has been set up by bootloader */
798 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
801 if (!gpmc_cs_mem_enabled(cs))
803 gpmc_cs_get_memconf(cs, &base, &size);
804 rc = gpmc_cs_insert_mem(cs, base, size);
805 if (IS_ERR_VALUE(rc)) {
807 if (gpmc_cs_mem_enabled(cs))
808 gpmc_cs_delete_mem(cs);
816 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
821 div = gpmc_calc_divider(sync_clk);
822 temp = gpmc_ps_to_ticks(time_ps);
823 temp = (temp + div - 1) / div;
824 return gpmc_ticks_to_ps(temp * div);
827 /* XXX: can the cycles be avoided ? */
828 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
829 struct gpmc_device_timings *dev_t)
831 bool mux = dev_t->mux;
835 temp = dev_t->t_avdp_r;
836 /* XXX: mux check required ? */
838 /* XXX: t_avdp not to be required for sync, only added for tusb
839 * this indirectly necessitates requirement of t_avdp_r and
840 * t_avdp_w instead of having a single t_avdp
842 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
843 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
845 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
848 temp = dev_t->t_oeasu; /* XXX: remove this ? */
850 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
851 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
852 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
854 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
857 /* XXX: any scope for improvement ?, by combining oe_on
858 * and clk_activation, need to check whether
859 * access = clk_activation + round to sync clk ?
861 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
862 temp += gpmc_t->clk_activation;
864 temp = max_t(u32, temp, gpmc_t->oe_on +
865 gpmc_ticks_to_ps(dev_t->cyc_oe));
866 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
868 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
869 gpmc_t->cs_rd_off = gpmc_t->oe_off;
872 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
873 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
875 /* XXX: barter t_ce_rdyz with t_cez_r ? */
876 if (dev_t->t_ce_rdyz)
877 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
878 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
883 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
884 struct gpmc_device_timings *dev_t)
886 bool mux = dev_t->mux;
890 temp = dev_t->t_avdp_w;
892 temp = max_t(u32, temp,
893 gpmc_t->clk_activation + dev_t->t_avdh);
894 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
896 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
898 /* wr_data_mux_bus */
899 temp = max_t(u32, dev_t->t_weasu,
900 gpmc_t->clk_activation + dev_t->t_rdyo);
901 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
902 * and in that case remember to handle we_on properly
905 temp = max_t(u32, temp,
906 gpmc_t->adv_wr_off + dev_t->t_aavdh);
907 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
908 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
910 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
913 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
914 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
916 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
919 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
920 gpmc_t->wr_access = gpmc_t->access;
923 temp = gpmc_t->we_on + dev_t->t_wpl;
924 temp = max_t(u32, temp,
925 gpmc_t->wr_access + gpmc_ticks_to_ps(1));
926 temp = max_t(u32, temp,
927 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
928 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
930 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
934 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
935 temp += gpmc_t->wr_access;
936 /* XXX: barter t_ce_rdyz with t_cez_w ? */
937 if (dev_t->t_ce_rdyz)
938 temp = max_t(u32, temp,
939 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
940 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
945 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
946 struct gpmc_device_timings *dev_t)
948 bool mux = dev_t->mux;
952 temp = dev_t->t_avdp_r;
954 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
955 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
958 temp = dev_t->t_oeasu;
960 temp = max_t(u32, temp,
961 gpmc_t->adv_rd_off + dev_t->t_aavdh);
962 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
965 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
966 gpmc_t->oe_on + dev_t->t_oe);
967 temp = max_t(u32, temp,
968 gpmc_t->cs_on + dev_t->t_ce);
969 temp = max_t(u32, temp,
970 gpmc_t->adv_on + dev_t->t_aa);
971 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
973 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
974 gpmc_t->cs_rd_off = gpmc_t->oe_off;
977 temp = max_t(u32, dev_t->t_rd_cycle,
978 gpmc_t->cs_rd_off + dev_t->t_cez_r);
979 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
980 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
985 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
986 struct gpmc_device_timings *dev_t)
988 bool mux = dev_t->mux;
992 temp = dev_t->t_avdp_w;
994 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
995 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
997 /* wr_data_mux_bus */
998 temp = dev_t->t_weasu;
1000 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1001 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1002 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1004 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1007 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1008 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1010 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1013 temp = gpmc_t->we_on + dev_t->t_wpl;
1014 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1016 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1020 temp = max_t(u32, dev_t->t_wr_cycle,
1021 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1022 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1027 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1028 struct gpmc_device_timings *dev_t)
1032 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1033 gpmc_get_fclk_period();
1035 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1039 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1040 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1042 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1045 if (dev_t->ce_xdelay)
1046 gpmc_t->bool_timings.cs_extra_delay = true;
1047 if (dev_t->avd_xdelay)
1048 gpmc_t->bool_timings.adv_extra_delay = true;
1049 if (dev_t->oe_xdelay)
1050 gpmc_t->bool_timings.oe_extra_delay = true;
1051 if (dev_t->we_xdelay)
1052 gpmc_t->bool_timings.we_extra_delay = true;
1057 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1058 struct gpmc_device_timings *dev_t)
1063 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1066 temp = dev_t->t_avdasu;
1067 if (dev_t->t_ce_avd)
1068 temp = max_t(u32, temp,
1069 gpmc_t->cs_on + dev_t->t_ce_avd);
1070 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1072 if (dev_t->sync_write || dev_t->sync_read)
1073 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1078 /* TODO: remove this function once all peripherals are confirmed to
1079 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1080 * has to be modified to handle timings in ps instead of ns
1082 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1085 t->cs_rd_off /= 1000;
1086 t->cs_wr_off /= 1000;
1088 t->adv_rd_off /= 1000;
1089 t->adv_wr_off /= 1000;
1094 t->page_burst_access /= 1000;
1096 t->rd_cycle /= 1000;
1097 t->wr_cycle /= 1000;
1098 t->bus_turnaround /= 1000;
1099 t->cycle2cycle_delay /= 1000;
1100 t->wait_monitoring /= 1000;
1101 t->clk_activation /= 1000;
1102 t->wr_access /= 1000;
1103 t->wr_data_mux_bus /= 1000;
1106 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1107 struct gpmc_device_timings *dev_t)
1109 memset(gpmc_t, 0, sizeof(*gpmc_t));
1111 gpmc_calc_common_timings(gpmc_t, dev_t);
1113 if (dev_t->sync_read)
1114 gpmc_calc_sync_read_timings(gpmc_t, dev_t);
1116 gpmc_calc_async_read_timings(gpmc_t, dev_t);
1118 if (dev_t->sync_write)
1119 gpmc_calc_sync_write_timings(gpmc_t, dev_t);
1121 gpmc_calc_async_write_timings(gpmc_t, dev_t);
1123 /* TODO: remove, see function definition */
1124 gpmc_convert_ps_to_ns(gpmc_t);
1130 static struct of_device_id gpmc_dt_ids[] = {
1131 { .compatible = "ti,omap2420-gpmc" },
1132 { .compatible = "ti,omap2430-gpmc" },
1133 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1134 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1135 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
1138 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1140 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1141 struct gpmc_timings *gpmc_t)
1145 memset(gpmc_t, 0, sizeof(*gpmc_t));
1147 /* minimum clock period for syncronous mode */
1148 if (!of_property_read_u32(np, "gpmc,sync-clk", &val))
1149 gpmc_t->sync_clk = val;
1151 /* chip select timtings */
1152 if (!of_property_read_u32(np, "gpmc,cs-on", &val))
1153 gpmc_t->cs_on = val;
1155 if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val))
1156 gpmc_t->cs_rd_off = val;
1158 if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val))
1159 gpmc_t->cs_wr_off = val;
1161 /* ADV signal timings */
1162 if (!of_property_read_u32(np, "gpmc,adv-on", &val))
1163 gpmc_t->adv_on = val;
1165 if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val))
1166 gpmc_t->adv_rd_off = val;
1168 if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val))
1169 gpmc_t->adv_wr_off = val;
1171 /* WE signal timings */
1172 if (!of_property_read_u32(np, "gpmc,we-on", &val))
1173 gpmc_t->we_on = val;
1175 if (!of_property_read_u32(np, "gpmc,we-off", &val))
1176 gpmc_t->we_off = val;
1178 /* OE signal timings */
1179 if (!of_property_read_u32(np, "gpmc,oe-on", &val))
1180 gpmc_t->oe_on = val;
1182 if (!of_property_read_u32(np, "gpmc,oe-off", &val))
1183 gpmc_t->oe_off = val;
1185 /* access and cycle timings */
1186 if (!of_property_read_u32(np, "gpmc,page-burst-access", &val))
1187 gpmc_t->page_burst_access = val;
1189 if (!of_property_read_u32(np, "gpmc,access", &val))
1190 gpmc_t->access = val;
1192 if (!of_property_read_u32(np, "gpmc,rd-cycle", &val))
1193 gpmc_t->rd_cycle = val;
1195 if (!of_property_read_u32(np, "gpmc,wr-cycle", &val))
1196 gpmc_t->wr_cycle = val;
1198 /* only for OMAP3430 */
1199 if (!of_property_read_u32(np, "gpmc,wr-access", &val))
1200 gpmc_t->wr_access = val;
1202 if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val))
1203 gpmc_t->wr_data_mux_bus = val;
1206 #ifdef CONFIG_MTD_NAND
1208 static const char * const nand_ecc_opts[] = {
1209 [OMAP_ECC_HAMMING_CODE_DEFAULT] = "sw",
1210 [OMAP_ECC_HAMMING_CODE_HW] = "hw",
1211 [OMAP_ECC_HAMMING_CODE_HW_ROMCODE] = "hw-romcode",
1212 [OMAP_ECC_BCH4_CODE_HW] = "bch4",
1213 [OMAP_ECC_BCH8_CODE_HW] = "bch8",
1216 static int gpmc_probe_nand_child(struct platform_device *pdev,
1217 struct device_node *child)
1221 struct gpmc_timings gpmc_t;
1222 struct omap_nand_platform_data *gpmc_nand_data;
1224 if (of_property_read_u32(child, "reg", &val) < 0) {
1225 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1230 gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1232 if (!gpmc_nand_data)
1235 gpmc_nand_data->cs = val;
1236 gpmc_nand_data->of_node = child;
1238 if (!of_property_read_string(child, "ti,nand-ecc-opt", &s))
1239 for (val = 0; val < ARRAY_SIZE(nand_ecc_opts); val++)
1240 if (!strcasecmp(s, nand_ecc_opts[val])) {
1241 gpmc_nand_data->ecc_opt = val;
1245 val = of_get_nand_bus_width(child);
1247 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1249 gpmc_read_timings_dt(child, &gpmc_t);
1250 gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1255 static int gpmc_probe_nand_child(struct platform_device *pdev,
1256 struct device_node *child)
1262 static int gpmc_probe_dt(struct platform_device *pdev)
1265 struct device_node *child;
1266 const struct of_device_id *of_id =
1267 of_match_device(gpmc_dt_ids, &pdev->dev);
1272 for_each_node_by_name(child, "nand") {
1273 ret = gpmc_probe_nand_child(pdev, child);
1282 static int gpmc_probe_dt(struct platform_device *pdev)
1288 static int gpmc_probe(struct platform_device *pdev)
1292 struct resource *res;
1294 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1298 phys_base = res->start;
1299 mem_size = resource_size(res);
1301 gpmc_base = devm_request_and_ioremap(&pdev->dev, res);
1303 dev_err(&pdev->dev, "error: request memory / ioremap\n");
1304 return -EADDRNOTAVAIL;
1307 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1309 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
1311 gpmc_irq = res->start;
1313 gpmc_l3_clk = clk_get(&pdev->dev, "fck");
1314 if (IS_ERR(gpmc_l3_clk)) {
1315 dev_err(&pdev->dev, "error: clk_get\n");
1317 return PTR_ERR(gpmc_l3_clk);
1320 clk_prepare_enable(gpmc_l3_clk);
1322 gpmc_dev = &pdev->dev;
1324 l = gpmc_read_reg(GPMC_REVISION);
1325 if (GPMC_REVISION_MAJOR(l) > 0x4)
1326 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
1327 dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
1328 GPMC_REVISION_MINOR(l));
1330 rc = gpmc_mem_init();
1331 if (IS_ERR_VALUE(rc)) {
1332 clk_disable_unprepare(gpmc_l3_clk);
1333 clk_put(gpmc_l3_clk);
1334 dev_err(gpmc_dev, "failed to reserve memory\n");
1338 if (IS_ERR_VALUE(gpmc_setup_irq()))
1339 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
1341 rc = gpmc_probe_dt(pdev);
1343 clk_disable_unprepare(gpmc_l3_clk);
1344 clk_put(gpmc_l3_clk);
1345 dev_err(gpmc_dev, "failed to probe DT parameters\n");
1352 static int gpmc_remove(struct platform_device *pdev)
1360 static struct platform_driver gpmc_driver = {
1361 .probe = gpmc_probe,
1362 .remove = gpmc_remove,
1364 .name = DEVICE_NAME,
1365 .owner = THIS_MODULE,
1366 .of_match_table = of_match_ptr(gpmc_dt_ids),
1370 static __init int gpmc_init(void)
1372 return platform_driver_register(&gpmc_driver);
1375 static __exit void gpmc_exit(void)
1377 platform_driver_unregister(&gpmc_driver);
1381 postcore_initcall(gpmc_init);
1382 module_exit(gpmc_exit);
1384 static int __init omap_gpmc_init(void)
1386 struct omap_hwmod *oh;
1387 struct platform_device *pdev;
1388 char *oh_name = "gpmc";
1391 * if the board boots up with a populated DT, do not
1392 * manually add the device from this initcall
1394 if (of_have_populated_dt())
1397 oh = omap_hwmod_lookup(oh_name);
1399 pr_err("Could not look up %s\n", oh_name);
1403 pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0);
1404 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
1406 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
1408 postcore_initcall(omap_gpmc_init);
1410 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
1415 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1420 for (i = 0; i < GPMC_NR_IRQ; i++)
1421 if (regval & gpmc_client_irq[i].bitmask)
1422 generic_handle_irq(gpmc_client_irq[i].irq);
1424 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1429 #ifdef CONFIG_ARCH_OMAP3
1430 static struct omap3_gpmc_regs gpmc_context;
1432 void omap3_gpmc_save_context(void)
1436 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
1437 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
1438 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
1439 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
1440 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
1441 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
1442 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
1443 for (i = 0; i < GPMC_CS_NUM; i++) {
1444 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
1445 if (gpmc_context.cs_context[i].is_valid) {
1446 gpmc_context.cs_context[i].config1 =
1447 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
1448 gpmc_context.cs_context[i].config2 =
1449 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
1450 gpmc_context.cs_context[i].config3 =
1451 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
1452 gpmc_context.cs_context[i].config4 =
1453 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
1454 gpmc_context.cs_context[i].config5 =
1455 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
1456 gpmc_context.cs_context[i].config6 =
1457 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
1458 gpmc_context.cs_context[i].config7 =
1459 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
1464 void omap3_gpmc_restore_context(void)
1468 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
1469 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
1470 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
1471 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
1472 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
1473 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
1474 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
1475 for (i = 0; i < GPMC_CS_NUM; i++) {
1476 if (gpmc_context.cs_context[i].is_valid) {
1477 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
1478 gpmc_context.cs_context[i].config1);
1479 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
1480 gpmc_context.cs_context[i].config2);
1481 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
1482 gpmc_context.cs_context[i].config3);
1483 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
1484 gpmc_context.cs_context[i].config4);
1485 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
1486 gpmc_context.cs_context[i].config5);
1487 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
1488 gpmc_context.cs_context[i].config6);
1489 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
1490 gpmc_context.cs_context[i].config7);
1494 #endif /* CONFIG_ARCH_OMAP3 */