arch/arm/mach-omap2/emif-common.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * EMIF programming
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Aneesh V <aneesh@ti.com>
   9  */
  10
  11 #include <common.h>
  12 #include <init.h>
  13 #include <net.h>
  14 #include <asm/emif.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/omap_common.h>
  18 #include <asm/omap_sec_common.h>
  19 #include <asm/utils.h>
  20 #include <linux/compiler.h>
  21 #include <asm/ti-common/ti-edma3.h>
  22
  23 static int emif1_enabled = -1, emif2_enabled = -1;
  24
  25 void set_lpmode_selfrefresh(u32 base)
  26 {
  27         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  28         u32 reg;
  29
  30         reg = readl(&emif->emif_pwr_mgmt_ctrl);
  31         reg &= ~EMIF_REG_LP_MODE_MASK;
  32         reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
  33         reg &= ~EMIF_REG_SR_TIM_MASK;
  34         writel(reg, &emif->emif_pwr_mgmt_ctrl);
  35
  36         /* dummy read for the new SR_TIM to be loaded */
  37         readl(&emif->emif_pwr_mgmt_ctrl);
  38 }
  39
  40 void force_emif_self_refresh()
  41 {
  42         set_lpmode_selfrefresh(EMIF1_BASE);
  43         if (!is_dra72x())
  44                 set_lpmode_selfrefresh(EMIF2_BASE);
  45 }
  46
  47 inline u32 emif_num(u32 base)
  48 {
  49         if (base == EMIF1_BASE)
  50                 return 1;
  51         else if (base == EMIF2_BASE)
  52                 return 2;
  53         else
  54                 return 0;
  55 }
  56
  57 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
  58 {
  59         u32 mr;
  60         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  61
  62         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  63         writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  64         if (omap_revision() == OMAP4430_ES2_0)
  65                 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
  66         else
  67                 mr = readl(&emif->emif_lpddr2_mode_reg_data);
  68         debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
  69               cs, mr_addr, mr);
  70         if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
  71             ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  72             ((mr & 0xff000000) >> 24) == (mr & 0xff))
  73                 return mr & 0xff;
  74         else
  75                 return mr;
  76 }
  77
  78 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
  79 {
  80         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  81
  82         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  83         writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  84         writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
  85 }
  86
  87 void emif_reset_phy(u32 base)
  88 {
  89         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  90         u32 iodft;
  91
  92         iodft = readl(&emif->emif_iodft_tlgc);
  93         iodft |= EMIF_REG_RESET_PHY_MASK;
  94         writel(iodft, &emif->emif_iodft_tlgc);
  95 }
  96
  97 static void do_lpddr2_init(u32 base, u32 cs)
  98 {
  99         u32 mr_addr;
 100         const struct lpddr2_mr_regs *mr_regs;
 101
 102         get_lpddr2_mr_regs(&mr_regs);
 103         /* Wait till device auto initialization is complete */
 104         while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
 105                 ;
 106         set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
 107         /*
 108          * tZQINIT = 1 us
 109          * Enough loops assuming a maximum of 2GHz
 110          */
 111
 112         sdelay(2000);
 113
 114         set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
 115         set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
 116
 117         /*
 118          * Enable refresh along with writing MR2
 119          * Encoding of RL in MR2 is (RL - 2)
 120          */
 121         mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
 122         set_mr(base, cs, mr_addr, mr_regs->mr2);
 123
 124         if (mr_regs->mr3 > 0)
 125                 set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
 126 }
 127
 128 static void lpddr2_init(u32 base, const struct emif_regs *regs)
 129 {
 130         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 131
 132         /* Not NVM */
 133         clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
 134
 135         /*
 136          * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
 137          * when EMIF_SDRAM_CONFIG register is written
 138          */
 139         setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 140
 141         /*
 142          * Set the SDRAM_CONFIG and PHY_CTRL for the
 143          * un-locked frequency & default RL
 144          */
 145         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 146         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 147
 148         do_ext_phy_settings(base, regs);
 149
 150         do_lpddr2_init(base, CS0);
 151         if (regs->sdram_config & EMIF_REG_EBANK_MASK)
 152                 do_lpddr2_init(base, CS1);
 153
 154         writel(regs->sdram_config, &emif->emif_sdram_config);
 155         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
 156
 157         /* Enable refresh now */
 158         clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 159
 160         }
 161
 162 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 163 {
 164 }
 165
 166 void emif_update_timings(u32 base, const struct emif_regs *regs)
 167 {
 168         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 169
 170         if (!is_dra7xx())
 171                 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
 172         else
 173                 writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw);
 174
 175         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
 176         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
 177         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
 178         if (omap_revision() == OMAP4430_ES1_0) {
 179                 /* ES1 bug EMIF should be in force idle during freq_update */
 180                 writel(0, &emif->emif_pwr_mgmt_ctrl);
 181         } else {
 182                 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
 183                 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
 184         }
 185         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
 186         writel(regs->zq_config, &emif->emif_zq_config);
 187         writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
 188         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 189
 190         if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
 191                 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
 192                         &emif->emif_l3_config);
 193         } else if (omap_revision() >= OMAP4460_ES1_0) {
 194                 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
 195                         &emif->emif_l3_config);
 196         } else {
 197                 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
 198                         &emif->emif_l3_config);
 199         }
 200 }
 201
 202 #ifndef CONFIG_OMAP44XX
 203 static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
 204 {
 205         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 206
 207         /* keep sdram in self-refresh */
 208         writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
 209                 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 210         __udelay(130);
 211
 212         /*
 213          * Set invert_clkout (if activated)--DDR_PHYCTRL_1
 214          * Invert clock adds an additional half cycle delay on the
 215          * command interface.  The additional half cycle, is usually
 216          * meant to enable leveling in the situation that DQS is later
 217          * than CK on the board.It also helps provide some additional
 218          * margin for leveling.
 219          */
 220         writel(regs->emif_ddr_phy_ctlr_1,
 221                &emif->emif_ddr_phy_ctrl_1);
 222
 223         writel(regs->emif_ddr_phy_ctlr_1,
 224                &emif->emif_ddr_phy_ctrl_1_shdw);
 225         __udelay(130);
 226
 227         writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
 228                & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 229
 230         /* Launch Full leveling */
 231         writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
 232
 233         /* Wait till full leveling is complete */
 234         readl(&emif->emif_rd_wr_lvl_ctl);
 235               __udelay(130);
 236
 237         /* Read data eye leveling no of samples */
 238         config_data_eye_leveling_samples(base);
 239
 240         /*
 241          * Launch 8 incremental WR_LVL- to compensate for
 242          * PHY limitation.
 243          */
 244         writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
 245                &emif->emif_rd_wr_lvl_ctl);
 246
 247         __udelay(130);
 248
 249         /* Launch Incremental leveling */
 250         writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
 251                __udelay(130);
 252 }
 253
 254 static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
 255 {
 256         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 257         u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
 258         u32 reg, i, phy;
 259
 260         emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[6];
 261         phy = readl(&emif->emif_ddr_phy_ctrl_1);
 262
 263         /* Update PHY_REG_RDDQS_RATIO */
 264         emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;
 265         if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK))
 266                 for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
 267                         reg = readl(emif_phy_status++);
 268                         writel(reg, emif_ext_phy_ctrl_reg++);
 269                         writel(reg, emif_ext_phy_ctrl_reg++);
 270                 }
 271
 272         /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
 273         emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
 274         emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[11];
 275         if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK))
 276                 for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
 277                         reg = readl(emif_phy_status++);
 278                         writel(reg, emif_ext_phy_ctrl_reg++);
 279                         writel(reg, emif_ext_phy_ctrl_reg++);
 280                 }
 281
 282         /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
 283         emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
 284         emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[16];
 285         if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK))
 286                 for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
 287                         reg = readl(emif_phy_status++);
 288                         writel(reg, emif_ext_phy_ctrl_reg++);
 289                         writel(reg, emif_ext_phy_ctrl_reg++);
 290                 }
 291
 292         /* Disable Leveling */
 293         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
 294         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 295         writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
 296 }
 297
 298 static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
 299 {
 300         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 301
 302         /* Clear Error Status */
 303         clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36,
 304                         EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
 305                         EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
 306
 307         clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw,
 308                         EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
 309                         EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
 310
 311         /* Disable refreshed before leveling */
 312         clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK,
 313                         EMIF_REG_INITREF_DIS_MASK);
 314
 315         /* Start Full leveling */
 316         writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
 317
 318         __udelay(300);
 319
 320         /* Check for leveling timeout */
 321         if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) {
 322                 printf("Leveling timeout on EMIF%d\n", emif_num(base));
 323                 return;
 324         }
 325
 326         /* Enable refreshes after leveling */
 327         clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 328
 329         debug("HW leveling success\n");
 330         /*
 331          * Update slave ratios in EXT_PHY_CTRLx registers
 332          * as per HW leveling output
 333          */
 334         update_hwleveling_output(base, regs);
 335 }
 336
 337 static void dra7_reset_ddr_data(u32 base, u32 size)
 338 {
 339 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
 340         enable_edma3_clocks();
 341
 342         edma3_fill(EDMA3_BASE, 1, (void *)base, 0, size);
 343
 344         disable_edma3_clocks();
 345 #else
 346         memset((void *)base, 0, size);
 347 #endif
 348 }
 349
 350 static void dra7_enable_ecc(u32 base, const struct emif_regs *regs)
 351 {
 352         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 353         u32 rgn, rgn_start, size, ctrl_reg;
 354
 355         /* ECC available only on dra76x EMIF1 */
 356         if ((base != EMIF1_BASE) || !is_dra76x())
 357                 return;
 358
 359         if (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK) {
 360                 /* Disable high-order interleaving */
 361                 clrbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);
 362
 363 #ifdef CONFIG_DRA7XX
 364                 /* Clear the status flags and other history */
 365                 writel(readl(&emif->emif_1b_ecc_err_cnt),
 366                        &emif->emif_1b_ecc_err_cnt);
 367                 writel(0xffffffff, &emif->emif_1b_ecc_err_dist_1);
 368                 writel(0x2, &emif->emif_1b_ecc_err_addr_log);
 369                 writel(0x1, &emif->emif_2b_ecc_err_addr_log);
 370                 writel(EMIF_INT_WR_ECC_ERR_SYS_MASK |
 371                        EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK |
 372                        EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK,
 373                        &emif->emif_irqstatus_sys);
 374 #endif
 375                 writel(regs->emif_ecc_address_range_1,
 376                        &emif->emif_ecc_address_range_1);
 377                 writel(regs->emif_ecc_address_range_2,
 378                        &emif->emif_ecc_address_range_2);
 379
 380                 /* Disable RMW and ECC verification for read accesses */
 381                 ctrl_reg = (regs->emif_ecc_ctrl_reg &
 382                             ~EMIF_ECC_REG_RMW_EN_MASK) |
 383                            EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK;
 384                 writel(ctrl_reg, &emif->emif_ecc_ctrl_reg);
 385
 386                 /* Set region1 memory with 0 */
 387                 rgn_start = (regs->emif_ecc_address_range_1 &
 388                              EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
 389                 rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
 390                 size = (regs->emif_ecc_address_range_1 &
 391                         EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
 392
 393                 if (regs->emif_ecc_ctrl_reg &
 394                     EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK)
 395                         dra7_reset_ddr_data(rgn, size);
 396
 397                 /* Set region2 memory with 0 */
 398                 rgn_start = (regs->emif_ecc_address_range_2 &
 399                              EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
 400                 rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
 401                 size = (regs->emif_ecc_address_range_2 &
 402                         EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
 403
 404                 if (regs->emif_ecc_ctrl_reg &
 405                     EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK)
 406                         dra7_reset_ddr_data(rgn, size);
 407
 408                 /* Default value enables RMW and ECC verification */
 409                 writel(regs->emif_ecc_ctrl_reg, &emif->emif_ecc_ctrl_reg);
 410         }
 411 }
 412
 413 static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
 414 {
 415         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 416
 417         if (warm_reset()) {
 418                 emif_reset_phy(base);
 419                 writel(0x0, &emif->emif_pwr_mgmt_ctrl);
 420         }
 421         do_ext_phy_settings(base, regs);
 422
 423         writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
 424                &emif->emif_sdram_ref_ctrl);
 425         /* Update timing registers */
 426         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
 427         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
 428         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
 429
 430         writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config);
 431         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 432         writel(regs->zq_config, &emif->emif_zq_config);
 433         writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
 434         writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
 435         writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
 436
 437         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 438         writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh);
 439
 440         writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
 441
 442         writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 443         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 444
 445         __udelay(1000);
 446
 447         writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
 448
 449         if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) {
 450                 /*
 451                  * Perform Dummy ECC setup just to allow hardware
 452                  * leveling of ECC memories
 453                  */
 454                 if (is_dra76x() && (base == EMIF1_BASE) &&
 455                     (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK)) {
 456                         writel(0, &emif->emif_ecc_address_range_1);
 457                         writel(0, &emif->emif_ecc_address_range_2);
 458                         writel(EMIF_ECC_CTRL_REG_ECC_EN_MASK |
 459                                EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK,
 460                                &emif->emif_ecc_ctrl_reg);
 461                 }
 462
 463                 dra7_ddr3_leveling(base, regs);
 464
 465                 /* Disable ECC */
 466                 if (is_dra76x())
 467                         writel(0, &emif->emif_ecc_ctrl_reg);
 468         }
 469
 470         /* Enable ECC as necessary */
 471         dra7_enable_ecc(base, regs);
 472 }
 473
 474 static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
 475 {
 476         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 477
 478         writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
 479         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 480         /*
 481          * Set SDRAM_CONFIG and PHY control registers to locked frequency
 482          * and RL =7. As the default values of the Mode Registers are not
 483          * defined, contents of mode Registers must be fully initialized.
 484          * H/W takes care of this initialization
 485          */
 486         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 487
 488         /* Update timing registers */
 489         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
 490         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
 491         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
 492
 493         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 494
 495         writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 496         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 497         do_ext_phy_settings(base, regs);
 498
 499         writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
 500         omap5_ddr3_leveling(base, regs);
 501 }
 502
 503 static void ddr3_init(u32 base, const struct emif_regs *regs)
 504 {
 505         if (is_omap54xx())
 506                 omap5_ddr3_init(base, regs);
 507         else
 508                 dra7_ddr3_init(base, regs);
 509 }
 510 #endif
 511
 512 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 513 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
 514
 515 /*
 516  * Organization and refresh requirements for LPDDR2 devices of different
 517  * types and densities. Derived from JESD209-2 section 2.4
 518  */
 519 const struct lpddr2_addressing addressing_table[] = {
 520         /* Banks tREFIx10     rowx32,rowx16      colx32,colx16  density */
 521         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
 522         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
 523         {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
 524         {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
 525         {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
 526         {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
 527         {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
 528         {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
 529         {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
 530         {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
 531 };
 532
 533 static const u32 lpddr2_density_2_size_in_mbytes[] = {
 534         8,                      /* 64Mb */
 535         16,                     /* 128Mb */
 536         32,                     /* 256Mb */
 537         64,                     /* 512Mb */
 538         128,                    /* 1Gb   */
 539         256,                    /* 2Gb   */
 540         512,                    /* 4Gb   */
 541         1024,                   /* 8Gb   */
 542         2048,                   /* 16Gb  */
 543         4096                    /* 32Gb  */
 544 };
 545
 546 /*
 547  * Calculate the period of DDR clock from frequency value and set the
 548  * denominator and numerator in global variables for easy access later
 549  */
 550 static void set_ddr_clk_period(u32 freq)
 551 {
 552         /*
 553          * period = 1/freq
 554          * period_in_ns = 10^9/freq
 555          */
 556         *T_num = 1000000000;
 557         *T_den = freq;
 558         cancel_out(T_num, T_den, 200);
 559
 560 }
 561
 562 /*
 563  * Convert time in nano seconds to number of cycles of DDR clock
 564  */
 565 static inline u32 ns_2_cycles(u32 ns)
 566 {
 567         return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
 568 }
 569
 570 /*
 571  * ns_2_cycles with the difference that the time passed is 2 times the actual
 572  * value(to avoid fractions). The cycles returned is for the original value of
 573  * the timing parameter
 574  */
 575 static inline u32 ns_x2_2_cycles(u32 ns)
 576 {
 577         return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
 578 }
 579
 580 /*
 581  * Find addressing table index based on the device's type(S2 or S4) and
 582  * density
 583  */
 584 s8 addressing_table_index(u8 type, u8 density, u8 width)
 585 {
 586         u8 index;
 587         if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
 588                 return -1;
 589
 590         /*
 591          * Look at the way ADDR_TABLE_INDEX* values have been defined
 592          * in emif.h compared to LPDDR2_DENSITY_* values
 593          * The table is layed out in the increasing order of density
 594          * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
 595          * at the end
 596          */
 597         if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
 598                 index = ADDR_TABLE_INDEX1GS2;
 599         else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
 600                 index = ADDR_TABLE_INDEX2GS2;
 601         else
 602                 index = density;
 603
 604         debug("emif: addressing table index %d\n", index);
 605
 606         return index;
 607 }
 608
 609 /*
 610  * Find the the right timing table from the array of timing
 611  * tables of the device using DDR clock frequency
 612  */
 613 static const struct lpddr2_ac_timings *get_timings_table(const struct
 614                         lpddr2_ac_timings *const *device_timings,
 615                         u32 freq)
 616 {
 617         u32 i, temp, freq_nearest;
 618         const struct lpddr2_ac_timings *timings = 0;
 619
 620         emif_assert(freq <= MAX_LPDDR2_FREQ);
 621         emif_assert(device_timings);
 622
 623         /*
 624          * Start with the maximum allowed frequency - that is always safe
 625          */
 626         freq_nearest = MAX_LPDDR2_FREQ;
 627         /*
 628          * Find the timings table that has the max frequency value:
 629          *   i.  Above or equal to the DDR frequency - safe
 630          *   ii. The lowest that satisfies condition (i) - optimal
 631          */
 632         for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
 633                 temp = device_timings[i]->max_freq;
 634                 if ((temp >= freq) && (temp <= freq_nearest)) {
 635                         freq_nearest = temp;
 636                         timings = device_timings[i];
 637                 }
 638         }
 639         debug("emif: timings table: %d\n", freq_nearest);
 640         return timings;
 641 }
 642
 643 /*
 644  * Finds the value of emif_sdram_config_reg
 645  * All parameters are programmed based on the device on CS0.
 646  * If there is a device on CS1, it will be same as that on CS0 or
 647  * it will be NVM. We don't support NVM yet.
 648  * If cs1_device pointer is NULL it is assumed that there is no device
 649  * on CS1
 650  */
 651 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
 652                                 const struct lpddr2_device_details *cs1_device,
 653                                 const struct lpddr2_addressing *addressing,
 654                                 u8 RL)
 655 {
 656         u32 config_reg = 0;
 657
 658         config_reg |=  (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
 659         config_reg |=  EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
 660                         EMIF_REG_IBANK_POS_SHIFT;
 661
 662         config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
 663
 664         config_reg |= RL << EMIF_REG_CL_SHIFT;
 665
 666         config_reg |= addressing->row_sz[cs0_device->io_width] <<
 667                         EMIF_REG_ROWSIZE_SHIFT;
 668
 669         config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
 670
 671         config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
 672                         EMIF_REG_EBANK_SHIFT;
 673
 674         config_reg |= addressing->col_sz[cs0_device->io_width] <<
 675                         EMIF_REG_PAGESIZE_SHIFT;
 676
 677         return config_reg;
 678 }
 679
 680 static u32 get_sdram_ref_ctrl(u32 freq,
 681                               const struct lpddr2_addressing *addressing)
 682 {
 683         u32 ref_ctrl = 0, val = 0, freq_khz;
 684         freq_khz = freq / 1000;
 685         /*
 686          * refresh rate to be set is 'tREFI * freq in MHz
 687          * division by 10000 to account for khz and x10 in t_REFI_us_x10
 688          */
 689         val = addressing->t_REFI_us_x10 * freq_khz / 10000;
 690         ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
 691
 692         return ref_ctrl;
 693 }
 694
 695 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
 696                                const struct lpddr2_min_tck *min_tck,
 697                                const struct lpddr2_addressing *addressing)
 698 {
 699         u32 tim1 = 0, val = 0;
 700         val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
 701         tim1 |= val << EMIF_REG_T_WTR_SHIFT;
 702
 703         if (addressing->num_banks == BANKS8)
 704                 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
 705                                                         (4 * (*T_num)) - 1;
 706         else
 707                 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
 708
 709         tim1 |= val << EMIF_REG_T_RRD_SHIFT;
 710
 711         val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
 712         tim1 |= val << EMIF_REG_T_RC_SHIFT;
 713
 714         val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
 715         tim1 |= val << EMIF_REG_T_RAS_SHIFT;
 716
 717         val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
 718         tim1 |= val << EMIF_REG_T_WR_SHIFT;
 719
 720         val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
 721         tim1 |= val << EMIF_REG_T_RCD_SHIFT;
 722
 723         val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
 724         tim1 |= val << EMIF_REG_T_RP_SHIFT;
 725
 726         return tim1;
 727 }
 728
 729 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
 730                                const struct lpddr2_min_tck *min_tck)
 731 {
 732         u32 tim2 = 0, val = 0;
 733         val = max(min_tck->tCKE, timings->tCKE) - 1;
 734         tim2 |= val << EMIF_REG_T_CKE_SHIFT;
 735
 736         val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
 737         tim2 |= val << EMIF_REG_T_RTP_SHIFT;
 738
 739         /*
 740          * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
 741          * same value
 742          */
 743         val = ns_2_cycles(timings->tXSR) - 1;
 744         tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
 745         tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
 746
 747         val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
 748         tim2 |= val << EMIF_REG_T_XP_SHIFT;
 749
 750         return tim2;
 751 }
 752
 753 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
 754                                const struct lpddr2_min_tck *min_tck,
 755                                const struct lpddr2_addressing *addressing)
 756 {
 757         u32 tim3 = 0, val = 0;
 758         val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
 759         tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
 760
 761         val = ns_2_cycles(timings->tRFCab) - 1;
 762         tim3 |= val << EMIF_REG_T_RFC_SHIFT;
 763
 764         val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
 765         tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
 766
 767         val = ns_2_cycles(timings->tZQCS) - 1;
 768         tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
 769
 770         val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
 771         tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
 772
 773         return tim3;
 774 }
 775
 776 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
 777                              const struct lpddr2_addressing *addressing,
 778                              u8 volt_ramp)
 779 {
 780         u32 zq = 0, val = 0;
 781         if (volt_ramp)
 782                 val =
 783                     EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
 784                     addressing->t_REFI_us_x10;
 785         else
 786                 val =
 787                     EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
 788                     addressing->t_REFI_us_x10;
 789         zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
 790
 791         zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
 792
 793         zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
 794
 795         zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
 796
 797         /*
 798          * Assuming that two chipselects have a single calibration resistor
 799          * If there are indeed two calibration resistors, then this flag should
 800          * be enabled to take advantage of dual calibration feature.
 801          * This data should ideally come from board files. But considering
 802          * that none of the boards today have calibration resistors per CS,
 803          * it would be an unnecessary overhead.
 804          */
 805         zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
 806
 807         zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
 808
 809         zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
 810
 811         return zq;
 812 }
 813
 814 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
 815                                  const struct lpddr2_addressing *addressing,
 816                                  u8 is_derated)
 817 {
 818         u32 alert = 0, interval;
 819         interval =
 820             TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
 821         if (is_derated)
 822                 interval *= 4;
 823         alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
 824
 825         alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
 826
 827         alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
 828
 829         alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
 830
 831         alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
 832
 833         alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
 834
 835         return alert;
 836 }
 837
 838 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
 839 {
 840         u32 idle = 0, val = 0;
 841         if (volt_ramp)
 842                 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
 843         else
 844                 /*Maximum value in normal conditions - suggested by hw team */
 845                 val = 0x1FF;
 846         idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
 847
 848         idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
 849
 850         return idle;
 851 }
 852
 853 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
 854 {
 855         u32 phy = 0, val = 0;
 856
 857         phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
 858
 859         if (freq <= 100000000)
 860                 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
 861         else if (freq <= 200000000)
 862                 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
 863         else
 864                 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
 865         phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
 866
 867         /* Other fields are constant magic values. Hardcode them together */
 868         phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
 869                 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
 870
 871         return phy;
 872 }
 873
 874 static u32 get_emif_mem_size(u32 base)
 875 {
 876         u32 size_mbytes = 0, temp;
 877         struct emif_device_details dev_details;
 878         struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
 879         u32 emif_nr = emif_num(base);
 880
 881         emif_reset_phy(base);
 882         dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
 883                                                 &cs0_dev_details);
 884         dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
 885                                                 &cs1_dev_details);
 886         emif_reset_phy(base);
 887
 888         if (dev_details.cs0_device_details) {
 889                 temp = dev_details.cs0_device_details->density;
 890                 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
 891         }
 892
 893         if (dev_details.cs1_device_details) {
 894                 temp = dev_details.cs1_device_details->density;
 895                 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
 896         }
 897         /* convert to bytes */
 898         return size_mbytes << 20;
 899 }
 900
 901 /* Gets the encoding corresponding to a given DMM section size */
 902 u32 get_dmm_section_size_map(u32 section_size)
 903 {
 904         /*
 905          * Section size mapping:
 906          * 0x0: 16-MiB section
 907          * 0x1: 32-MiB section
 908          * 0x2: 64-MiB section
 909          * 0x3: 128-MiB section
 910          * 0x4: 256-MiB section
 911          * 0x5: 512-MiB section
 912          * 0x6: 1-GiB section
 913          * 0x7: 2-GiB section
 914          */
 915         section_size >>= 24; /* divide by 16 MB */
 916         return log_2_n_round_down(section_size);
 917 }
 918
 919 static void emif_calculate_regs(
 920                 const struct emif_device_details *emif_dev_details,
 921                 u32 freq, struct emif_regs *regs)
 922 {
 923         u32 temp, sys_freq;
 924         const struct lpddr2_addressing *addressing;
 925         const struct lpddr2_ac_timings *timings;
 926         const struct lpddr2_min_tck *min_tck;
 927         const struct lpddr2_device_details *cs0_dev_details =
 928                                         emif_dev_details->cs0_device_details;
 929         const struct lpddr2_device_details *cs1_dev_details =
 930                                         emif_dev_details->cs1_device_details;
 931         const struct lpddr2_device_timings *cs0_dev_timings =
 932                                         emif_dev_details->cs0_device_timings;
 933
 934         emif_assert(emif_dev_details);
 935         emif_assert(regs);
 936         /*
 937          * You can not have a device on CS1 without one on CS0
 938          * So configuring EMIF without a device on CS0 doesn't
 939          * make sense
 940          */
 941         emif_assert(cs0_dev_details);
 942         emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
 943         /*
 944          * If there is a device on CS1 it should be same type as CS0
 945          * (or NVM. But NVM is not supported in this driver yet)
 946          */
 947         emif_assert((cs1_dev_details == NULL) ||
 948                     (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
 949                     (cs0_dev_details->type == cs1_dev_details->type));
 950         emif_assert(freq <= MAX_LPDDR2_FREQ);
 951
 952         set_ddr_clk_period(freq);
 953
 954         /*
 955          * The device on CS0 is used for all timing calculations
 956          * There is only one set of registers for timings per EMIF. So, if the
 957          * second CS(CS1) has a device, it should have the same timings as the
 958          * device on CS0
 959          */
 960         timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
 961         emif_assert(timings);
 962         min_tck = cs0_dev_timings->min_tck;
 963
 964         temp = addressing_table_index(cs0_dev_details->type,
 965                                       cs0_dev_details->density,
 966                                       cs0_dev_details->io_width);
 967
 968         emif_assert((temp >= 0));
 969         addressing = &(addressing_table[temp]);
 970         emif_assert(addressing);
 971
 972         sys_freq = get_sys_clk_freq();
 973
 974         regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
 975                                                         cs1_dev_details,
 976                                                         addressing, RL_BOOT);
 977
 978         regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
 979                                                 cs1_dev_details,
 980                                                 addressing, RL_FINAL);
 981
 982         regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
 983
 984         regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
 985
 986         regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
 987
 988         regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
 989
 990         regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
 991
 992         regs->temp_alert_config =
 993             get_temp_alert_config(cs1_dev_details, addressing, 0);
 994
 995         regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
 996                                             LPDDR2_VOLTAGE_STABLE);
 997
 998         regs->emif_ddr_phy_ctlr_1_init =
 999                         get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
1000
1001         regs->emif_ddr_phy_ctlr_1 =
1002                         get_ddr_phy_ctrl_1(freq, RL_FINAL);
1003
1004         regs->freq = freq;
1005
1006         print_timing_reg(regs->sdram_config_init);
1007         print_timing_reg(regs->sdram_config);
1008         print_timing_reg(regs->ref_ctrl);
1009         print_timing_reg(regs->sdram_tim1);
1010         print_timing_reg(regs->sdram_tim2);
1011         print_timing_reg(regs->sdram_tim3);
1012         print_timing_reg(regs->read_idle_ctrl);
1013         print_timing_reg(regs->temp_alert_config);
1014         print_timing_reg(regs->zq_config);
1015         print_timing_reg(regs->emif_ddr_phy_ctlr_1);
1016         print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
1017 }
1018 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1019
1020 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
1021 const char *get_lpddr2_type(u8 type_id)
1022 {
1023         switch (type_id) {
1024         case LPDDR2_TYPE_S4:
1025                 return "LPDDR2-S4";
1026         case LPDDR2_TYPE_S2:
1027                 return "LPDDR2-S2";
1028         default:
1029                 return NULL;
1030         }
1031 }
1032
1033 const char *get_lpddr2_io_width(u8 width_id)
1034 {
1035         switch (width_id) {
1036         case LPDDR2_IO_WIDTH_8:
1037                 return "x8";
1038         case LPDDR2_IO_WIDTH_16:
1039                 return "x16";
1040         case LPDDR2_IO_WIDTH_32:
1041                 return "x32";
1042         default:
1043                 return NULL;
1044         }
1045 }
1046
1047 const char *get_lpddr2_manufacturer(u32 manufacturer)
1048 {
1049         switch (manufacturer) {
1050         case LPDDR2_MANUFACTURER_SAMSUNG:
1051                 return "Samsung";
1052         case LPDDR2_MANUFACTURER_QIMONDA:
1053                 return "Qimonda";
1054         case LPDDR2_MANUFACTURER_ELPIDA:
1055                 return "Elpida";
1056         case LPDDR2_MANUFACTURER_ETRON:
1057                 return "Etron";
1058         case LPDDR2_MANUFACTURER_NANYA:
1059                 return "Nanya";
1060         case LPDDR2_MANUFACTURER_HYNIX:
1061                 return "Hynix";
1062         case LPDDR2_MANUFACTURER_MOSEL:
1063                 return "Mosel";
1064         case LPDDR2_MANUFACTURER_WINBOND:
1065                 return "Winbond";
1066         case LPDDR2_MANUFACTURER_ESMT:
1067                 return "ESMT";
1068         case LPDDR2_MANUFACTURER_SPANSION:
1069                 return "Spansion";
1070         case LPDDR2_MANUFACTURER_SST:
1071                 return "SST";
1072         case LPDDR2_MANUFACTURER_ZMOS:
1073                 return "ZMOS";
1074         case LPDDR2_MANUFACTURER_INTEL:
1075                 return "Intel";
1076         case LPDDR2_MANUFACTURER_NUMONYX:
1077                 return "Numonyx";
1078         case LPDDR2_MANUFACTURER_MICRON:
1079                 return "Micron";
1080         default:
1081                 return NULL;
1082         }
1083 }
1084
1085 static void display_sdram_details(u32 emif_nr, u32 cs,
1086                                   struct lpddr2_device_details *device)
1087 {
1088         const char *mfg_str;
1089         const char *type_str;
1090         char density_str[10];
1091         u32 density;
1092
1093         debug("EMIF%d CS%d\t", emif_nr, cs);
1094
1095         if (!device) {
1096                 debug("None\n");
1097                 return;
1098         }
1099
1100         mfg_str = get_lpddr2_manufacturer(device->manufacturer);
1101         type_str = get_lpddr2_type(device->type);
1102
1103         density = lpddr2_density_2_size_in_mbytes[device->density];
1104         if ((density / 1024 * 1024) == density) {
1105                 density /= 1024;
1106                 sprintf(density_str, "%d GB", density);
1107         } else
1108                 sprintf(density_str, "%d MB", density);
1109         if (mfg_str && type_str)
1110                 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
1111 }
1112
1113 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
1114                                   struct lpddr2_device_details *lpddr2_device)
1115 {
1116         u32 mr = 0, temp;
1117
1118         mr = get_mr(base, cs, LPDDR2_MR0);
1119         if (mr > 0xFF) {
1120                 /* Mode register value bigger than 8 bit */
1121                 return 0;
1122         }
1123
1124         temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
1125         if (temp) {
1126                 /* Not SDRAM */
1127                 return 0;
1128         }
1129         temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
1130
1131         if (temp) {
1132                 /* DNV supported - But DNV is only supported for NVM */
1133                 return 0;
1134         }
1135
1136         mr = get_mr(base, cs, LPDDR2_MR4);
1137         if (mr > 0xFF) {
1138                 /* Mode register value bigger than 8 bit */
1139                 return 0;
1140         }
1141
1142         mr = get_mr(base, cs, LPDDR2_MR5);
1143         if (mr > 0xFF) {
1144                 /* Mode register value bigger than 8 bit */
1145                 return 0;
1146         }
1147
1148         if (!get_lpddr2_manufacturer(mr)) {
1149                 /* Manufacturer not identified */
1150                 return 0;
1151         }
1152         lpddr2_device->manufacturer = mr;
1153
1154         mr = get_mr(base, cs, LPDDR2_MR6);
1155         if (mr >= 0xFF) {
1156                 /* Mode register value bigger than 8 bit */
1157                 return 0;
1158         }
1159
1160         mr = get_mr(base, cs, LPDDR2_MR7);
1161         if (mr >= 0xFF) {
1162                 /* Mode register value bigger than 8 bit */
1163                 return 0;
1164         }
1165
1166         mr = get_mr(base, cs, LPDDR2_MR8);
1167         if (mr >= 0xFF) {
1168                 /* Mode register value bigger than 8 bit */
1169                 return 0;
1170         }
1171
1172         temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
1173         if (!get_lpddr2_type(temp)) {
1174                 /* Not SDRAM */
1175                 return 0;
1176         }
1177         lpddr2_device->type = temp;
1178
1179         temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
1180         if (temp > LPDDR2_DENSITY_32Gb) {
1181                 /* Density not supported */
1182                 return 0;
1183         }
1184         lpddr2_device->density = temp;
1185
1186         temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
1187         if (!get_lpddr2_io_width(temp)) {
1188                 /* IO width unsupported value */
1189                 return 0;
1190         }
1191         lpddr2_device->io_width = temp;
1192
1193         /*
1194          * If all the above tests pass we should
1195          * have a device on this chip-select
1196          */
1197         return 1;
1198 }
1199
1200 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
1201                         struct lpddr2_device_details *lpddr2_dev_details)
1202 {
1203         u32 phy;
1204         u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
1205
1206         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1207
1208         if (!lpddr2_dev_details)
1209                 return NULL;
1210
1211         /* Do the minimum init for mode register accesses */
1212         if (!(running_from_sdram() || warm_reset())) {
1213                 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
1214                 writel(phy, &emif->emif_ddr_phy_ctrl_1);
1215         }
1216
1217         if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
1218                 return NULL;
1219
1220         display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
1221
1222         return lpddr2_dev_details;
1223 }
1224 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1225
1226 static void do_sdram_init(u32 base)
1227 {
1228         const struct emif_regs *regs;
1229         u32 in_sdram, emif_nr;
1230
1231         debug(">>do_sdram_init() %x\n", base);
1232
1233         in_sdram = running_from_sdram();
1234         emif_nr = (base == EMIF1_BASE) ? 1 : 2;
1235
1236 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1237         emif_get_reg_dump(emif_nr, &regs);
1238         if (!regs) {
1239                 debug("EMIF: reg dump not provided\n");
1240                 return;
1241         }
1242 #else
1243         /*
1244          * The user has not provided the register values. We need to
1245          * calculate it based on the timings and the DDR frequency
1246          */
1247         struct emif_device_details dev_details;
1248         struct emif_regs calculated_regs;
1249
1250         /*
1251          * Get device details:
1252          * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1253          * - Obtained from user otherwise
1254          */
1255         struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1256         emif_reset_phy(base);
1257         dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
1258                                                 &cs0_dev_details);
1259         dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
1260                                                 &cs1_dev_details);
1261         emif_reset_phy(base);
1262
1263         /* Return if no devices on this EMIF */
1264         if (!dev_details.cs0_device_details &&
1265             !dev_details.cs1_device_details) {
1266                 return;
1267         }
1268
1269         /*
1270          * Get device timings:
1271          * - Default timings specified by JESD209-2 if
1272          *   CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1273          * - Obtained from user otherwise
1274          */
1275         emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1276                                 &dev_details.cs1_device_timings);
1277
1278         /* Calculate the register values */
1279         emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
1280         regs = &calculated_regs;
1281 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1282
1283         /*
1284          * Initializing the DDR device can not happen from SDRAM.
1285          * Changing the timing registers in EMIF can happen(going from one
1286          * OPP to another)
1287          */
1288         if (!in_sdram && (!warm_reset() || is_dra7xx())) {
1289                 if (emif_sdram_type(regs->sdram_config) ==
1290                     EMIF_SDRAM_TYPE_LPDDR2)
1291                         lpddr2_init(base, regs);
1292 #ifndef CONFIG_OMAP44XX
1293                 else
1294                         ddr3_init(base, regs);
1295 #endif
1296         }
1297 #ifdef CONFIG_OMAP54XX
1298         if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
1299             EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
1300                 set_lpmode_selfrefresh(base);
1301                 emif_reset_phy(base);
1302                 omap5_ddr3_leveling(base, regs);
1303         }
1304 #endif
1305
1306         /* Write to the shadow registers */
1307         emif_update_timings(base, regs);
1308
1309         debug("<<do_sdram_init() %x\n", base);
1310 }
1311
1312 void emif_post_init_config(u32 base)
1313 {
1314         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1315         u32 omap_rev = omap_revision();
1316
1317         /* reset phy on ES2.0 */
1318         if (omap_rev == OMAP4430_ES2_0)
1319                 emif_reset_phy(base);
1320
1321         /* Put EMIF back in smart idle on ES1.0 */
1322         if (omap_rev == OMAP4430_ES1_0)
1323                 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1324 }
1325
1326 void dmm_init(u32 base)
1327 {
1328         const struct dmm_lisa_map_regs *lisa_map_regs;
1329         u32 i, section, valid;
1330
1331 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1332         emif_get_dmm_regs(&lisa_map_regs);
1333 #else
1334         u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1335         u32 section_cnt, sys_addr;
1336         struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1337
1338         mapped_size = 0;
1339         section_cnt = 3;
1340         sys_addr = CONFIG_SYS_SDRAM_BASE;
1341         emif1_size = get_emif_mem_size(EMIF1_BASE);
1342         emif2_size = get_emif_mem_size(EMIF2_BASE);
1343         debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1344
1345         if (!emif1_size && !emif2_size)
1346                 return;
1347
1348         /* symmetric interleaved section */
1349         if (emif1_size && emif2_size) {
1350                 mapped_size = min(emif1_size, emif2_size);
1351                 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1352                 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
1353                 /* only MSB */
1354                 section_map |= (sys_addr >> 24) <<
1355                                 EMIF_SYS_ADDR_SHIFT;
1356                 section_map |= get_dmm_section_size_map(mapped_size * 2)
1357                                 << EMIF_SYS_SIZE_SHIFT;
1358                 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1359                 emif1_size -= mapped_size;
1360                 emif2_size -= mapped_size;
1361                 sys_addr += (mapped_size * 2);
1362                 section_cnt--;
1363         }
1364
1365         /*
1366          * Single EMIF section(we can have a maximum of 1 single EMIF
1367          * section- either EMIF1 or EMIF2 or none, but not both)
1368          */
1369         if (emif1_size) {
1370                 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1371                 section_map |= get_dmm_section_size_map(emif1_size)
1372                                 << EMIF_SYS_SIZE_SHIFT;
1373                 /* only MSB */
1374                 section_map |= (mapped_size >> 24) <<
1375                                 EMIF_SDRC_ADDR_SHIFT;
1376                 /* only MSB */
1377                 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
1378                 section_cnt--;
1379         }
1380         if (emif2_size) {
1381                 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1382                 section_map |= get_dmm_section_size_map(emif2_size) <<
1383                                 EMIF_SYS_SIZE_SHIFT;
1384                 /* only MSB */
1385                 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
1386                 /* only MSB */
1387                 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
1388                 section_cnt--;
1389         }
1390
1391         if (section_cnt == 2) {
1392                 /* Only 1 section - either symmetric or single EMIF */
1393                 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1394                 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1395                 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1396         } else {
1397                 /* 2 sections - 1 symmetric, 1 single EMIF */
1398                 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1399                 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1400         }
1401
1402         /* TRAP for invalid TILER mappings in section 0 */
1403         lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1404
1405         if (omap_revision() >= OMAP4460_ES1_0)
1406                 lis_map_regs_calculated.is_ma_present = 1;
1407
1408         lisa_map_regs = &lis_map_regs_calculated;
1409 #endif
1410         struct dmm_lisa_map_regs *hw_lisa_map_regs =
1411             (struct dmm_lisa_map_regs *)base;
1412
1413         writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1414         writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1415         writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1416         writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1417
1418         writel(lisa_map_regs->dmm_lisa_map_3,
1419                 &hw_lisa_map_regs->dmm_lisa_map_3);
1420         writel(lisa_map_regs->dmm_lisa_map_2,
1421                 &hw_lisa_map_regs->dmm_lisa_map_2);
1422         writel(lisa_map_regs->dmm_lisa_map_1,
1423                 &hw_lisa_map_regs->dmm_lisa_map_1);
1424         writel(lisa_map_regs->dmm_lisa_map_0,
1425                 &hw_lisa_map_regs->dmm_lisa_map_0);
1426
1427         if (lisa_map_regs->is_ma_present) {
1428                 hw_lisa_map_regs =
1429                     (struct dmm_lisa_map_regs *)MA_BASE;
1430
1431                 writel(lisa_map_regs->dmm_lisa_map_3,
1432                         &hw_lisa_map_regs->dmm_lisa_map_3);
1433                 writel(lisa_map_regs->dmm_lisa_map_2,
1434                         &hw_lisa_map_regs->dmm_lisa_map_2);
1435                 writel(lisa_map_regs->dmm_lisa_map_1,
1436                         &hw_lisa_map_regs->dmm_lisa_map_1);
1437                 writel(lisa_map_regs->dmm_lisa_map_0,
1438                         &hw_lisa_map_regs->dmm_lisa_map_0);
1439
1440                 setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);
1441         }
1442
1443         /*
1444          * EMIF should be configured only when
1445          * memory is mapped on it. Using emif1_enabled
1446          * and emif2_enabled variables for this.
1447          */
1448         emif1_enabled = 0;
1449         emif2_enabled = 0;
1450         for (i = 0; i < 4; i++) {
1451                 section = __raw_readl(DMM_BASE + i*4);
1452                 valid = (section & EMIF_SDRC_MAP_MASK) >>
1453                         (EMIF_SDRC_MAP_SHIFT);
1454                 if (valid == 3) {
1455                         emif1_enabled = 1;
1456                         emif2_enabled = 1;
1457                         break;
1458                 }
1459
1460                 if (valid == 1)
1461                         emif1_enabled = 1;
1462
1463                 if (valid == 2)
1464                         emif2_enabled = 1;
1465         }
1466 }
1467
1468 static void do_bug0039_workaround(u32 base)
1469 {
1470         u32 val, i, clkctrl;
1471         struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
1472         const struct read_write_regs *bug_00339_regs;
1473         u32 iterations;
1474         u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
1475         u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
1476
1477         if (is_dra7xx())
1478                 phy_status_base++;
1479
1480         bug_00339_regs = get_bug_regs(&iterations);
1481
1482         /* Put EMIF in to idle */
1483         clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
1484         __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
1485
1486         /* Copy the phy status registers in to phy ctrl shadow registers */
1487         for (i = 0; i < iterations; i++) {
1488                 val = __raw_readl(phy_status_base +
1489                                   bug_00339_regs[i].read_reg - 1);
1490
1491                 __raw_writel(val, phy_ctrl_base +
1492                              ((bug_00339_regs[i].write_reg - 1) << 1));
1493
1494                 __raw_writel(val, phy_ctrl_base +
1495                              (bug_00339_regs[i].write_reg << 1) - 1);
1496         }
1497
1498         /* Disable leveling */
1499         writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
1500
1501         __raw_writel(clkctrl,  (*prcm)->cm_memif_clkstctrl);
1502 }
1503
1504 /*
1505  * SDRAM initialization:
1506  * SDRAM initialization has two parts:
1507  * 1. Configuring the SDRAM device
1508  * 2. Update the AC timings related parameters in the EMIF module
1509  * (1) should be done only once and should not be done while we are
1510  * running from SDRAM.
1511  * (2) can and should be done more than once if OPP changes.
1512  * Particularly, this may be needed when we boot without SPL and
1513  * and using Configuration Header(CH). ROM code supports only at 50% OPP
1514  * at boot (low power boot). So u-boot has to switch to OPP100 and update
1515  * the frequency. So,
1516  * Doing (1) and (2) makes sense - first time initialization
1517  * Doing (2) and not (1) makes sense - OPP change (when using CH)
1518  * Doing (1) and not (2) doen't make sense
1519  * See do_sdram_init() for the details
1520  */
1521 void sdram_init(void)
1522 {
1523         u32 in_sdram, size_prog, size_detect;
1524         struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
1525         u32 sdram_type = emif_sdram_type(emif->emif_sdram_config);
1526
1527         debug(">>sdram_init()\n");
1528
1529         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1530                 return;
1531
1532         in_sdram = running_from_sdram();
1533         debug("in_sdram = %d\n", in_sdram);
1534
1535         if (!in_sdram) {
1536                 if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
1537                         bypass_dpll((*prcm)->cm_clkmode_dpll_core);
1538                 else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
1539                         writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
1540         }
1541
1542         if (!in_sdram)
1543                 dmm_init(DMM_BASE);
1544
1545         if (emif1_enabled)
1546                 do_sdram_init(EMIF1_BASE);
1547
1548         if (emif2_enabled)
1549                 do_sdram_init(EMIF2_BASE);
1550
1551         if (!(in_sdram || warm_reset())) {
1552                 if (emif1_enabled)
1553                         emif_post_init_config(EMIF1_BASE);
1554                 if (emif2_enabled)
1555                         emif_post_init_config(EMIF2_BASE);
1556         }
1557
1558         /* for the shadow registers to take effect */
1559         if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
1560                 freq_update_core();
1561
1562         /* Do some testing after the init */
1563         if (!in_sdram) {
1564                 size_prog = omap_sdram_size();
1565                 size_prog = log_2_n_round_down(size_prog);
1566                 size_prog = (1 << size_prog);
1567
1568                 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1569                                                 size_prog);
1570                 /* Compare with the size programmed */
1571                 if (size_detect != size_prog) {
1572                         printf("SDRAM: identified size not same as expected"
1573                                 " size identified: %x expected: %x\n",
1574                                 size_detect,
1575                                 size_prog);
1576                 } else
1577                         debug("get_ram_size() successful");
1578         }
1579
1580 #if defined(CONFIG_TI_SECURE_DEVICE)
1581         /*
1582          * On HS devices, do static EMIF firewall configuration
1583          * but only do it if not already running in SDRAM
1584          */
1585         if (!in_sdram)
1586                 if (0 != secure_emif_reserve())
1587                         hang();
1588
1589         /* On HS devices, ensure static EMIF firewall APIs are locked */
1590         if (0 != secure_emif_firewall_lock())
1591                 hang();
1592 #endif
1593
1594         if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
1595             (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
1596                 if (emif1_enabled)
1597                         do_bug0039_workaround(EMIF1_BASE);
1598                 if (emif2_enabled)
1599                         do_bug0039_workaround(EMIF2_BASE);
1600         }
1601
1602         debug("<<sdram_init()\n");
1603 }