arch/arm/mach-omap2/emif-common.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * EMIF programming
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Aneesh V <aneesh@ti.com>
   9  */
  10
  11 #include <common.h>
  12 #include <asm/emif.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/omap_sec_common.h>
  17 #include <asm/utils.h>
  18 #include <linux/compiler.h>
  19 #include <asm/ti-common/ti-edma3.h>
  20
  21 static int emif1_enabled = -1, emif2_enabled = -1;
  22
  23 void set_lpmode_selfrefresh(u32 base)
  24 {
  25         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  26         u32 reg;
  27
  28         reg = readl(&emif->emif_pwr_mgmt_ctrl);
  29         reg &= ~EMIF_REG_LP_MODE_MASK;
  30         reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
  31         reg &= ~EMIF_REG_SR_TIM_MASK;
  32         writel(reg, &emif->emif_pwr_mgmt_ctrl);
  33
  34         /* dummy read for the new SR_TIM to be loaded */
  35         readl(&emif->emif_pwr_mgmt_ctrl);
  36 }
  37
  38 void force_emif_self_refresh()
  39 {
  40         set_lpmode_selfrefresh(EMIF1_BASE);
  41         if (!is_dra72x())
  42                 set_lpmode_selfrefresh(EMIF2_BASE);
  43 }
  44
  45 inline u32 emif_num(u32 base)
  46 {
  47         if (base == EMIF1_BASE)
  48                 return 1;
  49         else if (base == EMIF2_BASE)
  50                 return 2;
  51         else
  52                 return 0;
  53 }
  54
  55 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
  56 {
  57         u32 mr;
  58         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  59
  60         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  61         writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  62         if (omap_revision() == OMAP4430_ES2_0)
  63                 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
  64         else
  65                 mr = readl(&emif->emif_lpddr2_mode_reg_data);
  66         debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
  67               cs, mr_addr, mr);
  68         if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
  69             ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  70             ((mr & 0xff000000) >> 24) == (mr & 0xff))
  71                 return mr & 0xff;
  72         else
  73                 return mr;
  74 }
  75
  76 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
  77 {
  78         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  79
  80         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  81         writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  82         writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
  83 }
  84
  85 void emif_reset_phy(u32 base)
  86 {
  87         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  88         u32 iodft;
  89
  90         iodft = readl(&emif->emif_iodft_tlgc);
  91         iodft |= EMIF_REG_RESET_PHY_MASK;
  92         writel(iodft, &emif->emif_iodft_tlgc);
  93 }
  94
  95 static void do_lpddr2_init(u32 base, u32 cs)
  96 {
  97         u32 mr_addr;
  98         const struct lpddr2_mr_regs *mr_regs;
  99
 100         get_lpddr2_mr_regs(&mr_regs);
 101         /* Wait till device auto initialization is complete */
 102         while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
 103                 ;
 104         set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
 105         /*
 106          * tZQINIT = 1 us
 107          * Enough loops assuming a maximum of 2GHz
 108          */
 109
 110         sdelay(2000);
 111
 112         set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
 113         set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
 114
 115         /*
 116          * Enable refresh along with writing MR2
 117          * Encoding of RL in MR2 is (RL - 2)
 118          */
 119         mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
 120         set_mr(base, cs, mr_addr, mr_regs->mr2);
 121
 122         if (mr_regs->mr3 > 0)
 123                 set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
 124 }
 125
 126 static void lpddr2_init(u32 base, const struct emif_regs *regs)
 127 {
 128         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 129
 130         /* Not NVM */
 131         clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
 132
 133         /*
 134          * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
 135          * when EMIF_SDRAM_CONFIG register is written
 136          */
 137         setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 138
 139         /*
 140          * Set the SDRAM_CONFIG and PHY_CTRL for the
 141          * un-locked frequency & default RL
 142          */
 143         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 144         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 145
 146         do_ext_phy_settings(base, regs);
 147
 148         do_lpddr2_init(base, CS0);
 149         if (regs->sdram_config & EMIF_REG_EBANK_MASK)
 150                 do_lpddr2_init(base, CS1);
 151
 152         writel(regs->sdram_config, &emif->emif_sdram_config);
 153         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
 154
 155         /* Enable refresh now */
 156         clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 157
 158         }
 159
 160 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 161 {
 162 }
 163
 164 void emif_update_timings(u32 base, const struct emif_regs *regs)
 165 {
 166         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 167
 168         if (!is_dra7xx())
 169                 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
 170         else
 171                 writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw);
 172
 173         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
 174         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
 175         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
 176         if (omap_revision() == OMAP4430_ES1_0) {
 177                 /* ES1 bug EMIF should be in force idle during freq_update */
 178                 writel(0, &emif->emif_pwr_mgmt_ctrl);
 179         } else {
 180                 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
 181                 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
 182         }
 183         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
 184         writel(regs->zq_config, &emif->emif_zq_config);
 185         writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
 186         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 187
 188         if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
 189                 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
 190                         &emif->emif_l3_config);
 191         } else if (omap_revision() >= OMAP4460_ES1_0) {
 192                 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
 193                         &emif->emif_l3_config);
 194         } else {
 195                 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
 196                         &emif->emif_l3_config);
 197         }
 198 }
 199
 200 #ifndef CONFIG_OMAP44XX
 201 static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
 202 {
 203         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 204
 205         /* keep sdram in self-refresh */
 206         writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
 207                 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 208         __udelay(130);
 209
 210         /*
 211          * Set invert_clkout (if activated)--DDR_PHYCTRL_1
 212          * Invert clock adds an additional half cycle delay on the
 213          * command interface.  The additional half cycle, is usually
 214          * meant to enable leveling in the situation that DQS is later
 215          * than CK on the board.It also helps provide some additional
 216          * margin for leveling.
 217          */
 218         writel(regs->emif_ddr_phy_ctlr_1,
 219                &emif->emif_ddr_phy_ctrl_1);
 220
 221         writel(regs->emif_ddr_phy_ctlr_1,
 222                &emif->emif_ddr_phy_ctrl_1_shdw);
 223         __udelay(130);
 224
 225         writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
 226                & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 227
 228         /* Launch Full leveling */
 229         writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
 230
 231         /* Wait till full leveling is complete */
 232         readl(&emif->emif_rd_wr_lvl_ctl);
 233               __udelay(130);
 234
 235         /* Read data eye leveling no of samples */
 236         config_data_eye_leveling_samples(base);
 237
 238         /*
 239          * Launch 8 incremental WR_LVL- to compensate for
 240          * PHY limitation.
 241          */
 242         writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
 243                &emif->emif_rd_wr_lvl_ctl);
 244
 245         __udelay(130);
 246
 247         /* Launch Incremental leveling */
 248         writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
 249                __udelay(130);
 250 }
 251
 252 static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
 253 {
 254         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 255         u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
 256         u32 reg, i, phy;
 257
 258         emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[6];
 259         phy = readl(&emif->emif_ddr_phy_ctrl_1);
 260
 261         /* Update PHY_REG_RDDQS_RATIO */
 262         emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;
 263         if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK))
 264                 for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
 265                         reg = readl(emif_phy_status++);
 266                         writel(reg, emif_ext_phy_ctrl_reg++);
 267                         writel(reg, emif_ext_phy_ctrl_reg++);
 268                 }
 269
 270         /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
 271         emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
 272         emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[11];
 273         if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK))
 274                 for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
 275                         reg = readl(emif_phy_status++);
 276                         writel(reg, emif_ext_phy_ctrl_reg++);
 277                         writel(reg, emif_ext_phy_ctrl_reg++);
 278                 }
 279
 280         /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
 281         emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
 282         emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[16];
 283         if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK))
 284                 for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
 285                         reg = readl(emif_phy_status++);
 286                         writel(reg, emif_ext_phy_ctrl_reg++);
 287                         writel(reg, emif_ext_phy_ctrl_reg++);
 288                 }
 289
 290         /* Disable Leveling */
 291         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
 292         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 293         writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
 294 }
 295
 296 static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
 297 {
 298         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 299
 300         /* Clear Error Status */
 301         clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36,
 302                         EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
 303                         EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
 304
 305         clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw,
 306                         EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
 307                         EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
 308
 309         /* Disable refreshed before leveling */
 310         clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK,
 311                         EMIF_REG_INITREF_DIS_MASK);
 312
 313         /* Start Full leveling */
 314         writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
 315
 316         __udelay(300);
 317
 318         /* Check for leveling timeout */
 319         if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) {
 320                 printf("Leveling timeout on EMIF%d\n", emif_num(base));
 321                 return;
 322         }
 323
 324         /* Enable refreshes after leveling */
 325         clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 326
 327         debug("HW leveling success\n");
 328         /*
 329          * Update slave ratios in EXT_PHY_CTRLx registers
 330          * as per HW leveling output
 331          */
 332         update_hwleveling_output(base, regs);
 333 }
 334
 335 static void dra7_reset_ddr_data(u32 base, u32 size)
 336 {
 337 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
 338         enable_edma3_clocks();
 339
 340         edma3_fill(EDMA3_BASE, 1, (void *)base, 0, size);
 341
 342         disable_edma3_clocks();
 343 #else
 344         memset((void *)base, 0, size);
 345 #endif
 346 }
 347
 348 static void dra7_enable_ecc(u32 base, const struct emif_regs *regs)
 349 {
 350         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 351         u32 rgn, rgn_start, size, ctrl_reg;
 352
 353         /* ECC available only on dra76x EMIF1 */
 354         if ((base != EMIF1_BASE) || !is_dra76x())
 355                 return;
 356
 357         if (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK) {
 358                 /* Disable high-order interleaving */
 359                 clrbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);
 360
 361 #ifdef CONFIG_DRA7XX
 362                 /* Clear the status flags and other history */
 363                 writel(readl(&emif->emif_1b_ecc_err_cnt),
 364                        &emif->emif_1b_ecc_err_cnt);
 365                 writel(0xffffffff, &emif->emif_1b_ecc_err_dist_1);
 366                 writel(0x2, &emif->emif_1b_ecc_err_addr_log);
 367                 writel(0x1, &emif->emif_2b_ecc_err_addr_log);
 368                 writel(EMIF_INT_WR_ECC_ERR_SYS_MASK |
 369                        EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK |
 370                        EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK,
 371                        &emif->emif_irqstatus_sys);
 372 #endif
 373                 writel(regs->emif_ecc_address_range_1,
 374                        &emif->emif_ecc_address_range_1);
 375                 writel(regs->emif_ecc_address_range_2,
 376                        &emif->emif_ecc_address_range_2);
 377
 378                 /* Disable RMW and ECC verification for read accesses */
 379                 ctrl_reg = (regs->emif_ecc_ctrl_reg &
 380                             ~EMIF_ECC_REG_RMW_EN_MASK) |
 381                            EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK;
 382                 writel(ctrl_reg, &emif->emif_ecc_ctrl_reg);
 383
 384                 /* Set region1 memory with 0 */
 385                 rgn_start = (regs->emif_ecc_address_range_1 &
 386                              EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
 387                 rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
 388                 size = (regs->emif_ecc_address_range_1 &
 389                         EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
 390
 391                 if (regs->emif_ecc_ctrl_reg &
 392                     EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK)
 393                         dra7_reset_ddr_data(rgn, size);
 394
 395                 /* Set region2 memory with 0 */
 396                 rgn_start = (regs->emif_ecc_address_range_2 &
 397                              EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
 398                 rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
 399                 size = (regs->emif_ecc_address_range_2 &
 400                         EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
 401
 402                 if (regs->emif_ecc_ctrl_reg &
 403                     EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK)
 404                         dra7_reset_ddr_data(rgn, size);
 405
 406                 /* Default value enables RMW and ECC verification */
 407                 writel(regs->emif_ecc_ctrl_reg, &emif->emif_ecc_ctrl_reg);
 408         }
 409 }
 410
 411 static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
 412 {
 413         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 414
 415         if (warm_reset()) {
 416                 emif_reset_phy(base);
 417                 writel(0x0, &emif->emif_pwr_mgmt_ctrl);
 418         }
 419         do_ext_phy_settings(base, regs);
 420
 421         writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
 422                &emif->emif_sdram_ref_ctrl);
 423         /* Update timing registers */
 424         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
 425         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
 426         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
 427
 428         writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config);
 429         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 430         writel(regs->zq_config, &emif->emif_zq_config);
 431         writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
 432         writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
 433         writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
 434
 435         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 436         writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh);
 437
 438         writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
 439
 440         writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 441         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 442
 443         __udelay(1000);
 444
 445         writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
 446
 447         if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) {
 448                 /*
 449                  * Perform Dummy ECC setup just to allow hardware
 450                  * leveling of ECC memories
 451                  */
 452                 if (is_dra76x() && (base == EMIF1_BASE) &&
 453                     (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK)) {
 454                         writel(0, &emif->emif_ecc_address_range_1);
 455                         writel(0, &emif->emif_ecc_address_range_2);
 456                         writel(EMIF_ECC_CTRL_REG_ECC_EN_MASK |
 457                                EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK,
 458                                &emif->emif_ecc_ctrl_reg);
 459                 }
 460
 461                 dra7_ddr3_leveling(base, regs);
 462
 463                 /* Disable ECC */
 464                 if (is_dra76x())
 465                         writel(0, &emif->emif_ecc_ctrl_reg);
 466         }
 467
 468         /* Enable ECC as necessary */
 469         dra7_enable_ecc(base, regs);
 470 }
 471
 472 static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
 473 {
 474         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 475
 476         writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
 477         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 478         /*
 479          * Set SDRAM_CONFIG and PHY control registers to locked frequency
 480          * and RL =7. As the default values of the Mode Registers are not
 481          * defined, contents of mode Registers must be fully initialized.
 482          * H/W takes care of this initialization
 483          */
 484         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 485
 486         /* Update timing registers */
 487         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
 488         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
 489         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
 490
 491         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 492
 493         writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 494         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 495         do_ext_phy_settings(base, regs);
 496
 497         writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
 498         omap5_ddr3_leveling(base, regs);
 499 }
 500
 501 static void ddr3_init(u32 base, const struct emif_regs *regs)
 502 {
 503         if (is_omap54xx())
 504                 omap5_ddr3_init(base, regs);
 505         else
 506                 dra7_ddr3_init(base, regs);
 507 }
 508 #endif
 509
 510 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 511 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
 512
 513 /*
 514  * Organization and refresh requirements for LPDDR2 devices of different
 515  * types and densities. Derived from JESD209-2 section 2.4
 516  */
 517 const struct lpddr2_addressing addressing_table[] = {
 518         /* Banks tREFIx10     rowx32,rowx16      colx32,colx16  density */
 519         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
 520         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
 521         {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
 522         {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
 523         {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
 524         {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
 525         {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
 526         {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
 527         {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
 528         {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
 529 };
 530
 531 static const u32 lpddr2_density_2_size_in_mbytes[] = {
 532         8,                      /* 64Mb */
 533         16,                     /* 128Mb */
 534         32,                     /* 256Mb */
 535         64,                     /* 512Mb */
 536         128,                    /* 1Gb   */
 537         256,                    /* 2Gb   */
 538         512,                    /* 4Gb   */
 539         1024,                   /* 8Gb   */
 540         2048,                   /* 16Gb  */
 541         4096                    /* 32Gb  */
 542 };
 543
 544 /*
 545  * Calculate the period of DDR clock from frequency value and set the
 546  * denominator and numerator in global variables for easy access later
 547  */
 548 static void set_ddr_clk_period(u32 freq)
 549 {
 550         /*
 551          * period = 1/freq
 552          * period_in_ns = 10^9/freq
 553          */
 554         *T_num = 1000000000;
 555         *T_den = freq;
 556         cancel_out(T_num, T_den, 200);
 557
 558 }
 559
 560 /*
 561  * Convert time in nano seconds to number of cycles of DDR clock
 562  */
 563 static inline u32 ns_2_cycles(u32 ns)
 564 {
 565         return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
 566 }
 567
 568 /*
 569  * ns_2_cycles with the difference that the time passed is 2 times the actual
 570  * value(to avoid fractions). The cycles returned is for the original value of
 571  * the timing parameter
 572  */
 573 static inline u32 ns_x2_2_cycles(u32 ns)
 574 {
 575         return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
 576 }
 577
 578 /*
 579  * Find addressing table index based on the device's type(S2 or S4) and
 580  * density
 581  */
 582 s8 addressing_table_index(u8 type, u8 density, u8 width)
 583 {
 584         u8 index;
 585         if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
 586                 return -1;
 587
 588         /*
 589          * Look at the way ADDR_TABLE_INDEX* values have been defined
 590          * in emif.h compared to LPDDR2_DENSITY_* values
 591          * The table is layed out in the increasing order of density
 592          * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
 593          * at the end
 594          */
 595         if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
 596                 index = ADDR_TABLE_INDEX1GS2;
 597         else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
 598                 index = ADDR_TABLE_INDEX2GS2;
 599         else
 600                 index = density;
 601
 602         debug("emif: addressing table index %d\n", index);
 603
 604         return index;
 605 }
 606
 607 /*
 608  * Find the the right timing table from the array of timing
 609  * tables of the device using DDR clock frequency
 610  */
 611 static const struct lpddr2_ac_timings *get_timings_table(const struct
 612                         lpddr2_ac_timings *const *device_timings,
 613                         u32 freq)
 614 {
 615         u32 i, temp, freq_nearest;
 616         const struct lpddr2_ac_timings *timings = 0;
 617
 618         emif_assert(freq <= MAX_LPDDR2_FREQ);
 619         emif_assert(device_timings);
 620
 621         /*
 622          * Start with the maximum allowed frequency - that is always safe
 623          */
 624         freq_nearest = MAX_LPDDR2_FREQ;
 625         /*
 626          * Find the timings table that has the max frequency value:
 627          *   i.  Above or equal to the DDR frequency - safe
 628          *   ii. The lowest that satisfies condition (i) - optimal
 629          */
 630         for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
 631                 temp = device_timings[i]->max_freq;
 632                 if ((temp >= freq) && (temp <= freq_nearest)) {
 633                         freq_nearest = temp;
 634                         timings = device_timings[i];
 635                 }
 636         }
 637         debug("emif: timings table: %d\n", freq_nearest);
 638         return timings;
 639 }
 640
 641 /*
 642  * Finds the value of emif_sdram_config_reg
 643  * All parameters are programmed based on the device on CS0.
 644  * If there is a device on CS1, it will be same as that on CS0 or
 645  * it will be NVM. We don't support NVM yet.
 646  * If cs1_device pointer is NULL it is assumed that there is no device
 647  * on CS1
 648  */
 649 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
 650                                 const struct lpddr2_device_details *cs1_device,
 651                                 const struct lpddr2_addressing *addressing,
 652                                 u8 RL)
 653 {
 654         u32 config_reg = 0;
 655
 656         config_reg |=  (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
 657         config_reg |=  EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
 658                         EMIF_REG_IBANK_POS_SHIFT;
 659
 660         config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
 661
 662         config_reg |= RL << EMIF_REG_CL_SHIFT;
 663
 664         config_reg |= addressing->row_sz[cs0_device->io_width] <<
 665                         EMIF_REG_ROWSIZE_SHIFT;
 666
 667         config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
 668
 669         config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
 670                         EMIF_REG_EBANK_SHIFT;
 671
 672         config_reg |= addressing->col_sz[cs0_device->io_width] <<
 673                         EMIF_REG_PAGESIZE_SHIFT;
 674
 675         return config_reg;
 676 }
 677
 678 static u32 get_sdram_ref_ctrl(u32 freq,
 679                               const struct lpddr2_addressing *addressing)
 680 {
 681         u32 ref_ctrl = 0, val = 0, freq_khz;
 682         freq_khz = freq / 1000;
 683         /*
 684          * refresh rate to be set is 'tREFI * freq in MHz
 685          * division by 10000 to account for khz and x10 in t_REFI_us_x10
 686          */
 687         val = addressing->t_REFI_us_x10 * freq_khz / 10000;
 688         ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
 689
 690         return ref_ctrl;
 691 }
 692
 693 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
 694                                const struct lpddr2_min_tck *min_tck,
 695                                const struct lpddr2_addressing *addressing)
 696 {
 697         u32 tim1 = 0, val = 0;
 698         val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
 699         tim1 |= val << EMIF_REG_T_WTR_SHIFT;
 700
 701         if (addressing->num_banks == BANKS8)
 702                 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
 703                                                         (4 * (*T_num)) - 1;
 704         else
 705                 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
 706
 707         tim1 |= val << EMIF_REG_T_RRD_SHIFT;
 708
 709         val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
 710         tim1 |= val << EMIF_REG_T_RC_SHIFT;
 711
 712         val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
 713         tim1 |= val << EMIF_REG_T_RAS_SHIFT;
 714
 715         val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
 716         tim1 |= val << EMIF_REG_T_WR_SHIFT;
 717
 718         val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
 719         tim1 |= val << EMIF_REG_T_RCD_SHIFT;
 720
 721         val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
 722         tim1 |= val << EMIF_REG_T_RP_SHIFT;
 723
 724         return tim1;
 725 }
 726
 727 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
 728                                const struct lpddr2_min_tck *min_tck)
 729 {
 730         u32 tim2 = 0, val = 0;
 731         val = max(min_tck->tCKE, timings->tCKE) - 1;
 732         tim2 |= val << EMIF_REG_T_CKE_SHIFT;
 733
 734         val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
 735         tim2 |= val << EMIF_REG_T_RTP_SHIFT;
 736
 737         /*
 738          * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
 739          * same value
 740          */
 741         val = ns_2_cycles(timings->tXSR) - 1;
 742         tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
 743         tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
 744
 745         val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
 746         tim2 |= val << EMIF_REG_T_XP_SHIFT;
 747
 748         return tim2;
 749 }
 750
 751 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
 752                                const struct lpddr2_min_tck *min_tck,
 753                                const struct lpddr2_addressing *addressing)
 754 {
 755         u32 tim3 = 0, val = 0;
 756         val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
 757         tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
 758
 759         val = ns_2_cycles(timings->tRFCab) - 1;
 760         tim3 |= val << EMIF_REG_T_RFC_SHIFT;
 761
 762         val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
 763         tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
 764
 765         val = ns_2_cycles(timings->tZQCS) - 1;
 766         tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
 767
 768         val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
 769         tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
 770
 771         return tim3;
 772 }
 773
 774 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
 775                              const struct lpddr2_addressing *addressing,
 776                              u8 volt_ramp)
 777 {
 778         u32 zq = 0, val = 0;
 779         if (volt_ramp)
 780                 val =
 781                     EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
 782                     addressing->t_REFI_us_x10;
 783         else
 784                 val =
 785                     EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
 786                     addressing->t_REFI_us_x10;
 787         zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
 788
 789         zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
 790
 791         zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
 792
 793         zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
 794
 795         /*
 796          * Assuming that two chipselects have a single calibration resistor
 797          * If there are indeed two calibration resistors, then this flag should
 798          * be enabled to take advantage of dual calibration feature.
 799          * This data should ideally come from board files. But considering
 800          * that none of the boards today have calibration resistors per CS,
 801          * it would be an unnecessary overhead.
 802          */
 803         zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
 804
 805         zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
 806
 807         zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
 808
 809         return zq;
 810 }
 811
 812 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
 813                                  const struct lpddr2_addressing *addressing,
 814                                  u8 is_derated)
 815 {
 816         u32 alert = 0, interval;
 817         interval =
 818             TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
 819         if (is_derated)
 820                 interval *= 4;
 821         alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
 822
 823         alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
 824
 825         alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
 826
 827         alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
 828
 829         alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
 830
 831         alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
 832
 833         return alert;
 834 }
 835
 836 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
 837 {
 838         u32 idle = 0, val = 0;
 839         if (volt_ramp)
 840                 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
 841         else
 842                 /*Maximum value in normal conditions - suggested by hw team */
 843                 val = 0x1FF;
 844         idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
 845
 846         idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
 847
 848         return idle;
 849 }
 850
 851 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
 852 {
 853         u32 phy = 0, val = 0;
 854
 855         phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
 856
 857         if (freq <= 100000000)
 858                 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
 859         else if (freq <= 200000000)
 860                 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
 861         else
 862                 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
 863         phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
 864
 865         /* Other fields are constant magic values. Hardcode them together */
 866         phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
 867                 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
 868
 869         return phy;
 870 }
 871
 872 static u32 get_emif_mem_size(u32 base)
 873 {
 874         u32 size_mbytes = 0, temp;
 875         struct emif_device_details dev_details;
 876         struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
 877         u32 emif_nr = emif_num(base);
 878
 879         emif_reset_phy(base);
 880         dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
 881                                                 &cs0_dev_details);
 882         dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
 883                                                 &cs1_dev_details);
 884         emif_reset_phy(base);
 885
 886         if (dev_details.cs0_device_details) {
 887                 temp = dev_details.cs0_device_details->density;
 888                 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
 889         }
 890
 891         if (dev_details.cs1_device_details) {
 892                 temp = dev_details.cs1_device_details->density;
 893                 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
 894         }
 895         /* convert to bytes */
 896         return size_mbytes << 20;
 897 }
 898
 899 /* Gets the encoding corresponding to a given DMM section size */
 900 u32 get_dmm_section_size_map(u32 section_size)
 901 {
 902         /*
 903          * Section size mapping:
 904          * 0x0: 16-MiB section
 905          * 0x1: 32-MiB section
 906          * 0x2: 64-MiB section
 907          * 0x3: 128-MiB section
 908          * 0x4: 256-MiB section
 909          * 0x5: 512-MiB section
 910          * 0x6: 1-GiB section
 911          * 0x7: 2-GiB section
 912          */
 913         section_size >>= 24; /* divide by 16 MB */
 914         return log_2_n_round_down(section_size);
 915 }
 916
 917 static void emif_calculate_regs(
 918                 const struct emif_device_details *emif_dev_details,
 919                 u32 freq, struct emif_regs *regs)
 920 {
 921         u32 temp, sys_freq;
 922         const struct lpddr2_addressing *addressing;
 923         const struct lpddr2_ac_timings *timings;
 924         const struct lpddr2_min_tck *min_tck;
 925         const struct lpddr2_device_details *cs0_dev_details =
 926                                         emif_dev_details->cs0_device_details;
 927         const struct lpddr2_device_details *cs1_dev_details =
 928                                         emif_dev_details->cs1_device_details;
 929         const struct lpddr2_device_timings *cs0_dev_timings =
 930                                         emif_dev_details->cs0_device_timings;
 931
 932         emif_assert(emif_dev_details);
 933         emif_assert(regs);
 934         /*
 935          * You can not have a device on CS1 without one on CS0
 936          * So configuring EMIF without a device on CS0 doesn't
 937          * make sense
 938          */
 939         emif_assert(cs0_dev_details);
 940         emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
 941         /*
 942          * If there is a device on CS1 it should be same type as CS0
 943          * (or NVM. But NVM is not supported in this driver yet)
 944          */
 945         emif_assert((cs1_dev_details == NULL) ||
 946                     (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
 947                     (cs0_dev_details->type == cs1_dev_details->type));
 948         emif_assert(freq <= MAX_LPDDR2_FREQ);
 949
 950         set_ddr_clk_period(freq);
 951
 952         /*
 953          * The device on CS0 is used for all timing calculations
 954          * There is only one set of registers for timings per EMIF. So, if the
 955          * second CS(CS1) has a device, it should have the same timings as the
 956          * device on CS0
 957          */
 958         timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
 959         emif_assert(timings);
 960         min_tck = cs0_dev_timings->min_tck;
 961
 962         temp = addressing_table_index(cs0_dev_details->type,
 963                                       cs0_dev_details->density,
 964                                       cs0_dev_details->io_width);
 965
 966         emif_assert((temp >= 0));
 967         addressing = &(addressing_table[temp]);
 968         emif_assert(addressing);
 969
 970         sys_freq = get_sys_clk_freq();
 971
 972         regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
 973                                                         cs1_dev_details,
 974                                                         addressing, RL_BOOT);
 975
 976         regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
 977                                                 cs1_dev_details,
 978                                                 addressing, RL_FINAL);
 979
 980         regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
 981
 982         regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
 983
 984         regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
 985
 986         regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
 987
 988         regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
 989
 990         regs->temp_alert_config =
 991             get_temp_alert_config(cs1_dev_details, addressing, 0);
 992
 993         regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
 994                                             LPDDR2_VOLTAGE_STABLE);
 995
 996         regs->emif_ddr_phy_ctlr_1_init =
 997                         get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
 998
 999         regs->emif_ddr_phy_ctlr_1 =
1000                         get_ddr_phy_ctrl_1(freq, RL_FINAL);
1001
1002         regs->freq = freq;
1003
1004         print_timing_reg(regs->sdram_config_init);
1005         print_timing_reg(regs->sdram_config);
1006         print_timing_reg(regs->ref_ctrl);
1007         print_timing_reg(regs->sdram_tim1);
1008         print_timing_reg(regs->sdram_tim2);
1009         print_timing_reg(regs->sdram_tim3);
1010         print_timing_reg(regs->read_idle_ctrl);
1011         print_timing_reg(regs->temp_alert_config);
1012         print_timing_reg(regs->zq_config);
1013         print_timing_reg(regs->emif_ddr_phy_ctlr_1);
1014         print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
1015 }
1016 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1017
1018 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
1019 const char *get_lpddr2_type(u8 type_id)
1020 {
1021         switch (type_id) {
1022         case LPDDR2_TYPE_S4:
1023                 return "LPDDR2-S4";
1024         case LPDDR2_TYPE_S2:
1025                 return "LPDDR2-S2";
1026         default:
1027                 return NULL;
1028         }
1029 }
1030
1031 const char *get_lpddr2_io_width(u8 width_id)
1032 {
1033         switch (width_id) {
1034         case LPDDR2_IO_WIDTH_8:
1035                 return "x8";
1036         case LPDDR2_IO_WIDTH_16:
1037                 return "x16";
1038         case LPDDR2_IO_WIDTH_32:
1039                 return "x32";
1040         default:
1041                 return NULL;
1042         }
1043 }
1044
1045 const char *get_lpddr2_manufacturer(u32 manufacturer)
1046 {
1047         switch (manufacturer) {
1048         case LPDDR2_MANUFACTURER_SAMSUNG:
1049                 return "Samsung";
1050         case LPDDR2_MANUFACTURER_QIMONDA:
1051                 return "Qimonda";
1052         case LPDDR2_MANUFACTURER_ELPIDA:
1053                 return "Elpida";
1054         case LPDDR2_MANUFACTURER_ETRON:
1055                 return "Etron";
1056         case LPDDR2_MANUFACTURER_NANYA:
1057                 return "Nanya";
1058         case LPDDR2_MANUFACTURER_HYNIX:
1059                 return "Hynix";
1060         case LPDDR2_MANUFACTURER_MOSEL:
1061                 return "Mosel";
1062         case LPDDR2_MANUFACTURER_WINBOND:
1063                 return "Winbond";
1064         case LPDDR2_MANUFACTURER_ESMT:
1065                 return "ESMT";
1066         case LPDDR2_MANUFACTURER_SPANSION:
1067                 return "Spansion";
1068         case LPDDR2_MANUFACTURER_SST:
1069                 return "SST";
1070         case LPDDR2_MANUFACTURER_ZMOS:
1071                 return "ZMOS";
1072         case LPDDR2_MANUFACTURER_INTEL:
1073                 return "Intel";
1074         case LPDDR2_MANUFACTURER_NUMONYX:
1075                 return "Numonyx";
1076         case LPDDR2_MANUFACTURER_MICRON:
1077                 return "Micron";
1078         default:
1079                 return NULL;
1080         }
1081 }
1082
1083 static void display_sdram_details(u32 emif_nr, u32 cs,
1084                                   struct lpddr2_device_details *device)
1085 {
1086         const char *mfg_str;
1087         const char *type_str;
1088         char density_str[10];
1089         u32 density;
1090
1091         debug("EMIF%d CS%d\t", emif_nr, cs);
1092
1093         if (!device) {
1094                 debug("None\n");
1095                 return;
1096         }
1097
1098         mfg_str = get_lpddr2_manufacturer(device->manufacturer);
1099         type_str = get_lpddr2_type(device->type);
1100
1101         density = lpddr2_density_2_size_in_mbytes[device->density];
1102         if ((density / 1024 * 1024) == density) {
1103                 density /= 1024;
1104                 sprintf(density_str, "%d GB", density);
1105         } else
1106                 sprintf(density_str, "%d MB", density);
1107         if (mfg_str && type_str)
1108                 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
1109 }
1110
1111 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
1112                                   struct lpddr2_device_details *lpddr2_device)
1113 {
1114         u32 mr = 0, temp;
1115
1116         mr = get_mr(base, cs, LPDDR2_MR0);
1117         if (mr > 0xFF) {
1118                 /* Mode register value bigger than 8 bit */
1119                 return 0;
1120         }
1121
1122         temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
1123         if (temp) {
1124                 /* Not SDRAM */
1125                 return 0;
1126         }
1127         temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
1128
1129         if (temp) {
1130                 /* DNV supported - But DNV is only supported for NVM */
1131                 return 0;
1132         }
1133
1134         mr = get_mr(base, cs, LPDDR2_MR4);
1135         if (mr > 0xFF) {
1136                 /* Mode register value bigger than 8 bit */
1137                 return 0;
1138         }
1139
1140         mr = get_mr(base, cs, LPDDR2_MR5);
1141         if (mr > 0xFF) {
1142                 /* Mode register value bigger than 8 bit */
1143                 return 0;
1144         }
1145
1146         if (!get_lpddr2_manufacturer(mr)) {
1147                 /* Manufacturer not identified */
1148                 return 0;
1149         }
1150         lpddr2_device->manufacturer = mr;
1151
1152         mr = get_mr(base, cs, LPDDR2_MR6);
1153         if (mr >= 0xFF) {
1154                 /* Mode register value bigger than 8 bit */
1155                 return 0;
1156         }
1157
1158         mr = get_mr(base, cs, LPDDR2_MR7);
1159         if (mr >= 0xFF) {
1160                 /* Mode register value bigger than 8 bit */
1161                 return 0;
1162         }
1163
1164         mr = get_mr(base, cs, LPDDR2_MR8);
1165         if (mr >= 0xFF) {
1166                 /* Mode register value bigger than 8 bit */
1167                 return 0;
1168         }
1169
1170         temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
1171         if (!get_lpddr2_type(temp)) {
1172                 /* Not SDRAM */
1173                 return 0;
1174         }
1175         lpddr2_device->type = temp;
1176
1177         temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
1178         if (temp > LPDDR2_DENSITY_32Gb) {
1179                 /* Density not supported */
1180                 return 0;
1181         }
1182         lpddr2_device->density = temp;
1183
1184         temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
1185         if (!get_lpddr2_io_width(temp)) {
1186                 /* IO width unsupported value */
1187                 return 0;
1188         }
1189         lpddr2_device->io_width = temp;
1190
1191         /*
1192          * If all the above tests pass we should
1193          * have a device on this chip-select
1194          */
1195         return 1;
1196 }
1197
1198 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
1199                         struct lpddr2_device_details *lpddr2_dev_details)
1200 {
1201         u32 phy;
1202         u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
1203
1204         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1205
1206         if (!lpddr2_dev_details)
1207                 return NULL;
1208
1209         /* Do the minimum init for mode register accesses */
1210         if (!(running_from_sdram() || warm_reset())) {
1211                 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
1212                 writel(phy, &emif->emif_ddr_phy_ctrl_1);
1213         }
1214
1215         if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
1216                 return NULL;
1217
1218         display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
1219
1220         return lpddr2_dev_details;
1221 }
1222 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1223
1224 static void do_sdram_init(u32 base)
1225 {
1226         const struct emif_regs *regs;
1227         u32 in_sdram, emif_nr;
1228
1229         debug(">>do_sdram_init() %x\n", base);
1230
1231         in_sdram = running_from_sdram();
1232         emif_nr = (base == EMIF1_BASE) ? 1 : 2;
1233
1234 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1235         emif_get_reg_dump(emif_nr, &regs);
1236         if (!regs) {
1237                 debug("EMIF: reg dump not provided\n");
1238                 return;
1239         }
1240 #else
1241         /*
1242          * The user has not provided the register values. We need to
1243          * calculate it based on the timings and the DDR frequency
1244          */
1245         struct emif_device_details dev_details;
1246         struct emif_regs calculated_regs;
1247
1248         /*
1249          * Get device details:
1250          * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1251          * - Obtained from user otherwise
1252          */
1253         struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1254         emif_reset_phy(base);
1255         dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
1256                                                 &cs0_dev_details);
1257         dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
1258                                                 &cs1_dev_details);
1259         emif_reset_phy(base);
1260
1261         /* Return if no devices on this EMIF */
1262         if (!dev_details.cs0_device_details &&
1263             !dev_details.cs1_device_details) {
1264                 return;
1265         }
1266
1267         /*
1268          * Get device timings:
1269          * - Default timings specified by JESD209-2 if
1270          *   CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1271          * - Obtained from user otherwise
1272          */
1273         emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1274                                 &dev_details.cs1_device_timings);
1275
1276         /* Calculate the register values */
1277         emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
1278         regs = &calculated_regs;
1279 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1280
1281         /*
1282          * Initializing the DDR device can not happen from SDRAM.
1283          * Changing the timing registers in EMIF can happen(going from one
1284          * OPP to another)
1285          */
1286         if (!in_sdram && (!warm_reset() || is_dra7xx())) {
1287                 if (emif_sdram_type(regs->sdram_config) ==
1288                     EMIF_SDRAM_TYPE_LPDDR2)
1289                         lpddr2_init(base, regs);
1290 #ifndef CONFIG_OMAP44XX
1291                 else
1292                         ddr3_init(base, regs);
1293 #endif
1294         }
1295 #ifdef CONFIG_OMAP54XX
1296         if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
1297             EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
1298                 set_lpmode_selfrefresh(base);
1299                 emif_reset_phy(base);
1300                 omap5_ddr3_leveling(base, regs);
1301         }
1302 #endif
1303
1304         /* Write to the shadow registers */
1305         emif_update_timings(base, regs);
1306
1307         debug("<<do_sdram_init() %x\n", base);
1308 }
1309
1310 void emif_post_init_config(u32 base)
1311 {
1312         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1313         u32 omap_rev = omap_revision();
1314
1315         /* reset phy on ES2.0 */
1316         if (omap_rev == OMAP4430_ES2_0)
1317                 emif_reset_phy(base);
1318
1319         /* Put EMIF back in smart idle on ES1.0 */
1320         if (omap_rev == OMAP4430_ES1_0)
1321                 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1322 }
1323
1324 void dmm_init(u32 base)
1325 {
1326         const struct dmm_lisa_map_regs *lisa_map_regs;
1327         u32 i, section, valid;
1328
1329 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1330         emif_get_dmm_regs(&lisa_map_regs);
1331 #else
1332         u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1333         u32 section_cnt, sys_addr;
1334         struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1335
1336         mapped_size = 0;
1337         section_cnt = 3;
1338         sys_addr = CONFIG_SYS_SDRAM_BASE;
1339         emif1_size = get_emif_mem_size(EMIF1_BASE);
1340         emif2_size = get_emif_mem_size(EMIF2_BASE);
1341         debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1342
1343         if (!emif1_size && !emif2_size)
1344                 return;
1345
1346         /* symmetric interleaved section */
1347         if (emif1_size && emif2_size) {
1348                 mapped_size = min(emif1_size, emif2_size);
1349                 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1350                 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
1351                 /* only MSB */
1352                 section_map |= (sys_addr >> 24) <<
1353                                 EMIF_SYS_ADDR_SHIFT;
1354                 section_map |= get_dmm_section_size_map(mapped_size * 2)
1355                                 << EMIF_SYS_SIZE_SHIFT;
1356                 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1357                 emif1_size -= mapped_size;
1358                 emif2_size -= mapped_size;
1359                 sys_addr += (mapped_size * 2);
1360                 section_cnt--;
1361         }
1362
1363         /*
1364          * Single EMIF section(we can have a maximum of 1 single EMIF
1365          * section- either EMIF1 or EMIF2 or none, but not both)
1366          */
1367         if (emif1_size) {
1368                 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1369                 section_map |= get_dmm_section_size_map(emif1_size)
1370                                 << EMIF_SYS_SIZE_SHIFT;
1371                 /* only MSB */
1372                 section_map |= (mapped_size >> 24) <<
1373                                 EMIF_SDRC_ADDR_SHIFT;
1374                 /* only MSB */
1375                 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
1376                 section_cnt--;
1377         }
1378         if (emif2_size) {
1379                 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1380                 section_map |= get_dmm_section_size_map(emif2_size) <<
1381                                 EMIF_SYS_SIZE_SHIFT;
1382                 /* only MSB */
1383                 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
1384                 /* only MSB */
1385                 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
1386                 section_cnt--;
1387         }
1388
1389         if (section_cnt == 2) {
1390                 /* Only 1 section - either symmetric or single EMIF */
1391                 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1392                 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1393                 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1394         } else {
1395                 /* 2 sections - 1 symmetric, 1 single EMIF */
1396                 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1397                 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1398         }
1399
1400         /* TRAP for invalid TILER mappings in section 0 */
1401         lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1402
1403         if (omap_revision() >= OMAP4460_ES1_0)
1404                 lis_map_regs_calculated.is_ma_present = 1;
1405
1406         lisa_map_regs = &lis_map_regs_calculated;
1407 #endif
1408         struct dmm_lisa_map_regs *hw_lisa_map_regs =
1409             (struct dmm_lisa_map_regs *)base;
1410
1411         writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1412         writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1413         writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1414         writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1415
1416         writel(lisa_map_regs->dmm_lisa_map_3,
1417                 &hw_lisa_map_regs->dmm_lisa_map_3);
1418         writel(lisa_map_regs->dmm_lisa_map_2,
1419                 &hw_lisa_map_regs->dmm_lisa_map_2);
1420         writel(lisa_map_regs->dmm_lisa_map_1,
1421                 &hw_lisa_map_regs->dmm_lisa_map_1);
1422         writel(lisa_map_regs->dmm_lisa_map_0,
1423                 &hw_lisa_map_regs->dmm_lisa_map_0);
1424
1425         if (lisa_map_regs->is_ma_present) {
1426                 hw_lisa_map_regs =
1427                     (struct dmm_lisa_map_regs *)MA_BASE;
1428
1429                 writel(lisa_map_regs->dmm_lisa_map_3,
1430                         &hw_lisa_map_regs->dmm_lisa_map_3);
1431                 writel(lisa_map_regs->dmm_lisa_map_2,
1432                         &hw_lisa_map_regs->dmm_lisa_map_2);
1433                 writel(lisa_map_regs->dmm_lisa_map_1,
1434                         &hw_lisa_map_regs->dmm_lisa_map_1);
1435                 writel(lisa_map_regs->dmm_lisa_map_0,
1436                         &hw_lisa_map_regs->dmm_lisa_map_0);
1437
1438                 setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);
1439         }
1440
1441         /*
1442          * EMIF should be configured only when
1443          * memory is mapped on it. Using emif1_enabled
1444          * and emif2_enabled variables for this.
1445          */
1446         emif1_enabled = 0;
1447         emif2_enabled = 0;
1448         for (i = 0; i < 4; i++) {
1449                 section = __raw_readl(DMM_BASE + i*4);
1450                 valid = (section & EMIF_SDRC_MAP_MASK) >>
1451                         (EMIF_SDRC_MAP_SHIFT);
1452                 if (valid == 3) {
1453                         emif1_enabled = 1;
1454                         emif2_enabled = 1;
1455                         break;
1456                 }
1457
1458                 if (valid == 1)
1459                         emif1_enabled = 1;
1460
1461                 if (valid == 2)
1462                         emif2_enabled = 1;
1463         }
1464 }
1465
1466 static void do_bug0039_workaround(u32 base)
1467 {
1468         u32 val, i, clkctrl;
1469         struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
1470         const struct read_write_regs *bug_00339_regs;
1471         u32 iterations;
1472         u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
1473         u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
1474
1475         if (is_dra7xx())
1476                 phy_status_base++;
1477
1478         bug_00339_regs = get_bug_regs(&iterations);
1479
1480         /* Put EMIF in to idle */
1481         clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
1482         __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
1483
1484         /* Copy the phy status registers in to phy ctrl shadow registers */
1485         for (i = 0; i < iterations; i++) {
1486                 val = __raw_readl(phy_status_base +
1487                                   bug_00339_regs[i].read_reg - 1);
1488
1489                 __raw_writel(val, phy_ctrl_base +
1490                              ((bug_00339_regs[i].write_reg - 1) << 1));
1491
1492                 __raw_writel(val, phy_ctrl_base +
1493                              (bug_00339_regs[i].write_reg << 1) - 1);
1494         }
1495
1496         /* Disable leveling */
1497         writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
1498
1499         __raw_writel(clkctrl,  (*prcm)->cm_memif_clkstctrl);
1500 }
1501
1502 /*
1503  * SDRAM initialization:
1504  * SDRAM initialization has two parts:
1505  * 1. Configuring the SDRAM device
1506  * 2. Update the AC timings related parameters in the EMIF module
1507  * (1) should be done only once and should not be done while we are
1508  * running from SDRAM.
1509  * (2) can and should be done more than once if OPP changes.
1510  * Particularly, this may be needed when we boot without SPL and
1511  * and using Configuration Header(CH). ROM code supports only at 50% OPP
1512  * at boot (low power boot). So u-boot has to switch to OPP100 and update
1513  * the frequency. So,
1514  * Doing (1) and (2) makes sense - first time initialization
1515  * Doing (2) and not (1) makes sense - OPP change (when using CH)
1516  * Doing (1) and not (2) doen't make sense
1517  * See do_sdram_init() for the details
1518  */
1519 void sdram_init(void)
1520 {
1521         u32 in_sdram, size_prog, size_detect;
1522         struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
1523         u32 sdram_type = emif_sdram_type(emif->emif_sdram_config);
1524
1525         debug(">>sdram_init()\n");
1526
1527         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1528                 return;
1529
1530         in_sdram = running_from_sdram();
1531         debug("in_sdram = %d\n", in_sdram);
1532
1533         if (!in_sdram) {
1534                 if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
1535                         bypass_dpll((*prcm)->cm_clkmode_dpll_core);
1536                 else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
1537                         writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
1538         }
1539
1540         if (!in_sdram)
1541                 dmm_init(DMM_BASE);
1542
1543         if (emif1_enabled)
1544                 do_sdram_init(EMIF1_BASE);
1545
1546         if (emif2_enabled)
1547                 do_sdram_init(EMIF2_BASE);
1548
1549         if (!(in_sdram || warm_reset())) {
1550                 if (emif1_enabled)
1551                         emif_post_init_config(EMIF1_BASE);
1552                 if (emif2_enabled)
1553                         emif_post_init_config(EMIF2_BASE);
1554         }
1555
1556         /* for the shadow registers to take effect */
1557         if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
1558                 freq_update_core();
1559
1560         /* Do some testing after the init */
1561         if (!in_sdram) {
1562                 size_prog = omap_sdram_size();
1563                 size_prog = log_2_n_round_down(size_prog);
1564                 size_prog = (1 << size_prog);
1565
1566                 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1567                                                 size_prog);
1568                 /* Compare with the size programmed */
1569                 if (size_detect != size_prog) {
1570                         printf("SDRAM: identified size not same as expected"
1571                                 " size identified: %x expected: %x\n",
1572                                 size_detect,
1573                                 size_prog);
1574                 } else
1575                         debug("get_ram_size() successful");
1576         }
1577
1578 #if defined(CONFIG_TI_SECURE_DEVICE)
1579         /*
1580          * On HS devices, do static EMIF firewall configuration
1581          * but only do it if not already running in SDRAM
1582          */
1583         if (!in_sdram)
1584                 if (0 != secure_emif_reserve())
1585                         hang();
1586
1587         /* On HS devices, ensure static EMIF firewall APIs are locked */
1588         if (0 != secure_emif_firewall_lock())
1589                 hang();
1590 #endif
1591
1592         if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
1593             (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
1594                 if (emif1_enabled)
1595                         do_bug0039_workaround(EMIF1_BASE);
1596                 if (emif2_enabled)
1597                         do_bug0039_workaround(EMIF2_BASE);
1598         }
1599
1600         debug("<<sdram_init()\n");
1601 }