2 * OMAP2plus display device setup / initialization.
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Senthilvadivu Guruswamy
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/string.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
23 #include <linux/clk.h>
24 #include <linux/err.h>
25 #include <linux/delay.h>
27 #include <video/omapdss.h>
28 #include "omap_hwmod.h"
29 #include "omap_device.h"
39 #define DISPC_CONTROL 0x0040
40 #define DISPC_CONTROL2 0x0238
41 #define DISPC_CONTROL3 0x0848
42 #define DISPC_IRQSTATUS 0x0018
44 #define DSS_SYSCONFIG 0x10
45 #define DSS_SYSSTATUS 0x14
46 #define DSS_CONTROL 0x40
47 #define DSS_SDI_CONTROL 0x44
48 #define DSS_PLL_CONTROL 0x48
50 #define LCD_EN_MASK (0x1 << 0)
51 #define DIGIT_EN_MASK (0x1 << 1)
53 #define FRAMEDONE_IRQ_SHIFT 0
54 #define EVSYNC_EVEN_IRQ_SHIFT 2
55 #define EVSYNC_ODD_IRQ_SHIFT 3
56 #define FRAMEDONE2_IRQ_SHIFT 22
57 #define FRAMEDONE3_IRQ_SHIFT 30
58 #define FRAMEDONETV_IRQ_SHIFT 24
61 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
62 * reset before deciding that something has gone wrong
64 #define FRAMEDONE_IRQ_TIMEOUT 100
66 static struct platform_device omap_display_device = {
70 .platform_data = NULL,
74 struct omap_dss_hwmod_data {
80 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
81 { "dss_core", "omapdss_dss", -1 },
82 { "dss_dispc", "omapdss_dispc", -1 },
83 { "dss_rfbi", "omapdss_rfbi", -1 },
84 { "dss_venc", "omapdss_venc", -1 },
87 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
88 { "dss_core", "omapdss_dss", -1 },
89 { "dss_dispc", "omapdss_dispc", -1 },
90 { "dss_rfbi", "omapdss_rfbi", -1 },
91 { "dss_venc", "omapdss_venc", -1 },
92 { "dss_dsi1", "omapdss_dsi", 0 },
95 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
96 { "dss_core", "omapdss_dss", -1 },
97 { "dss_dispc", "omapdss_dispc", -1 },
98 { "dss_rfbi", "omapdss_rfbi", -1 },
99 { "dss_dsi1", "omapdss_dsi", 0 },
100 { "dss_dsi2", "omapdss_dsi", 1 },
101 { "dss_hdmi", "omapdss_hdmi", -1 },
104 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
106 u32 enable_mask, enable_shift;
107 u32 pipd_mask, pipd_shift;
111 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
112 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
113 pipd_mask = OMAP4_DSI1_PIPD_MASK;
114 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
115 } else if (dsi_id == 1) {
116 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
117 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
118 pipd_mask = OMAP4_DSI2_PIPD_MASK;
119 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
124 reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
129 reg |= (lanes << enable_shift) & enable_mask;
130 reg |= (lanes << pipd_shift) & pipd_mask;
132 omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
137 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
139 if (cpu_is_omap44xx())
140 return omap4_dsi_mux_pads(dsi_id, lane_mask);
145 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
147 if (cpu_is_omap44xx())
148 omap4_dsi_mux_pads(dsi_id, 0);
151 static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
153 return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
156 static struct platform_device *create_dss_pdev(const char *pdev_name,
157 int pdev_id, const char *oh_name, void *pdata, int pdata_len,
158 struct platform_device *parent)
160 struct platform_device *pdev;
161 struct omap_device *od;
162 struct omap_hwmod *ohs[1];
163 struct omap_hwmod *oh;
166 oh = omap_hwmod_lookup(oh_name);
168 pr_err("Could not look up %s\n", oh_name);
173 pdev = platform_device_alloc(pdev_name, pdev_id);
175 pr_err("Could not create pdev for %s\n", pdev_name);
181 pdev->dev.parent = &parent->dev;
184 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
186 dev_set_name(&pdev->dev, "%s", pdev->name);
189 od = omap_device_alloc(pdev, ohs, 1);
191 pr_err("Could not alloc omap_device for %s\n", pdev_name);
196 r = platform_device_add_data(pdev, pdata, pdata_len);
198 pr_err("Could not set pdata for %s\n", pdev_name);
202 r = omap_device_register(pdev);
204 pr_err("Could not register omap_device for %s\n", pdev_name);
214 static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
215 int pdev_id, void *pdata, int pdata_len,
216 struct platform_device *parent)
218 struct platform_device *pdev;
221 pdev = platform_device_alloc(pdev_name, pdev_id);
223 pr_err("Could not create pdev for %s\n", pdev_name);
229 pdev->dev.parent = &parent->dev;
232 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
234 dev_set_name(&pdev->dev, "%s", pdev->name);
236 r = platform_device_add_data(pdev, pdata, pdata_len);
238 pr_err("Could not set pdata for %s\n", pdev_name);
242 r = platform_device_add(pdev);
244 pr_err("Could not register platform_device for %s\n", pdev_name);
254 static enum omapdss_version __init omap_display_get_version(void)
256 if (cpu_is_omap24xx())
257 return OMAPDSS_VER_OMAP24xx;
258 else if (cpu_is_omap3630())
259 return OMAPDSS_VER_OMAP3630;
260 else if (cpu_is_omap34xx()) {
261 if (soc_is_am35xx()) {
262 return OMAPDSS_VER_AM35xx;
264 if (omap_rev() < OMAP3430_REV_ES3_0)
265 return OMAPDSS_VER_OMAP34xx_ES1;
267 return OMAPDSS_VER_OMAP34xx_ES3;
269 } else if (omap_rev() == OMAP4430_REV_ES1_0)
270 return OMAPDSS_VER_OMAP4430_ES1;
271 else if (omap_rev() == OMAP4430_REV_ES2_0 ||
272 omap_rev() == OMAP4430_REV_ES2_1 ||
273 omap_rev() == OMAP4430_REV_ES2_2)
274 return OMAPDSS_VER_OMAP4430_ES2;
275 else if (cpu_is_omap44xx())
276 return OMAPDSS_VER_OMAP4;
277 else if (soc_is_omap54xx())
278 return OMAPDSS_VER_OMAP5;
280 return OMAPDSS_VER_UNKNOWN;
283 int __init omap_display_init(struct omap_dss_board_info *board_data)
286 struct platform_device *pdev;
288 const struct omap_dss_hwmod_data *curr_dss_hwmod;
289 struct platform_device *dss_pdev;
290 enum omapdss_version ver;
292 /* create omapdss device */
294 ver = omap_display_get_version();
296 if (ver == OMAPDSS_VER_UNKNOWN) {
297 pr_err("DSS not supported on this SoC\n");
301 board_data->version = ver;
302 board_data->dsi_enable_pads = omap_dsi_enable_pads;
303 board_data->dsi_disable_pads = omap_dsi_disable_pads;
304 board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
305 board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
307 omap_display_device.dev.platform_data = board_data;
309 r = platform_device_register(&omap_display_device);
311 pr_err("Unable to register omapdss device\n");
315 /* create devices for dss hwmods */
317 if (cpu_is_omap24xx()) {
318 curr_dss_hwmod = omap2_dss_hwmod_data;
319 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
320 } else if (cpu_is_omap34xx()) {
321 curr_dss_hwmod = omap3_dss_hwmod_data;
322 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
324 curr_dss_hwmod = omap4_dss_hwmod_data;
325 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
329 * First create the pdev for dss_core, which is used as a parent device
330 * by the other dss pdevs. Note: dss_core has to be the first item in
333 dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
334 curr_dss_hwmod[0].id,
335 curr_dss_hwmod[0].oh_name,
336 board_data, sizeof(*board_data),
339 if (IS_ERR(dss_pdev)) {
340 pr_err("Could not build omap_device for %s\n",
341 curr_dss_hwmod[0].oh_name);
343 return PTR_ERR(dss_pdev);
346 for (i = 1; i < oh_count; i++) {
347 pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
348 curr_dss_hwmod[i].id,
349 curr_dss_hwmod[i].oh_name,
350 board_data, sizeof(*board_data),
354 pr_err("Could not build omap_device for %s\n",
355 curr_dss_hwmod[i].oh_name);
357 return PTR_ERR(pdev);
361 /* Create devices for DPI and SDI */
363 pdev = create_simple_dss_pdev("omapdss_dpi", 0,
364 board_data, sizeof(*board_data), dss_pdev);
366 pr_err("Could not build platform_device for omapdss_dpi\n");
367 return PTR_ERR(pdev);
370 if (cpu_is_omap34xx()) {
371 pdev = create_simple_dss_pdev("omapdss_sdi", 0,
372 board_data, sizeof(*board_data), dss_pdev);
374 pr_err("Could not build platform_device for omapdss_sdi\n");
375 return PTR_ERR(pdev);
379 /* create DRM device */
382 pr_err("Unable to register omapdrm device\n");
386 /* create vrfb device */
387 r = omap_init_vrfb();
389 pr_err("Unable to register omapvrfb device\n");
393 /* create FB device */
396 pr_err("Unable to register omapfb device\n");
400 /* create V4L2 display device */
401 r = omap_init_vout();
403 pr_err("Unable to register omap_vout device\n");
410 static void dispc_disable_outputs(void)
413 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
415 struct omap_dss_dispc_dev_attr *da;
416 struct omap_hwmod *oh;
418 oh = omap_hwmod_lookup("dss_dispc");
420 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
425 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
429 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
431 /* store value of LCDENABLE and DIGITENABLE bits */
432 v = omap_hwmod_read(oh, DISPC_CONTROL);
433 lcd_en = v & LCD_EN_MASK;
434 digit_en = v & DIGIT_EN_MASK;
436 /* store value of LCDENABLE for LCD2 */
437 if (da->manager_count > 2) {
438 v = omap_hwmod_read(oh, DISPC_CONTROL2);
439 lcd2_en = v & LCD_EN_MASK;
442 /* store value of LCDENABLE for LCD3 */
443 if (da->manager_count > 3) {
444 v = omap_hwmod_read(oh, DISPC_CONTROL3);
445 lcd3_en = v & LCD_EN_MASK;
448 if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
449 return; /* no managers currently enabled */
452 * If any manager was enabled, we need to disable it before
453 * DSS clocks are disabled or DISPC module is reset
456 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
459 if (da->has_framedonetv_irq) {
460 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
462 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
463 1 << EVSYNC_ODD_IRQ_SHIFT;
468 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
470 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
473 * clear any previous FRAMEDONE, FRAMEDONETV,
474 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
476 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
478 /* disable LCD and TV managers */
479 v = omap_hwmod_read(oh, DISPC_CONTROL);
480 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
481 omap_hwmod_write(v, oh, DISPC_CONTROL);
483 /* disable LCD2 manager */
484 if (da->manager_count > 2) {
485 v = omap_hwmod_read(oh, DISPC_CONTROL2);
487 omap_hwmod_write(v, oh, DISPC_CONTROL2);
490 /* disable LCD3 manager */
491 if (da->manager_count > 3) {
492 v = omap_hwmod_read(oh, DISPC_CONTROL3);
494 omap_hwmod_write(v, oh, DISPC_CONTROL3);
498 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
501 if (i > FRAMEDONE_IRQ_TIMEOUT) {
502 pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
509 int omap_dss_reset(struct omap_hwmod *oh)
511 struct omap_hwmod_opt_clk *oc;
515 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
516 pr_err("dss_core: hwmod data doesn't contain reset data\n");
520 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
522 clk_prepare_enable(oc->_clk);
524 dispc_disable_outputs();
526 /* clear SDI registers */
527 if (cpu_is_omap3430()) {
528 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
529 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
533 * clear DSS_CONTROL register to switch DSS clock sources to
536 omap_hwmod_write(0x0, oh, DSS_CONTROL);
538 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
539 & SYSS_RESETDONE_MASK),
540 MAX_MODULE_SOFTRESET_WAIT, c);
542 if (c == MAX_MODULE_SOFTRESET_WAIT)
543 pr_warning("dss_core: waiting for reset to finish failed\n");
545 pr_debug("dss_core: softreset done\n");
547 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
549 clk_disable_unprepare(oc->_clk);
551 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;