arch/arm/mach-omap2/clock44xx_data.c

   1 /*
   2  * OMAP4 Clock data
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  *
  21  * XXX Some of the ES1 clocks have been removed/changed; once support
  22  * is added for discriminating clocks by ES level, these should be added back
  23  * in.
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/clk.h>
  29 #include <plat/clkdev_omap.h>
  30
  31 #include "clock.h"
  32 #include "clock44xx.h"
  33 #include "cm1_44xx.h"
  34 #include "cm2_44xx.h"
  35 #include "cm-regbits-44xx.h"
  36 #include "prm44xx.h"
  37 #include "prm44xx.h"
  38 #include "prm-regbits-44xx.h"
  39 #include "control.h"
  40 #include "scrm44xx.h"
  41
  42 /* OMAP4 modulemode control */
  43 #define OMAP4430_MODULEMODE_HWCTRL                      0
  44 #define OMAP4430_MODULEMODE_SWCTRL                      1
  45
  46 /* Root clocks */
  47
  48 static struct clk extalt_clkin_ck = {
  49         .name           = "extalt_clkin_ck",
  50         .rate           = 59000000,
  51         .ops            = &clkops_null,
  52 };
  53
  54 static struct clk pad_clks_ck = {
  55         .name           = "pad_clks_ck",
  56         .rate           = 12000000,
  57         .ops            = &clkops_omap2_dflt,
  58         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
  59         .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
  60 };
  61
  62 static struct clk pad_slimbus_core_clks_ck = {
  63         .name           = "pad_slimbus_core_clks_ck",
  64         .rate           = 12000000,
  65         .ops            = &clkops_null,
  66 };
  67
  68 static struct clk secure_32k_clk_src_ck = {
  69         .name           = "secure_32k_clk_src_ck",
  70         .rate           = 32768,
  71         .ops            = &clkops_null,
  72 };
  73
  74 static struct clk slimbus_clk = {
  75         .name           = "slimbus_clk",
  76         .rate           = 12000000,
  77         .ops            = &clkops_omap2_dflt,
  78         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
  79         .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
  80 };
  81
  82 static struct clk sys_32k_ck = {
  83         .name           = "sys_32k_ck",
  84         .rate           = 32768,
  85         .ops            = &clkops_null,
  86 };
  87
  88 static struct clk virt_12000000_ck = {
  89         .name           = "virt_12000000_ck",
  90         .ops            = &clkops_null,
  91         .rate           = 12000000,
  92 };
  93
  94 static struct clk virt_13000000_ck = {
  95         .name           = "virt_13000000_ck",
  96         .ops            = &clkops_null,
  97         .rate           = 13000000,
  98 };
  99
 100 static struct clk virt_16800000_ck = {
 101         .name           = "virt_16800000_ck",
 102         .ops            = &clkops_null,
 103         .rate           = 16800000,
 104 };
 105
 106 static struct clk virt_19200000_ck = {
 107         .name           = "virt_19200000_ck",
 108         .ops            = &clkops_null,
 109         .rate           = 19200000,
 110 };
 111
 112 static struct clk virt_26000000_ck = {
 113         .name           = "virt_26000000_ck",
 114         .ops            = &clkops_null,
 115         .rate           = 26000000,
 116 };
 117
 118 static struct clk virt_27000000_ck = {
 119         .name           = "virt_27000000_ck",
 120         .ops            = &clkops_null,
 121         .rate           = 27000000,
 122 };
 123
 124 static struct clk virt_38400000_ck = {
 125         .name           = "virt_38400000_ck",
 126         .ops            = &clkops_null,
 127         .rate           = 38400000,
 128 };
 129
 130 static const struct clksel_rate div_1_0_rates[] = {
 131         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 132         { .div = 0 },
 133 };
 134
 135 static const struct clksel_rate div_1_1_rates[] = {
 136         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 137         { .div = 0 },
 138 };
 139
 140 static const struct clksel_rate div_1_2_rates[] = {
 141         { .div = 1, .val = 2, .flags = RATE_IN_4430 },
 142         { .div = 0 },
 143 };
 144
 145 static const struct clksel_rate div_1_3_rates[] = {
 146         { .div = 1, .val = 3, .flags = RATE_IN_4430 },
 147         { .div = 0 },
 148 };
 149
 150 static const struct clksel_rate div_1_4_rates[] = {
 151         { .div = 1, .val = 4, .flags = RATE_IN_4430 },
 152         { .div = 0 },
 153 };
 154
 155 static const struct clksel_rate div_1_5_rates[] = {
 156         { .div = 1, .val = 5, .flags = RATE_IN_4430 },
 157         { .div = 0 },
 158 };
 159
 160 static const struct clksel_rate div_1_6_rates[] = {
 161         { .div = 1, .val = 6, .flags = RATE_IN_4430 },
 162         { .div = 0 },
 163 };
 164
 165 static const struct clksel_rate div_1_7_rates[] = {
 166         { .div = 1, .val = 7, .flags = RATE_IN_4430 },
 167         { .div = 0 },
 168 };
 169
 170 static const struct clksel sys_clkin_sel[] = {
 171         { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
 172         { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
 173         { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
 174         { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
 175         { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
 176         { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
 177         { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
 178         { .parent = NULL },
 179 };
 180
 181 static struct clk sys_clkin_ck = {
 182         .name           = "sys_clkin_ck",
 183         .rate           = 38400000,
 184         .clksel         = sys_clkin_sel,
 185         .init           = &omap2_init_clksel_parent,
 186         .clksel_reg     = OMAP4430_CM_SYS_CLKSEL,
 187         .clksel_mask    = OMAP4430_SYS_CLKSEL_MASK,
 188         .ops            = &clkops_null,
 189         .recalc         = &omap2_clksel_recalc,
 190 };
 191
 192 static struct clk tie_low_clock_ck = {
 193         .name           = "tie_low_clock_ck",
 194         .rate           = 0,
 195         .ops            = &clkops_null,
 196 };
 197
 198 static struct clk utmi_phy_clkout_ck = {
 199         .name           = "utmi_phy_clkout_ck",
 200         .rate           = 60000000,
 201         .ops            = &clkops_null,
 202 };
 203
 204 static struct clk xclk60mhsp1_ck = {
 205         .name           = "xclk60mhsp1_ck",
 206         .rate           = 60000000,
 207         .ops            = &clkops_null,
 208 };
 209
 210 static struct clk xclk60mhsp2_ck = {
 211         .name           = "xclk60mhsp2_ck",
 212         .rate           = 60000000,
 213         .ops            = &clkops_null,
 214 };
 215
 216 static struct clk xclk60motg_ck = {
 217         .name           = "xclk60motg_ck",
 218         .rate           = 60000000,
 219         .ops            = &clkops_null,
 220 };
 221
 222 /* Module clocks and DPLL outputs */
 223
 224 static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
 225         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 226         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
 227         { .parent = NULL },
 228 };
 229
 230 static struct clk abe_dpll_bypass_clk_mux_ck = {
 231         .name           = "abe_dpll_bypass_clk_mux_ck",
 232         .parent         = &sys_clkin_ck,
 233         .ops            = &clkops_null,
 234         .recalc         = &followparent_recalc,
 235 };
 236
 237 static struct clk abe_dpll_refclk_mux_ck = {
 238         .name           = "abe_dpll_refclk_mux_ck",
 239         .parent         = &sys_clkin_ck,
 240         .clksel         = abe_dpll_bypass_clk_mux_sel,
 241         .init           = &omap2_init_clksel_parent,
 242         .clksel_reg     = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
 243         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
 244         .ops            = &clkops_null,
 245         .recalc         = &omap2_clksel_recalc,
 246 };
 247
 248 /* DPLL_ABE */
 249 static struct dpll_data dpll_abe_dd = {
 250         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
 251         .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
 252         .clk_ref        = &abe_dpll_refclk_mux_ck,
 253         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
 254         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 255         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
 256         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
 257         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 258         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 259         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 260         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 261         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 262         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 263         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 264         .min_divider    = 1,
 265 };
 266
 267
 268 static struct clk dpll_abe_ck = {
 269         .name           = "dpll_abe_ck",
 270         .parent         = &abe_dpll_refclk_mux_ck,
 271         .dpll_data      = &dpll_abe_dd,
 272         .init           = &omap2_init_dpll_parent,
 273         .ops            = &clkops_omap3_noncore_dpll_ops,
 274         .recalc         = &omap3_dpll_recalc,
 275         .round_rate     = &omap2_dpll_round_rate,
 276         .set_rate       = &omap3_noncore_dpll_set_rate,
 277 };
 278
 279 static struct clk dpll_abe_x2_ck = {
 280         .name           = "dpll_abe_x2_ck",
 281         .parent         = &dpll_abe_ck,
 282         .ops            = &clkops_null,
 283         .recalc         = &omap3_clkoutx2_recalc,
 284 };
 285
 286 static const struct clksel_rate div31_1to31_rates[] = {
 287         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 288         { .div = 2, .val = 2, .flags = RATE_IN_4430 },
 289         { .div = 3, .val = 3, .flags = RATE_IN_4430 },
 290         { .div = 4, .val = 4, .flags = RATE_IN_4430 },
 291         { .div = 5, .val = 5, .flags = RATE_IN_4430 },
 292         { .div = 6, .val = 6, .flags = RATE_IN_4430 },
 293         { .div = 7, .val = 7, .flags = RATE_IN_4430 },
 294         { .div = 8, .val = 8, .flags = RATE_IN_4430 },
 295         { .div = 9, .val = 9, .flags = RATE_IN_4430 },
 296         { .div = 10, .val = 10, .flags = RATE_IN_4430 },
 297         { .div = 11, .val = 11, .flags = RATE_IN_4430 },
 298         { .div = 12, .val = 12, .flags = RATE_IN_4430 },
 299         { .div = 13, .val = 13, .flags = RATE_IN_4430 },
 300         { .div = 14, .val = 14, .flags = RATE_IN_4430 },
 301         { .div = 15, .val = 15, .flags = RATE_IN_4430 },
 302         { .div = 16, .val = 16, .flags = RATE_IN_4430 },
 303         { .div = 17, .val = 17, .flags = RATE_IN_4430 },
 304         { .div = 18, .val = 18, .flags = RATE_IN_4430 },
 305         { .div = 19, .val = 19, .flags = RATE_IN_4430 },
 306         { .div = 20, .val = 20, .flags = RATE_IN_4430 },
 307         { .div = 21, .val = 21, .flags = RATE_IN_4430 },
 308         { .div = 22, .val = 22, .flags = RATE_IN_4430 },
 309         { .div = 23, .val = 23, .flags = RATE_IN_4430 },
 310         { .div = 24, .val = 24, .flags = RATE_IN_4430 },
 311         { .div = 25, .val = 25, .flags = RATE_IN_4430 },
 312         { .div = 26, .val = 26, .flags = RATE_IN_4430 },
 313         { .div = 27, .val = 27, .flags = RATE_IN_4430 },
 314         { .div = 28, .val = 28, .flags = RATE_IN_4430 },
 315         { .div = 29, .val = 29, .flags = RATE_IN_4430 },
 316         { .div = 30, .val = 30, .flags = RATE_IN_4430 },
 317         { .div = 31, .val = 31, .flags = RATE_IN_4430 },
 318         { .div = 0 },
 319 };
 320
 321 static const struct clksel dpll_abe_m2x2_div[] = {
 322         { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
 323         { .parent = NULL },
 324 };
 325
 326 static struct clk dpll_abe_m2x2_ck = {
 327         .name           = "dpll_abe_m2x2_ck",
 328         .parent         = &dpll_abe_x2_ck,
 329         .clksel         = dpll_abe_m2x2_div,
 330         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 331         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 332         .ops            = &clkops_null,
 333         .recalc         = &omap2_clksel_recalc,
 334         .round_rate     = &omap2_clksel_round_rate,
 335         .set_rate       = &omap2_clksel_set_rate,
 336 };
 337
 338 static struct clk abe_24m_fclk = {
 339         .name           = "abe_24m_fclk",
 340         .parent         = &dpll_abe_m2x2_ck,
 341         .ops            = &clkops_null,
 342         .recalc         = &followparent_recalc,
 343 };
 344
 345 static const struct clksel_rate div3_1to4_rates[] = {
 346         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 347         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 348         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 349         { .div = 0 },
 350 };
 351
 352 static const struct clksel abe_clk_div[] = {
 353         { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
 354         { .parent = NULL },
 355 };
 356
 357 static struct clk abe_clk = {
 358         .name           = "abe_clk",
 359         .parent         = &dpll_abe_m2x2_ck,
 360         .clksel         = abe_clk_div,
 361         .clksel_reg     = OMAP4430_CM_CLKSEL_ABE,
 362         .clksel_mask    = OMAP4430_CLKSEL_OPP_MASK,
 363         .ops            = &clkops_null,
 364         .recalc         = &omap2_clksel_recalc,
 365         .round_rate     = &omap2_clksel_round_rate,
 366         .set_rate       = &omap2_clksel_set_rate,
 367 };
 368
 369 static const struct clksel_rate div2_1to2_rates[] = {
 370         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 371         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 372         { .div = 0 },
 373 };
 374
 375 static const struct clksel aess_fclk_div[] = {
 376         { .parent = &abe_clk, .rates = div2_1to2_rates },
 377         { .parent = NULL },
 378 };
 379
 380 static struct clk aess_fclk = {
 381         .name           = "aess_fclk",
 382         .parent         = &abe_clk,
 383         .clksel         = aess_fclk_div,
 384         .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 385         .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
 386         .ops            = &clkops_null,
 387         .recalc         = &omap2_clksel_recalc,
 388         .round_rate     = &omap2_clksel_round_rate,
 389         .set_rate       = &omap2_clksel_set_rate,
 390 };
 391
 392 static struct clk dpll_abe_m3x2_ck = {
 393         .name           = "dpll_abe_m3x2_ck",
 394         .parent         = &dpll_abe_x2_ck,
 395         .clksel         = dpll_abe_m2x2_div,
 396         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_ABE,
 397         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 398         .ops            = &clkops_null,
 399         .recalc         = &omap2_clksel_recalc,
 400         .round_rate     = &omap2_clksel_round_rate,
 401         .set_rate       = &omap2_clksel_set_rate,
 402 };
 403
 404 static const struct clksel core_hsd_byp_clk_mux_sel[] = {
 405         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 406         { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
 407         { .parent = NULL },
 408 };
 409
 410 static struct clk core_hsd_byp_clk_mux_ck = {
 411         .name           = "core_hsd_byp_clk_mux_ck",
 412         .parent         = &sys_clkin_ck,
 413         .clksel         = core_hsd_byp_clk_mux_sel,
 414         .init           = &omap2_init_clksel_parent,
 415         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_CORE,
 416         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 417         .ops            = &clkops_null,
 418         .recalc         = &omap2_clksel_recalc,
 419 };
 420
 421 /* DPLL_CORE */
 422 static struct dpll_data dpll_core_dd = {
 423         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
 424         .clk_bypass     = &core_hsd_byp_clk_mux_ck,
 425         .clk_ref        = &sys_clkin_ck,
 426         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
 427         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 428         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
 429         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
 430         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 431         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 432         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 433         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 434         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 435         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 436         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 437         .min_divider    = 1,
 438 };
 439
 440
 441 static struct clk dpll_core_ck = {
 442         .name           = "dpll_core_ck",
 443         .parent         = &sys_clkin_ck,
 444         .dpll_data      = &dpll_core_dd,
 445         .init           = &omap2_init_dpll_parent,
 446         .ops            = &clkops_null,
 447         .recalc         = &omap3_dpll_recalc,
 448 };
 449
 450 static struct clk dpll_core_x2_ck = {
 451         .name           = "dpll_core_x2_ck",
 452         .parent         = &dpll_core_ck,
 453         .ops            = &clkops_null,
 454         .recalc         = &omap3_clkoutx2_recalc,
 455 };
 456
 457 static const struct clksel dpll_core_m6x2_div[] = {
 458         { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
 459         { .parent = NULL },
 460 };
 461
 462 static struct clk dpll_core_m6x2_ck = {
 463         .name           = "dpll_core_m6x2_ck",
 464         .parent         = &dpll_core_x2_ck,
 465         .clksel         = dpll_core_m6x2_div,
 466         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_CORE,
 467         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 468         .ops            = &clkops_null,
 469         .recalc         = &omap2_clksel_recalc,
 470         .round_rate     = &omap2_clksel_round_rate,
 471         .set_rate       = &omap2_clksel_set_rate,
 472 };
 473
 474 static const struct clksel dbgclk_mux_sel[] = {
 475         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 476         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
 477         { .parent = NULL },
 478 };
 479
 480 static struct clk dbgclk_mux_ck = {
 481         .name           = "dbgclk_mux_ck",
 482         .parent         = &sys_clkin_ck,
 483         .ops            = &clkops_null,
 484         .recalc         = &followparent_recalc,
 485 };
 486
 487 static const struct clksel dpll_core_m2_div[] = {
 488         { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
 489         { .parent = NULL },
 490 };
 491
 492 static struct clk dpll_core_m2_ck = {
 493         .name           = "dpll_core_m2_ck",
 494         .parent         = &dpll_core_ck,
 495         .clksel         = dpll_core_m2_div,
 496         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_CORE,
 497         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 498         .ops            = &clkops_null,
 499         .recalc         = &omap2_clksel_recalc,
 500         .round_rate     = &omap2_clksel_round_rate,
 501         .set_rate       = &omap2_clksel_set_rate,
 502 };
 503
 504 static struct clk ddrphy_ck = {
 505         .name           = "ddrphy_ck",
 506         .parent         = &dpll_core_m2_ck,
 507         .ops            = &clkops_null,
 508         .recalc         = &followparent_recalc,
 509 };
 510
 511 static struct clk dpll_core_m5x2_ck = {
 512         .name           = "dpll_core_m5x2_ck",
 513         .parent         = &dpll_core_x2_ck,
 514         .clksel         = dpll_core_m6x2_div,
 515         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_CORE,
 516         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 517         .ops            = &clkops_null,
 518         .recalc         = &omap2_clksel_recalc,
 519         .round_rate     = &omap2_clksel_round_rate,
 520         .set_rate       = &omap2_clksel_set_rate,
 521 };
 522
 523 static const struct clksel div_core_div[] = {
 524         { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
 525         { .parent = NULL },
 526 };
 527
 528 static struct clk div_core_ck = {
 529         .name           = "div_core_ck",
 530         .parent         = &dpll_core_m5x2_ck,
 531         .clksel         = div_core_div,
 532         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
 533         .clksel_mask    = OMAP4430_CLKSEL_CORE_MASK,
 534         .ops            = &clkops_null,
 535         .recalc         = &omap2_clksel_recalc,
 536         .round_rate     = &omap2_clksel_round_rate,
 537         .set_rate       = &omap2_clksel_set_rate,
 538 };
 539
 540 static const struct clksel_rate div4_1to8_rates[] = {
 541         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 542         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 543         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 544         { .div = 8, .val = 3, .flags = RATE_IN_4430 },
 545         { .div = 0 },
 546 };
 547
 548 static const struct clksel div_iva_hs_clk_div[] = {
 549         { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
 550         { .parent = NULL },
 551 };
 552
 553 static struct clk div_iva_hs_clk = {
 554         .name           = "div_iva_hs_clk",
 555         .parent         = &dpll_core_m5x2_ck,
 556         .clksel         = div_iva_hs_clk_div,
 557         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_IVA,
 558         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 559         .ops            = &clkops_null,
 560         .recalc         = &omap2_clksel_recalc,
 561         .round_rate     = &omap2_clksel_round_rate,
 562         .set_rate       = &omap2_clksel_set_rate,
 563 };
 564
 565 static struct clk div_mpu_hs_clk = {
 566         .name           = "div_mpu_hs_clk",
 567         .parent         = &dpll_core_m5x2_ck,
 568         .clksel         = div_iva_hs_clk_div,
 569         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_MPU,
 570         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 571         .ops            = &clkops_null,
 572         .recalc         = &omap2_clksel_recalc,
 573         .round_rate     = &omap2_clksel_round_rate,
 574         .set_rate       = &omap2_clksel_set_rate,
 575 };
 576
 577 static struct clk dpll_core_m4x2_ck = {
 578         .name           = "dpll_core_m4x2_ck",
 579         .parent         = &dpll_core_x2_ck,
 580         .clksel         = dpll_core_m6x2_div,
 581         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_CORE,
 582         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 583         .ops            = &clkops_null,
 584         .recalc         = &omap2_clksel_recalc,
 585         .round_rate     = &omap2_clksel_round_rate,
 586         .set_rate       = &omap2_clksel_set_rate,
 587 };
 588
 589 static struct clk dll_clk_div_ck = {
 590         .name           = "dll_clk_div_ck",
 591         .parent         = &dpll_core_m4x2_ck,
 592         .ops            = &clkops_null,
 593         .recalc         = &followparent_recalc,
 594 };
 595
 596 static const struct clksel dpll_abe_m2_div[] = {
 597         { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
 598         { .parent = NULL },
 599 };
 600
 601 static struct clk dpll_abe_m2_ck = {
 602         .name           = "dpll_abe_m2_ck",
 603         .parent         = &dpll_abe_ck,
 604         .clksel         = dpll_abe_m2_div,
 605         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 606         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 607         .ops            = &clkops_null,
 608         .recalc         = &omap2_clksel_recalc,
 609         .round_rate     = &omap2_clksel_round_rate,
 610         .set_rate       = &omap2_clksel_set_rate,
 611 };
 612
 613 static struct clk dpll_core_m3x2_ck = {
 614         .name           = "dpll_core_m3x2_ck",
 615         .parent         = &dpll_core_x2_ck,
 616         .clksel         = dpll_core_m6x2_div,
 617         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 618         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 619         .ops            = &clkops_omap2_dflt,
 620         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 621         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 622         .recalc         = &omap2_clksel_recalc,
 623         .round_rate     = &omap2_clksel_round_rate,
 624         .set_rate       = &omap2_clksel_set_rate,
 625 };
 626
 627 static struct clk dpll_core_m7x2_ck = {
 628         .name           = "dpll_core_m7x2_ck",
 629         .parent         = &dpll_core_x2_ck,
 630         .clksel         = dpll_core_m6x2_div,
 631         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_CORE,
 632         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 633         .ops            = &clkops_null,
 634         .recalc         = &omap2_clksel_recalc,
 635         .round_rate     = &omap2_clksel_round_rate,
 636         .set_rate       = &omap2_clksel_set_rate,
 637 };
 638
 639 static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
 640         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 641         { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
 642         { .parent = NULL },
 643 };
 644
 645 static struct clk iva_hsd_byp_clk_mux_ck = {
 646         .name           = "iva_hsd_byp_clk_mux_ck",
 647         .parent         = &sys_clkin_ck,
 648         .clksel         = iva_hsd_byp_clk_mux_sel,
 649         .init           = &omap2_init_clksel_parent,
 650         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_IVA,
 651         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 652         .ops            = &clkops_null,
 653         .recalc         = &omap2_clksel_recalc,
 654 };
 655
 656 /* DPLL_IVA */
 657 static struct dpll_data dpll_iva_dd = {
 658         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
 659         .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
 660         .clk_ref        = &sys_clkin_ck,
 661         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
 662         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 663         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
 664         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
 665         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 666         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 667         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 668         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 669         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 670         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 671         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 672         .min_divider    = 1,
 673 };
 674
 675
 676 static struct clk dpll_iva_ck = {
 677         .name           = "dpll_iva_ck",
 678         .parent         = &sys_clkin_ck,
 679         .dpll_data      = &dpll_iva_dd,
 680         .init           = &omap2_init_dpll_parent,
 681         .ops            = &clkops_omap3_noncore_dpll_ops,
 682         .recalc         = &omap3_dpll_recalc,
 683         .round_rate     = &omap2_dpll_round_rate,
 684         .set_rate       = &omap3_noncore_dpll_set_rate,
 685 };
 686
 687 static struct clk dpll_iva_x2_ck = {
 688         .name           = "dpll_iva_x2_ck",
 689         .parent         = &dpll_iva_ck,
 690         .ops            = &clkops_null,
 691         .recalc         = &omap3_clkoutx2_recalc,
 692 };
 693
 694 static const struct clksel dpll_iva_m4x2_div[] = {
 695         { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
 696         { .parent = NULL },
 697 };
 698
 699 static struct clk dpll_iva_m4x2_ck = {
 700         .name           = "dpll_iva_m4x2_ck",
 701         .parent         = &dpll_iva_x2_ck,
 702         .clksel         = dpll_iva_m4x2_div,
 703         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_IVA,
 704         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 705         .ops            = &clkops_null,
 706         .recalc         = &omap2_clksel_recalc,
 707         .round_rate     = &omap2_clksel_round_rate,
 708         .set_rate       = &omap2_clksel_set_rate,
 709 };
 710
 711 static struct clk dpll_iva_m5x2_ck = {
 712         .name           = "dpll_iva_m5x2_ck",
 713         .parent         = &dpll_iva_x2_ck,
 714         .clksel         = dpll_iva_m4x2_div,
 715         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_IVA,
 716         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 717         .ops            = &clkops_null,
 718         .recalc         = &omap2_clksel_recalc,
 719         .round_rate     = &omap2_clksel_round_rate,
 720         .set_rate       = &omap2_clksel_set_rate,
 721 };
 722
 723 /* DPLL_MPU */
 724 static struct dpll_data dpll_mpu_dd = {
 725         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
 726         .clk_bypass     = &div_mpu_hs_clk,
 727         .clk_ref        = &sys_clkin_ck,
 728         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
 729         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 730         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
 731         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
 732         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 733         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 734         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 735         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 736         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 737         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 738         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 739         .min_divider    = 1,
 740 };
 741
 742
 743 static struct clk dpll_mpu_ck = {
 744         .name           = "dpll_mpu_ck",
 745         .parent         = &sys_clkin_ck,
 746         .dpll_data      = &dpll_mpu_dd,
 747         .init           = &omap2_init_dpll_parent,
 748         .ops            = &clkops_omap3_noncore_dpll_ops,
 749         .recalc         = &omap3_dpll_recalc,
 750         .round_rate     = &omap2_dpll_round_rate,
 751         .set_rate       = &omap3_noncore_dpll_set_rate,
 752 };
 753
 754 static const struct clksel dpll_mpu_m2_div[] = {
 755         { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
 756         { .parent = NULL },
 757 };
 758
 759 static struct clk dpll_mpu_m2_ck = {
 760         .name           = "dpll_mpu_m2_ck",
 761         .parent         = &dpll_mpu_ck,
 762         .clksel         = dpll_mpu_m2_div,
 763         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_MPU,
 764         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 765         .ops            = &clkops_null,
 766         .recalc         = &omap2_clksel_recalc,
 767         .round_rate     = &omap2_clksel_round_rate,
 768         .set_rate       = &omap2_clksel_set_rate,
 769 };
 770
 771 static struct clk per_hs_clk_div_ck = {
 772         .name           = "per_hs_clk_div_ck",
 773         .parent         = &dpll_abe_m3x2_ck,
 774         .ops            = &clkops_null,
 775         .recalc         = &followparent_recalc,
 776 };
 777
 778 static const struct clksel per_hsd_byp_clk_mux_sel[] = {
 779         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 780         { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
 781         { .parent = NULL },
 782 };
 783
 784 static struct clk per_hsd_byp_clk_mux_ck = {
 785         .name           = "per_hsd_byp_clk_mux_ck",
 786         .parent         = &sys_clkin_ck,
 787         .clksel         = per_hsd_byp_clk_mux_sel,
 788         .init           = &omap2_init_clksel_parent,
 789         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_PER,
 790         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 791         .ops            = &clkops_null,
 792         .recalc         = &omap2_clksel_recalc,
 793 };
 794
 795 /* DPLL_PER */
 796 static struct dpll_data dpll_per_dd = {
 797         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
 798         .clk_bypass     = &per_hsd_byp_clk_mux_ck,
 799         .clk_ref        = &sys_clkin_ck,
 800         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
 801         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 802         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
 803         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
 804         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 805         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 806         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 807         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 808         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 809         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 810         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 811         .min_divider    = 1,
 812 };
 813
 814
 815 static struct clk dpll_per_ck = {
 816         .name           = "dpll_per_ck",
 817         .parent         = &sys_clkin_ck,
 818         .dpll_data      = &dpll_per_dd,
 819         .init           = &omap2_init_dpll_parent,
 820         .ops            = &clkops_omap3_noncore_dpll_ops,
 821         .recalc         = &omap3_dpll_recalc,
 822         .round_rate     = &omap2_dpll_round_rate,
 823         .set_rate       = &omap3_noncore_dpll_set_rate,
 824 };
 825
 826 static const struct clksel dpll_per_m2_div[] = {
 827         { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
 828         { .parent = NULL },
 829 };
 830
 831 static struct clk dpll_per_m2_ck = {
 832         .name           = "dpll_per_m2_ck",
 833         .parent         = &dpll_per_ck,
 834         .clksel         = dpll_per_m2_div,
 835         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 836         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 837         .ops            = &clkops_null,
 838         .recalc         = &omap2_clksel_recalc,
 839         .round_rate     = &omap2_clksel_round_rate,
 840         .set_rate       = &omap2_clksel_set_rate,
 841 };
 842
 843 static struct clk dpll_per_x2_ck = {
 844         .name           = "dpll_per_x2_ck",
 845         .parent         = &dpll_per_ck,
 846         .ops            = &clkops_null,
 847         .recalc         = &omap3_clkoutx2_recalc,
 848 };
 849
 850 static const struct clksel dpll_per_m2x2_div[] = {
 851         { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
 852         { .parent = NULL },
 853 };
 854
 855 static struct clk dpll_per_m2x2_ck = {
 856         .name           = "dpll_per_m2x2_ck",
 857         .parent         = &dpll_per_x2_ck,
 858         .clksel         = dpll_per_m2x2_div,
 859         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 860         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 861         .ops            = &clkops_null,
 862         .recalc         = &omap2_clksel_recalc,
 863         .round_rate     = &omap2_clksel_round_rate,
 864         .set_rate       = &omap2_clksel_set_rate,
 865 };
 866
 867 static struct clk dpll_per_m3x2_ck = {
 868         .name           = "dpll_per_m3x2_ck",
 869         .parent         = &dpll_per_x2_ck,
 870         .clksel         = dpll_per_m2x2_div,
 871         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 872         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 873         .ops            = &clkops_omap2_dflt,
 874         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 875         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 876         .recalc         = &omap2_clksel_recalc,
 877         .round_rate     = &omap2_clksel_round_rate,
 878         .set_rate       = &omap2_clksel_set_rate,
 879 };
 880
 881 static struct clk dpll_per_m4x2_ck = {
 882         .name           = "dpll_per_m4x2_ck",
 883         .parent         = &dpll_per_x2_ck,
 884         .clksel         = dpll_per_m2x2_div,
 885         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_PER,
 886         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 887         .ops            = &clkops_null,
 888         .recalc         = &omap2_clksel_recalc,
 889         .round_rate     = &omap2_clksel_round_rate,
 890         .set_rate       = &omap2_clksel_set_rate,
 891 };
 892
 893 static struct clk dpll_per_m5x2_ck = {
 894         .name           = "dpll_per_m5x2_ck",
 895         .parent         = &dpll_per_x2_ck,
 896         .clksel         = dpll_per_m2x2_div,
 897         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_PER,
 898         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 899         .ops            = &clkops_null,
 900         .recalc         = &omap2_clksel_recalc,
 901         .round_rate     = &omap2_clksel_round_rate,
 902         .set_rate       = &omap2_clksel_set_rate,
 903 };
 904
 905 static struct clk dpll_per_m6x2_ck = {
 906         .name           = "dpll_per_m6x2_ck",
 907         .parent         = &dpll_per_x2_ck,
 908         .clksel         = dpll_per_m2x2_div,
 909         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_PER,
 910         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 911         .ops            = &clkops_null,
 912         .recalc         = &omap2_clksel_recalc,
 913         .round_rate     = &omap2_clksel_round_rate,
 914         .set_rate       = &omap2_clksel_set_rate,
 915 };
 916
 917 static struct clk dpll_per_m7x2_ck = {
 918         .name           = "dpll_per_m7x2_ck",
 919         .parent         = &dpll_per_x2_ck,
 920         .clksel         = dpll_per_m2x2_div,
 921         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_PER,
 922         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 923         .ops            = &clkops_null,
 924         .recalc         = &omap2_clksel_recalc,
 925         .round_rate     = &omap2_clksel_round_rate,
 926         .set_rate       = &omap2_clksel_set_rate,
 927 };
 928
 929 /* DPLL_UNIPRO */
 930 static struct dpll_data dpll_unipro_dd = {
 931         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
 932         .clk_bypass     = &sys_clkin_ck,
 933         .clk_ref        = &sys_clkin_ck,
 934         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
 935         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 936         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
 937         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
 938         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 939         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 940         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 941         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 942         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 943         .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
 944         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 945         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 946         .min_divider    = 1,
 947 };
 948
 949
 950 static struct clk dpll_unipro_ck = {
 951         .name           = "dpll_unipro_ck",
 952         .parent         = &sys_clkin_ck,
 953         .dpll_data      = &dpll_unipro_dd,
 954         .init           = &omap2_init_dpll_parent,
 955         .ops            = &clkops_omap3_noncore_dpll_ops,
 956         .recalc         = &omap3_dpll_recalc,
 957         .round_rate     = &omap2_dpll_round_rate,
 958         .set_rate       = &omap3_noncore_dpll_set_rate,
 959 };
 960
 961 static struct clk dpll_unipro_x2_ck = {
 962         .name           = "dpll_unipro_x2_ck",
 963         .parent         = &dpll_unipro_ck,
 964         .ops            = &clkops_null,
 965         .recalc         = &omap3_clkoutx2_recalc,
 966 };
 967
 968 static const struct clksel dpll_unipro_m2x2_div[] = {
 969         { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
 970         { .parent = NULL },
 971 };
 972
 973 static struct clk dpll_unipro_m2x2_ck = {
 974         .name           = "dpll_unipro_m2x2_ck",
 975         .parent         = &dpll_unipro_x2_ck,
 976         .clksel         = dpll_unipro_m2x2_div,
 977         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
 978         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 979         .ops            = &clkops_null,
 980         .recalc         = &omap2_clksel_recalc,
 981         .round_rate     = &omap2_clksel_round_rate,
 982         .set_rate       = &omap2_clksel_set_rate,
 983 };
 984
 985 static struct clk usb_hs_clk_div_ck = {
 986         .name           = "usb_hs_clk_div_ck",
 987         .parent         = &dpll_abe_m3x2_ck,
 988         .ops            = &clkops_null,
 989         .recalc         = &followparent_recalc,
 990 };
 991
 992 /* DPLL_USB */
 993 static struct dpll_data dpll_usb_dd = {
 994         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
 995         .clk_bypass     = &usb_hs_clk_div_ck,
 996         .flags          = DPLL_J_TYPE,
 997         .clk_ref        = &sys_clkin_ck,
 998         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
 999         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
1000         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
1001         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
1002         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
1003         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
1004         .enable_mask    = OMAP4430_DPLL_EN_MASK,
1005         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
1006         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
1007         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
1008         .max_divider    = OMAP4430_MAX_DPLL_DIV,
1009         .min_divider    = 1,
1010 };
1011
1012
1013 static struct clk dpll_usb_ck = {
1014         .name           = "dpll_usb_ck",
1015         .parent         = &sys_clkin_ck,
1016         .dpll_data      = &dpll_usb_dd,
1017         .init           = &omap2_init_dpll_parent,
1018         .ops            = &clkops_omap3_noncore_dpll_ops,
1019         .recalc         = &omap3_dpll_recalc,
1020         .round_rate     = &omap2_dpll_round_rate,
1021         .set_rate       = &omap3_noncore_dpll_set_rate,
1022 };
1023
1024 static struct clk dpll_usb_clkdcoldo_ck = {
1025         .name           = "dpll_usb_clkdcoldo_ck",
1026         .parent         = &dpll_usb_ck,
1027         .ops            = &clkops_null,
1028         .recalc         = &followparent_recalc,
1029 };
1030
1031 static const struct clksel dpll_usb_m2_div[] = {
1032         { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
1033         { .parent = NULL },
1034 };
1035
1036 static struct clk dpll_usb_m2_ck = {
1037         .name           = "dpll_usb_m2_ck",
1038         .parent         = &dpll_usb_ck,
1039         .clksel         = dpll_usb_m2_div,
1040         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_USB,
1041         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
1042         .ops            = &clkops_null,
1043         .recalc         = &omap2_clksel_recalc,
1044         .round_rate     = &omap2_clksel_round_rate,
1045         .set_rate       = &omap2_clksel_set_rate,
1046 };
1047
1048 static const struct clksel ducati_clk_mux_sel[] = {
1049         { .parent = &div_core_ck, .rates = div_1_0_rates },
1050         { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
1051         { .parent = NULL },
1052 };
1053
1054 static struct clk ducati_clk_mux_ck = {
1055         .name           = "ducati_clk_mux_ck",
1056         .parent         = &div_core_ck,
1057         .clksel         = ducati_clk_mux_sel,
1058         .init           = &omap2_init_clksel_parent,
1059         .clksel_reg     = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
1060         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1061         .ops            = &clkops_null,
1062         .recalc         = &omap2_clksel_recalc,
1063 };
1064
1065 static struct clk func_12m_fclk = {
1066         .name           = "func_12m_fclk",
1067         .parent         = &dpll_per_m2x2_ck,
1068         .ops            = &clkops_null,
1069         .recalc         = &followparent_recalc,
1070 };
1071
1072 static struct clk func_24m_clk = {
1073         .name           = "func_24m_clk",
1074         .parent         = &dpll_per_m2_ck,
1075         .ops            = &clkops_null,
1076         .recalc         = &followparent_recalc,
1077 };
1078
1079 static struct clk func_24mc_fclk = {
1080         .name           = "func_24mc_fclk",
1081         .parent         = &dpll_per_m2x2_ck,
1082         .ops            = &clkops_null,
1083         .recalc         = &followparent_recalc,
1084 };
1085
1086 static const struct clksel_rate div2_4to8_rates[] = {
1087         { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1088         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1089         { .div = 0 },
1090 };
1091
1092 static const struct clksel func_48m_fclk_div[] = {
1093         { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1094         { .parent = NULL },
1095 };
1096
1097 static struct clk func_48m_fclk = {
1098         .name           = "func_48m_fclk",
1099         .parent         = &dpll_per_m2x2_ck,
1100         .clksel         = func_48m_fclk_div,
1101         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1102         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1103         .ops            = &clkops_null,
1104         .recalc         = &omap2_clksel_recalc,
1105         .round_rate     = &omap2_clksel_round_rate,
1106         .set_rate       = &omap2_clksel_set_rate,
1107 };
1108
1109 static struct clk func_48mc_fclk = {
1110         .name           = "func_48mc_fclk",
1111         .parent         = &dpll_per_m2x2_ck,
1112         .ops            = &clkops_null,
1113         .recalc         = &followparent_recalc,
1114 };
1115
1116 static const struct clksel_rate div2_2to4_rates[] = {
1117         { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1118         { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1119         { .div = 0 },
1120 };
1121
1122 static const struct clksel func_64m_fclk_div[] = {
1123         { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
1124         { .parent = NULL },
1125 };
1126
1127 static struct clk func_64m_fclk = {
1128         .name           = "func_64m_fclk",
1129         .parent         = &dpll_per_m4x2_ck,
1130         .clksel         = func_64m_fclk_div,
1131         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1132         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1133         .ops            = &clkops_null,
1134         .recalc         = &omap2_clksel_recalc,
1135         .round_rate     = &omap2_clksel_round_rate,
1136         .set_rate       = &omap2_clksel_set_rate,
1137 };
1138
1139 static const struct clksel func_96m_fclk_div[] = {
1140         { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1141         { .parent = NULL },
1142 };
1143
1144 static struct clk func_96m_fclk = {
1145         .name           = "func_96m_fclk",
1146         .parent         = &dpll_per_m2x2_ck,
1147         .clksel         = func_96m_fclk_div,
1148         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1149         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1150         .ops            = &clkops_null,
1151         .recalc         = &omap2_clksel_recalc,
1152         .round_rate     = &omap2_clksel_round_rate,
1153         .set_rate       = &omap2_clksel_set_rate,
1154 };
1155
1156 static const struct clksel hsmmc6_fclk_sel[] = {
1157         { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1158         { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1159         { .parent = NULL },
1160 };
1161
1162 static struct clk hsmmc6_fclk = {
1163         .name           = "hsmmc6_fclk",
1164         .parent         = &func_64m_fclk,
1165         .ops            = &clkops_null,
1166         .recalc         = &followparent_recalc,
1167 };
1168
1169 static const struct clksel_rate div2_1to8_rates[] = {
1170         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1171         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1172         { .div = 0 },
1173 };
1174
1175 static const struct clksel init_60m_fclk_div[] = {
1176         { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1177         { .parent = NULL },
1178 };
1179
1180 static struct clk init_60m_fclk = {
1181         .name           = "init_60m_fclk",
1182         .parent         = &dpll_usb_m2_ck,
1183         .clksel         = init_60m_fclk_div,
1184         .clksel_reg     = OMAP4430_CM_CLKSEL_USB_60MHZ,
1185         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1186         .ops            = &clkops_null,
1187         .recalc         = &omap2_clksel_recalc,
1188         .round_rate     = &omap2_clksel_round_rate,
1189         .set_rate       = &omap2_clksel_set_rate,
1190 };
1191
1192 static const struct clksel l3_div_div[] = {
1193         { .parent = &div_core_ck, .rates = div2_1to2_rates },
1194         { .parent = NULL },
1195 };
1196
1197 static struct clk l3_div_ck = {
1198         .name           = "l3_div_ck",
1199         .parent         = &div_core_ck,
1200         .clksel         = l3_div_div,
1201         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1202         .clksel_mask    = OMAP4430_CLKSEL_L3_MASK,
1203         .ops            = &clkops_null,
1204         .recalc         = &omap2_clksel_recalc,
1205         .round_rate     = &omap2_clksel_round_rate,
1206         .set_rate       = &omap2_clksel_set_rate,
1207 };
1208
1209 static const struct clksel l4_div_div[] = {
1210         { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1211         { .parent = NULL },
1212 };
1213
1214 static struct clk l4_div_ck = {
1215         .name           = "l4_div_ck",
1216         .parent         = &l3_div_ck,
1217         .clksel         = l4_div_div,
1218         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1219         .clksel_mask    = OMAP4430_CLKSEL_L4_MASK,
1220         .ops            = &clkops_null,
1221         .recalc         = &omap2_clksel_recalc,
1222         .round_rate     = &omap2_clksel_round_rate,
1223         .set_rate       = &omap2_clksel_set_rate,
1224 };
1225
1226 static struct clk lp_clk_div_ck = {
1227         .name           = "lp_clk_div_ck",
1228         .parent         = &dpll_abe_m2x2_ck,
1229         .ops            = &clkops_null,
1230         .recalc         = &followparent_recalc,
1231 };
1232
1233 static const struct clksel l4_wkup_clk_mux_sel[] = {
1234         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1235         { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1236         { .parent = NULL },
1237 };
1238
1239 static struct clk l4_wkup_clk_mux_ck = {
1240         .name           = "l4_wkup_clk_mux_ck",
1241         .parent         = &sys_clkin_ck,
1242         .clksel         = l4_wkup_clk_mux_sel,
1243         .init           = &omap2_init_clksel_parent,
1244         .clksel_reg     = OMAP4430_CM_L4_WKUP_CLKSEL,
1245         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1246         .ops            = &clkops_null,
1247         .recalc         = &omap2_clksel_recalc,
1248 };
1249
1250 static const struct clksel per_abe_nc_fclk_div[] = {
1251         { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1252         { .parent = NULL },
1253 };
1254
1255 static struct clk per_abe_nc_fclk = {
1256         .name           = "per_abe_nc_fclk",
1257         .parent         = &dpll_abe_m2_ck,
1258         .clksel         = per_abe_nc_fclk_div,
1259         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1260         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1261         .ops            = &clkops_null,
1262         .recalc         = &omap2_clksel_recalc,
1263         .round_rate     = &omap2_clksel_round_rate,
1264         .set_rate       = &omap2_clksel_set_rate,
1265 };
1266
1267 static const struct clksel mcasp2_fclk_sel[] = {
1268         { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1269         { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1270         { .parent = NULL },
1271 };
1272
1273 static struct clk mcasp2_fclk = {
1274         .name           = "mcasp2_fclk",
1275         .parent         = &func_96m_fclk,
1276         .ops            = &clkops_null,
1277         .recalc         = &followparent_recalc,
1278 };
1279
1280 static struct clk mcasp3_fclk = {
1281         .name           = "mcasp3_fclk",
1282         .parent         = &func_96m_fclk,
1283         .ops            = &clkops_null,
1284         .recalc         = &followparent_recalc,
1285 };
1286
1287 static struct clk ocp_abe_iclk = {
1288         .name           = "ocp_abe_iclk",
1289         .parent         = &aess_fclk,
1290         .ops            = &clkops_null,
1291         .recalc         = &followparent_recalc,
1292 };
1293
1294 static struct clk per_abe_24m_fclk = {
1295         .name           = "per_abe_24m_fclk",
1296         .parent         = &dpll_abe_m2_ck,
1297         .ops            = &clkops_null,
1298         .recalc         = &followparent_recalc,
1299 };
1300
1301 static const struct clksel pmd_stm_clock_mux_sel[] = {
1302         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1303         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
1304         { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1305         { .parent = NULL },
1306 };
1307
1308 static struct clk pmd_stm_clock_mux_ck = {
1309         .name           = "pmd_stm_clock_mux_ck",
1310         .parent         = &sys_clkin_ck,
1311         .ops            = &clkops_null,
1312         .recalc         = &followparent_recalc,
1313 };
1314
1315 static struct clk pmd_trace_clk_mux_ck = {
1316         .name           = "pmd_trace_clk_mux_ck",
1317         .parent         = &sys_clkin_ck,
1318         .ops            = &clkops_null,
1319         .recalc         = &followparent_recalc,
1320 };
1321
1322 static const struct clksel syc_clk_div_div[] = {
1323         { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1324         { .parent = NULL },
1325 };
1326
1327 static struct clk syc_clk_div_ck = {
1328         .name           = "syc_clk_div_ck",
1329         .parent         = &sys_clkin_ck,
1330         .clksel         = syc_clk_div_div,
1331         .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1332         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1333         .ops            = &clkops_null,
1334         .recalc         = &omap2_clksel_recalc,
1335         .round_rate     = &omap2_clksel_round_rate,
1336         .set_rate       = &omap2_clksel_set_rate,
1337 };
1338
1339 /* Leaf clocks controlled by modules */
1340
1341 static struct clk aes1_fck = {
1342         .name           = "aes1_fck",
1343         .ops            = &clkops_omap2_dflt,
1344         .enable_reg     = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1345         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1346         .clkdm_name     = "l4_secure_clkdm",
1347         .parent         = &l3_div_ck,
1348         .recalc         = &followparent_recalc,
1349 };
1350
1351 static struct clk aes2_fck = {
1352         .name           = "aes2_fck",
1353         .ops            = &clkops_omap2_dflt,
1354         .enable_reg     = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1355         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1356         .clkdm_name     = "l4_secure_clkdm",
1357         .parent         = &l3_div_ck,
1358         .recalc         = &followparent_recalc,
1359 };
1360
1361 static struct clk aess_fck = {
1362         .name           = "aess_fck",
1363         .ops            = &clkops_omap2_dflt,
1364         .enable_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1365         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1366         .clkdm_name     = "abe_clkdm",
1367         .parent         = &aess_fclk,
1368         .recalc         = &followparent_recalc,
1369 };
1370
1371 static struct clk bandgap_fclk = {
1372         .name           = "bandgap_fclk",
1373         .ops            = &clkops_omap2_dflt,
1374         .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1375         .enable_bit     = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1376         .clkdm_name     = "l4_wkup_clkdm",
1377         .parent         = &sys_32k_ck,
1378         .recalc         = &followparent_recalc,
1379 };
1380
1381 static struct clk des3des_fck = {
1382         .name           = "des3des_fck",
1383         .ops            = &clkops_omap2_dflt,
1384         .enable_reg     = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1385         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1386         .clkdm_name     = "l4_secure_clkdm",
1387         .parent         = &l4_div_ck,
1388         .recalc         = &followparent_recalc,
1389 };
1390
1391 static const struct clksel dmic_sync_mux_sel[] = {
1392         { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1393         { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1394         { .parent = &func_24m_clk, .rates = div_1_2_rates },
1395         { .parent = NULL },
1396 };
1397
1398 static struct clk dmic_sync_mux_ck = {
1399         .name           = "dmic_sync_mux_ck",
1400         .parent         = &abe_24m_fclk,
1401         .clksel         = dmic_sync_mux_sel,
1402         .init           = &omap2_init_clksel_parent,
1403         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1404         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1405         .ops            = &clkops_null,
1406         .recalc         = &omap2_clksel_recalc,
1407 };
1408
1409 static const struct clksel func_dmic_abe_gfclk_sel[] = {
1410         { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1411         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1412         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1413         { .parent = NULL },
1414 };
1415
1416 /* Merged func_dmic_abe_gfclk into dmic */
1417 static struct clk dmic_fck = {
1418         .name           = "dmic_fck",
1419         .parent         = &dmic_sync_mux_ck,
1420         .clksel         = func_dmic_abe_gfclk_sel,
1421         .init           = &omap2_init_clksel_parent,
1422         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1423         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1424         .ops            = &clkops_omap2_dflt,
1425         .recalc         = &omap2_clksel_recalc,
1426         .enable_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1427         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1428         .clkdm_name     = "abe_clkdm",
1429 };
1430
1431 static struct clk dsp_fck = {
1432         .name           = "dsp_fck",
1433         .ops            = &clkops_omap2_dflt,
1434         .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1435         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1436         .clkdm_name     = "tesla_clkdm",
1437         .parent         = &dpll_iva_m4x2_ck,
1438         .recalc         = &followparent_recalc,
1439 };
1440
1441 static struct clk dss_sys_clk = {
1442         .name           = "dss_sys_clk",
1443         .ops            = &clkops_omap2_dflt,
1444         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1445         .enable_bit     = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1446         .clkdm_name     = "l3_dss_clkdm",
1447         .parent         = &syc_clk_div_ck,
1448         .recalc         = &followparent_recalc,
1449 };
1450
1451 static struct clk dss_tv_clk = {
1452         .name           = "dss_tv_clk",
1453         .ops            = &clkops_omap2_dflt,
1454         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1455         .enable_bit     = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1456         .clkdm_name     = "l3_dss_clkdm",
1457         .parent         = &extalt_clkin_ck,
1458         .recalc         = &followparent_recalc,
1459 };
1460
1461 static struct clk dss_dss_clk = {
1462         .name           = "dss_dss_clk",
1463         .ops            = &clkops_omap2_dflt,
1464         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1465         .enable_bit     = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1466         .clkdm_name     = "l3_dss_clkdm",
1467         .parent         = &dpll_per_m5x2_ck,
1468         .recalc         = &followparent_recalc,
1469 };
1470
1471 static struct clk dss_48mhz_clk = {
1472         .name           = "dss_48mhz_clk",
1473         .ops            = &clkops_omap2_dflt,
1474         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1475         .enable_bit     = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1476         .clkdm_name     = "l3_dss_clkdm",
1477         .parent         = &func_48mc_fclk,
1478         .recalc         = &followparent_recalc,
1479 };
1480
1481 static struct clk dss_fck = {
1482         .name           = "dss_fck",
1483         .ops            = &clkops_omap2_dflt,
1484         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1485         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1486         .clkdm_name     = "l3_dss_clkdm",
1487         .parent         = &l3_div_ck,
1488         .recalc         = &followparent_recalc,
1489 };
1490
1491 static struct clk efuse_ctrl_cust_fck = {
1492         .name           = "efuse_ctrl_cust_fck",
1493         .ops            = &clkops_omap2_dflt,
1494         .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1495         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1496         .clkdm_name     = "l4_cefuse_clkdm",
1497         .parent         = &sys_clkin_ck,
1498         .recalc         = &followparent_recalc,
1499 };
1500
1501 static struct clk emif1_fck = {
1502         .name           = "emif1_fck",
1503         .ops            = &clkops_omap2_dflt,
1504         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1505         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1506         .flags          = ENABLE_ON_INIT,
1507         .clkdm_name     = "l3_emif_clkdm",
1508         .parent         = &ddrphy_ck,
1509         .recalc         = &followparent_recalc,
1510 };
1511
1512 static struct clk emif2_fck = {
1513         .name           = "emif2_fck",
1514         .ops            = &clkops_omap2_dflt,
1515         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1516         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1517         .flags          = ENABLE_ON_INIT,
1518         .clkdm_name     = "l3_emif_clkdm",
1519         .parent         = &ddrphy_ck,
1520         .recalc         = &followparent_recalc,
1521 };
1522
1523 static const struct clksel fdif_fclk_div[] = {
1524         { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
1525         { .parent = NULL },
1526 };
1527
1528 /* Merged fdif_fclk into fdif */
1529 static struct clk fdif_fck = {
1530         .name           = "fdif_fck",
1531         .parent         = &dpll_per_m4x2_ck,
1532         .clksel         = fdif_fclk_div,
1533         .clksel_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1534         .clksel_mask    = OMAP4430_CLKSEL_FCLK_MASK,
1535         .ops            = &clkops_omap2_dflt,
1536         .recalc         = &omap2_clksel_recalc,
1537         .round_rate     = &omap2_clksel_round_rate,
1538         .set_rate       = &omap2_clksel_set_rate,
1539         .enable_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1540         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1541         .clkdm_name     = "iss_clkdm",
1542 };
1543
1544 static struct clk fpka_fck = {
1545         .name           = "fpka_fck",
1546         .ops            = &clkops_omap2_dflt,
1547         .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1548         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1549         .clkdm_name     = "l4_secure_clkdm",
1550         .parent         = &l4_div_ck,
1551         .recalc         = &followparent_recalc,
1552 };
1553
1554 static struct clk gpio1_dbclk = {
1555         .name           = "gpio1_dbclk",
1556         .ops            = &clkops_omap2_dflt,
1557         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1558         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1559         .clkdm_name     = "l4_wkup_clkdm",
1560         .parent         = &sys_32k_ck,
1561         .recalc         = &followparent_recalc,
1562 };
1563
1564 static struct clk gpio1_ick = {
1565         .name           = "gpio1_ick",
1566         .ops            = &clkops_omap2_dflt,
1567         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1568         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1569         .clkdm_name     = "l4_wkup_clkdm",
1570         .parent         = &l4_wkup_clk_mux_ck,
1571         .recalc         = &followparent_recalc,
1572 };
1573
1574 static struct clk gpio2_dbclk = {
1575         .name           = "gpio2_dbclk",
1576         .ops            = &clkops_omap2_dflt,
1577         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1578         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1579         .clkdm_name     = "l4_per_clkdm",
1580         .parent         = &sys_32k_ck,
1581         .recalc         = &followparent_recalc,
1582 };
1583
1584 static struct clk gpio2_ick = {
1585         .name           = "gpio2_ick",
1586         .ops            = &clkops_omap2_dflt,
1587         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1588         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1589         .clkdm_name     = "l4_per_clkdm",
1590         .parent         = &l4_div_ck,
1591         .recalc         = &followparent_recalc,
1592 };
1593
1594 static struct clk gpio3_dbclk = {
1595         .name           = "gpio3_dbclk",
1596         .ops            = &clkops_omap2_dflt,
1597         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1598         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1599         .clkdm_name     = "l4_per_clkdm",
1600         .parent         = &sys_32k_ck,
1601         .recalc         = &followparent_recalc,
1602 };
1603
1604 static struct clk gpio3_ick = {
1605         .name           = "gpio3_ick",
1606         .ops            = &clkops_omap2_dflt,
1607         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1608         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1609         .clkdm_name     = "l4_per_clkdm",
1610         .parent         = &l4_div_ck,
1611         .recalc         = &followparent_recalc,
1612 };
1613
1614 static struct clk gpio4_dbclk = {
1615         .name           = "gpio4_dbclk",
1616         .ops            = &clkops_omap2_dflt,
1617         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1618         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1619         .clkdm_name     = "l4_per_clkdm",
1620         .parent         = &sys_32k_ck,
1621         .recalc         = &followparent_recalc,
1622 };
1623
1624 static struct clk gpio4_ick = {
1625         .name           = "gpio4_ick",
1626         .ops            = &clkops_omap2_dflt,
1627         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1628         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1629         .clkdm_name     = "l4_per_clkdm",
1630         .parent         = &l4_div_ck,
1631         .recalc         = &followparent_recalc,
1632 };
1633
1634 static struct clk gpio5_dbclk = {
1635         .name           = "gpio5_dbclk",
1636         .ops            = &clkops_omap2_dflt,
1637         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1638         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1639         .clkdm_name     = "l4_per_clkdm",
1640         .parent         = &sys_32k_ck,
1641         .recalc         = &followparent_recalc,
1642 };
1643
1644 static struct clk gpio5_ick = {
1645         .name           = "gpio5_ick",
1646         .ops            = &clkops_omap2_dflt,
1647         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1648         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1649         .clkdm_name     = "l4_per_clkdm",
1650         .parent         = &l4_div_ck,
1651         .recalc         = &followparent_recalc,
1652 };
1653
1654 static struct clk gpio6_dbclk = {
1655         .name           = "gpio6_dbclk",
1656         .ops            = &clkops_omap2_dflt,
1657         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1658         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1659         .clkdm_name     = "l4_per_clkdm",
1660         .parent         = &sys_32k_ck,
1661         .recalc         = &followparent_recalc,
1662 };
1663
1664 static struct clk gpio6_ick = {
1665         .name           = "gpio6_ick",
1666         .ops            = &clkops_omap2_dflt,
1667         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1668         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1669         .clkdm_name     = "l4_per_clkdm",
1670         .parent         = &l4_div_ck,
1671         .recalc         = &followparent_recalc,
1672 };
1673
1674 static struct clk gpmc_ick = {
1675         .name           = "gpmc_ick",
1676         .ops            = &clkops_omap2_dflt,
1677         .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1678         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1679         .clkdm_name     = "l3_2_clkdm",
1680         .parent         = &l3_div_ck,
1681         .recalc         = &followparent_recalc,
1682 };
1683
1684 static const struct clksel sgx_clk_mux_sel[] = {
1685         { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
1686         { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
1687         { .parent = NULL },
1688 };
1689
1690 /* Merged sgx_clk_mux into gpu */
1691 static struct clk gpu_fck = {
1692         .name           = "gpu_fck",
1693         .parent         = &dpll_core_m7x2_ck,
1694         .clksel         = sgx_clk_mux_sel,
1695         .init           = &omap2_init_clksel_parent,
1696         .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1697         .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1698         .ops            = &clkops_omap2_dflt,
1699         .recalc         = &omap2_clksel_recalc,
1700         .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1701         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1702         .clkdm_name     = "l3_gfx_clkdm",
1703 };
1704
1705 static struct clk hdq1w_fck = {
1706         .name           = "hdq1w_fck",
1707         .ops            = &clkops_omap2_dflt,
1708         .enable_reg     = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1709         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1710         .clkdm_name     = "l4_per_clkdm",
1711         .parent         = &func_12m_fclk,
1712         .recalc         = &followparent_recalc,
1713 };
1714
1715 static const struct clksel hsi_fclk_div[] = {
1716         { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1717         { .parent = NULL },
1718 };
1719
1720 /* Merged hsi_fclk into hsi */
1721 static struct clk hsi_fck = {
1722         .name           = "hsi_fck",
1723         .parent         = &dpll_per_m2x2_ck,
1724         .clksel         = hsi_fclk_div,
1725         .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1726         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
1727         .ops            = &clkops_omap2_dflt,
1728         .recalc         = &omap2_clksel_recalc,
1729         .round_rate     = &omap2_clksel_round_rate,
1730         .set_rate       = &omap2_clksel_set_rate,
1731         .enable_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1732         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1733         .clkdm_name     = "l3_init_clkdm",
1734 };
1735
1736 static struct clk i2c1_fck = {
1737         .name           = "i2c1_fck",
1738         .ops            = &clkops_omap2_dflt,
1739         .enable_reg     = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1740         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1741         .clkdm_name     = "l4_per_clkdm",
1742         .parent         = &func_96m_fclk,
1743         .recalc         = &followparent_recalc,
1744 };
1745
1746 static struct clk i2c2_fck = {
1747         .name           = "i2c2_fck",
1748         .ops            = &clkops_omap2_dflt,
1749         .enable_reg     = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1750         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1751         .clkdm_name     = "l4_per_clkdm",
1752         .parent         = &func_96m_fclk,
1753         .recalc         = &followparent_recalc,
1754 };
1755
1756 static struct clk i2c3_fck = {
1757         .name           = "i2c3_fck",
1758         .ops            = &clkops_omap2_dflt,
1759         .enable_reg     = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1760         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1761         .clkdm_name     = "l4_per_clkdm",
1762         .parent         = &func_96m_fclk,
1763         .recalc         = &followparent_recalc,
1764 };
1765
1766 static struct clk i2c4_fck = {
1767         .name           = "i2c4_fck",
1768         .ops            = &clkops_omap2_dflt,
1769         .enable_reg     = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1770         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1771         .clkdm_name     = "l4_per_clkdm",
1772         .parent         = &func_96m_fclk,
1773         .recalc         = &followparent_recalc,
1774 };
1775
1776 static struct clk ipu_fck = {
1777         .name           = "ipu_fck",
1778         .ops            = &clkops_omap2_dflt,
1779         .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1780         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1781         .clkdm_name     = "ducati_clkdm",
1782         .parent         = &ducati_clk_mux_ck,
1783         .recalc         = &followparent_recalc,
1784 };
1785
1786 static struct clk iss_ctrlclk = {
1787         .name           = "iss_ctrlclk",
1788         .ops            = &clkops_omap2_dflt,
1789         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1790         .enable_bit     = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1791         .clkdm_name     = "iss_clkdm",
1792         .parent         = &func_96m_fclk,
1793         .recalc         = &followparent_recalc,
1794 };
1795
1796 static struct clk iss_fck = {
1797         .name           = "iss_fck",
1798         .ops            = &clkops_omap2_dflt,
1799         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1800         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1801         .clkdm_name     = "iss_clkdm",
1802         .parent         = &ducati_clk_mux_ck,
1803         .recalc         = &followparent_recalc,
1804 };
1805
1806 static struct clk iva_fck = {
1807         .name           = "iva_fck",
1808         .ops            = &clkops_omap2_dflt,
1809         .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1810         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1811         .clkdm_name     = "ivahd_clkdm",
1812         .parent         = &dpll_iva_m5x2_ck,
1813         .recalc         = &followparent_recalc,
1814 };
1815
1816 static struct clk kbd_fck = {
1817         .name           = "kbd_fck",
1818         .ops            = &clkops_omap2_dflt,
1819         .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1820         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1821         .clkdm_name     = "l4_wkup_clkdm",
1822         .parent         = &sys_32k_ck,
1823         .recalc         = &followparent_recalc,
1824 };
1825
1826 static struct clk l3_instr_ick = {
1827         .name           = "l3_instr_ick",
1828         .ops            = &clkops_omap2_dflt,
1829         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1830         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1831         .clkdm_name     = "l3_instr_clkdm",
1832         .flags          = ENABLE_ON_INIT,
1833         .parent         = &l3_div_ck,
1834         .recalc         = &followparent_recalc,
1835 };
1836
1837 static struct clk l3_main_3_ick = {
1838         .name           = "l3_main_3_ick",
1839         .ops            = &clkops_omap2_dflt,
1840         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1841         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1842         .clkdm_name     = "l3_instr_clkdm",
1843         .flags          = ENABLE_ON_INIT,
1844         .parent         = &l3_div_ck,
1845         .recalc         = &followparent_recalc,
1846 };
1847
1848 static struct clk mcasp_sync_mux_ck = {
1849         .name           = "mcasp_sync_mux_ck",
1850         .parent         = &abe_24m_fclk,
1851         .clksel         = dmic_sync_mux_sel,
1852         .init           = &omap2_init_clksel_parent,
1853         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1854         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1855         .ops            = &clkops_null,
1856         .recalc         = &omap2_clksel_recalc,
1857 };
1858
1859 static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1860         { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1861         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1862         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1863         { .parent = NULL },
1864 };
1865
1866 /* Merged func_mcasp_abe_gfclk into mcasp */
1867 static struct clk mcasp_fck = {
1868         .name           = "mcasp_fck",
1869         .parent         = &mcasp_sync_mux_ck,
1870         .clksel         = func_mcasp_abe_gfclk_sel,
1871         .init           = &omap2_init_clksel_parent,
1872         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1873         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1874         .ops            = &clkops_omap2_dflt,
1875         .recalc         = &omap2_clksel_recalc,
1876         .enable_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1877         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1878         .clkdm_name     = "abe_clkdm",
1879 };
1880
1881 static struct clk mcbsp1_sync_mux_ck = {
1882         .name           = "mcbsp1_sync_mux_ck",
1883         .parent         = &abe_24m_fclk,
1884         .clksel         = dmic_sync_mux_sel,
1885         .init           = &omap2_init_clksel_parent,
1886         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1887         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1888         .ops            = &clkops_null,
1889         .recalc         = &omap2_clksel_recalc,
1890 };
1891
1892 static const struct clksel func_mcbsp1_gfclk_sel[] = {
1893         { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1894         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1895         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1896         { .parent = NULL },
1897 };
1898
1899 /* Merged func_mcbsp1_gfclk into mcbsp1 */
1900 static struct clk mcbsp1_fck = {
1901         .name           = "mcbsp1_fck",
1902         .parent         = &mcbsp1_sync_mux_ck,
1903         .clksel         = func_mcbsp1_gfclk_sel,
1904         .init           = &omap2_init_clksel_parent,
1905         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1906         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1907         .ops            = &clkops_omap2_dflt,
1908         .recalc         = &omap2_clksel_recalc,
1909         .enable_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1910         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1911         .clkdm_name     = "abe_clkdm",
1912 };
1913
1914 static struct clk mcbsp2_sync_mux_ck = {
1915         .name           = "mcbsp2_sync_mux_ck",
1916         .parent         = &abe_24m_fclk,
1917         .clksel         = dmic_sync_mux_sel,
1918         .init           = &omap2_init_clksel_parent,
1919         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1920         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1921         .ops            = &clkops_null,
1922         .recalc         = &omap2_clksel_recalc,
1923 };
1924
1925 static const struct clksel func_mcbsp2_gfclk_sel[] = {
1926         { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1927         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1928         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1929         { .parent = NULL },
1930 };
1931
1932 /* Merged func_mcbsp2_gfclk into mcbsp2 */
1933 static struct clk mcbsp2_fck = {
1934         .name           = "mcbsp2_fck",
1935         .parent         = &mcbsp2_sync_mux_ck,
1936         .clksel         = func_mcbsp2_gfclk_sel,
1937         .init           = &omap2_init_clksel_parent,
1938         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1939         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1940         .ops            = &clkops_omap2_dflt,
1941         .recalc         = &omap2_clksel_recalc,
1942         .enable_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1943         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1944         .clkdm_name     = "abe_clkdm",
1945 };
1946
1947 static struct clk mcbsp3_sync_mux_ck = {
1948         .name           = "mcbsp3_sync_mux_ck",
1949         .parent         = &abe_24m_fclk,
1950         .clksel         = dmic_sync_mux_sel,
1951         .init           = &omap2_init_clksel_parent,
1952         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1953         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1954         .ops            = &clkops_null,
1955         .recalc         = &omap2_clksel_recalc,
1956 };
1957
1958 static const struct clksel func_mcbsp3_gfclk_sel[] = {
1959         { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1960         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1961         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1962         { .parent = NULL },
1963 };
1964
1965 /* Merged func_mcbsp3_gfclk into mcbsp3 */
1966 static struct clk mcbsp3_fck = {
1967         .name           = "mcbsp3_fck",
1968         .parent         = &mcbsp3_sync_mux_ck,
1969         .clksel         = func_mcbsp3_gfclk_sel,
1970         .init           = &omap2_init_clksel_parent,
1971         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1972         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1973         .ops            = &clkops_omap2_dflt,
1974         .recalc         = &omap2_clksel_recalc,
1975         .enable_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1976         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1977         .clkdm_name     = "abe_clkdm",
1978 };
1979
1980 static struct clk mcbsp4_sync_mux_ck = {
1981         .name           = "mcbsp4_sync_mux_ck",
1982         .parent         = &func_96m_fclk,
1983         .clksel         = mcasp2_fclk_sel,
1984         .init           = &omap2_init_clksel_parent,
1985         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1986         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1987         .ops            = &clkops_null,
1988         .recalc         = &omap2_clksel_recalc,
1989 };
1990
1991 static const struct clksel per_mcbsp4_gfclk_sel[] = {
1992         { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1993         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1994         { .parent = NULL },
1995 };
1996
1997 /* Merged per_mcbsp4_gfclk into mcbsp4 */
1998 static struct clk mcbsp4_fck = {
1999         .name           = "mcbsp4_fck",
2000         .parent         = &mcbsp4_sync_mux_ck,
2001         .clksel         = per_mcbsp4_gfclk_sel,
2002         .init           = &omap2_init_clksel_parent,
2003         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2004         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
2005         .ops            = &clkops_omap2_dflt,
2006         .recalc         = &omap2_clksel_recalc,
2007         .enable_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2008         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2009         .clkdm_name     = "l4_per_clkdm",
2010 };
2011
2012 static struct clk mcpdm_fck = {
2013         .name           = "mcpdm_fck",
2014         .ops            = &clkops_omap2_dflt,
2015         .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
2016         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2017         .clkdm_name     = "abe_clkdm",
2018         .parent         = &pad_clks_ck,
2019         .recalc         = &followparent_recalc,
2020 };
2021
2022 static struct clk mcspi1_fck = {
2023         .name           = "mcspi1_fck",
2024         .ops            = &clkops_omap2_dflt,
2025         .enable_reg     = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
2026         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2027         .clkdm_name     = "l4_per_clkdm",
2028         .parent         = &func_48m_fclk,
2029         .recalc         = &followparent_recalc,
2030 };
2031
2032 static struct clk mcspi2_fck = {
2033         .name           = "mcspi2_fck",
2034         .ops            = &clkops_omap2_dflt,
2035         .enable_reg     = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2036         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2037         .clkdm_name     = "l4_per_clkdm",
2038         .parent         = &func_48m_fclk,
2039         .recalc         = &followparent_recalc,
2040 };
2041
2042 static struct clk mcspi3_fck = {
2043         .name           = "mcspi3_fck",
2044         .ops            = &clkops_omap2_dflt,
2045         .enable_reg     = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2046         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2047         .clkdm_name     = "l4_per_clkdm",
2048         .parent         = &func_48m_fclk,
2049         .recalc         = &followparent_recalc,
2050 };
2051
2052 static struct clk mcspi4_fck = {
2053         .name           = "mcspi4_fck",
2054         .ops            = &clkops_omap2_dflt,
2055         .enable_reg     = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2056         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2057         .clkdm_name     = "l4_per_clkdm",
2058         .parent         = &func_48m_fclk,
2059         .recalc         = &followparent_recalc,
2060 };
2061
2062 /* Merged hsmmc1_fclk into mmc1 */
2063 static struct clk mmc1_fck = {
2064         .name           = "mmc1_fck",
2065         .parent         = &func_64m_fclk,
2066         .clksel         = hsmmc6_fclk_sel,
2067         .init           = &omap2_init_clksel_parent,
2068         .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2069         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2070         .ops            = &clkops_omap2_dflt,
2071         .recalc         = &omap2_clksel_recalc,
2072         .enable_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2073         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2074         .clkdm_name     = "l3_init_clkdm",
2075 };
2076
2077 /* Merged hsmmc2_fclk into mmc2 */
2078 static struct clk mmc2_fck = {
2079         .name           = "mmc2_fck",
2080         .parent         = &func_64m_fclk,
2081         .clksel         = hsmmc6_fclk_sel,
2082         .init           = &omap2_init_clksel_parent,
2083         .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2084         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2085         .ops            = &clkops_omap2_dflt,
2086         .recalc         = &omap2_clksel_recalc,
2087         .enable_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2088         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2089         .clkdm_name     = "l3_init_clkdm",
2090 };
2091
2092 static struct clk mmc3_fck = {
2093         .name           = "mmc3_fck",
2094         .ops            = &clkops_omap2_dflt,
2095         .enable_reg     = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2096         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2097         .clkdm_name     = "l4_per_clkdm",
2098         .parent         = &func_48m_fclk,
2099         .recalc         = &followparent_recalc,
2100 };
2101
2102 static struct clk mmc4_fck = {
2103         .name           = "mmc4_fck",
2104         .ops            = &clkops_omap2_dflt,
2105         .enable_reg     = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2106         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2107         .clkdm_name     = "l4_per_clkdm",
2108         .parent         = &func_48m_fclk,
2109         .recalc         = &followparent_recalc,
2110 };
2111
2112 static struct clk mmc5_fck = {
2113         .name           = "mmc5_fck",
2114         .ops            = &clkops_omap2_dflt,
2115         .enable_reg     = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2116         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2117         .clkdm_name     = "l4_per_clkdm",
2118         .parent         = &func_48m_fclk,
2119         .recalc         = &followparent_recalc,
2120 };
2121
2122 static struct clk ocp2scp_usb_phy_phy_48m = {
2123         .name           = "ocp2scp_usb_phy_phy_48m",
2124         .ops            = &clkops_omap2_dflt,
2125         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2126         .enable_bit     = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2127         .clkdm_name     = "l3_init_clkdm",
2128         .parent         = &func_48m_fclk,
2129         .recalc         = &followparent_recalc,
2130 };
2131
2132 static struct clk ocp2scp_usb_phy_ick = {
2133         .name           = "ocp2scp_usb_phy_ick",
2134         .ops            = &clkops_omap2_dflt,
2135         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2136         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2137         .clkdm_name     = "l3_init_clkdm",
2138         .parent         = &l4_div_ck,
2139         .recalc         = &followparent_recalc,
2140 };
2141
2142 static struct clk ocp_wp_noc_ick = {
2143         .name           = "ocp_wp_noc_ick",
2144         .ops            = &clkops_omap2_dflt,
2145         .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2146         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2147         .clkdm_name     = "l3_instr_clkdm",
2148         .flags          = ENABLE_ON_INIT,
2149         .parent         = &l3_div_ck,
2150         .recalc         = &followparent_recalc,
2151 };
2152
2153 static struct clk rng_ick = {
2154         .name           = "rng_ick",
2155         .ops            = &clkops_omap2_dflt,
2156         .enable_reg     = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2157         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2158         .clkdm_name     = "l4_secure_clkdm",
2159         .parent         = &l4_div_ck,
2160         .recalc         = &followparent_recalc,
2161 };
2162
2163 static struct clk sha2md5_fck = {
2164         .name           = "sha2md5_fck",
2165         .ops            = &clkops_omap2_dflt,
2166         .enable_reg     = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2167         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2168         .clkdm_name     = "l4_secure_clkdm",
2169         .parent         = &l3_div_ck,
2170         .recalc         = &followparent_recalc,
2171 };
2172
2173 static struct clk sl2if_ick = {
2174         .name           = "sl2if_ick",
2175         .ops            = &clkops_omap2_dflt,
2176         .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2177         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2178         .clkdm_name     = "ivahd_clkdm",
2179         .parent         = &dpll_iva_m5x2_ck,
2180         .recalc         = &followparent_recalc,
2181 };
2182
2183 static struct clk slimbus1_fclk_1 = {
2184         .name           = "slimbus1_fclk_1",
2185         .ops            = &clkops_omap2_dflt,
2186         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2187         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2188         .clkdm_name     = "abe_clkdm",
2189         .parent         = &func_24m_clk,
2190         .recalc         = &followparent_recalc,
2191 };
2192
2193 static struct clk slimbus1_fclk_0 = {
2194         .name           = "slimbus1_fclk_0",
2195         .ops            = &clkops_omap2_dflt,
2196         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2197         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2198         .clkdm_name     = "abe_clkdm",
2199         .parent         = &abe_24m_fclk,
2200         .recalc         = &followparent_recalc,
2201 };
2202
2203 static struct clk slimbus1_fclk_2 = {
2204         .name           = "slimbus1_fclk_2",
2205         .ops            = &clkops_omap2_dflt,
2206         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2207         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2208         .clkdm_name     = "abe_clkdm",
2209         .parent         = &pad_clks_ck,
2210         .recalc         = &followparent_recalc,
2211 };
2212
2213 static struct clk slimbus1_slimbus_clk = {
2214         .name           = "slimbus1_slimbus_clk",
2215         .ops            = &clkops_omap2_dflt,
2216         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2217         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2218         .clkdm_name     = "abe_clkdm",
2219         .parent         = &slimbus_clk,
2220         .recalc         = &followparent_recalc,
2221 };
2222
2223 static struct clk slimbus1_fck = {
2224         .name           = "slimbus1_fck",
2225         .ops            = &clkops_omap2_dflt,
2226         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2227         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2228         .clkdm_name     = "abe_clkdm",
2229         .parent         = &ocp_abe_iclk,
2230         .recalc         = &followparent_recalc,
2231 };
2232
2233 static struct clk slimbus2_fclk_1 = {
2234         .name           = "slimbus2_fclk_1",
2235         .ops            = &clkops_omap2_dflt,
2236         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2237         .enable_bit     = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2238         .clkdm_name     = "l4_per_clkdm",
2239         .parent         = &per_abe_24m_fclk,
2240         .recalc         = &followparent_recalc,
2241 };
2242
2243 static struct clk slimbus2_fclk_0 = {
2244         .name           = "slimbus2_fclk_0",
2245         .ops            = &clkops_omap2_dflt,
2246         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2247         .enable_bit     = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2248         .clkdm_name     = "l4_per_clkdm",
2249         .parent         = &func_24mc_fclk,
2250         .recalc         = &followparent_recalc,
2251 };
2252
2253 static struct clk slimbus2_slimbus_clk = {
2254         .name           = "slimbus2_slimbus_clk",
2255         .ops            = &clkops_omap2_dflt,
2256         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2257         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2258         .clkdm_name     = "l4_per_clkdm",
2259         .parent         = &pad_slimbus_core_clks_ck,
2260         .recalc         = &followparent_recalc,
2261 };
2262
2263 static struct clk slimbus2_fck = {
2264         .name           = "slimbus2_fck",
2265         .ops            = &clkops_omap2_dflt,
2266         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2267         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2268         .clkdm_name     = "l4_per_clkdm",
2269         .parent         = &l4_div_ck,
2270         .recalc         = &followparent_recalc,
2271 };
2272
2273 static struct clk smartreflex_core_fck = {
2274         .name           = "smartreflex_core_fck",
2275         .ops            = &clkops_omap2_dflt,
2276         .enable_reg     = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2277         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2278         .clkdm_name     = "l4_ao_clkdm",
2279         .parent         = &l4_wkup_clk_mux_ck,
2280         .recalc         = &followparent_recalc,
2281 };
2282
2283 static struct clk smartreflex_iva_fck = {
2284         .name           = "smartreflex_iva_fck",
2285         .ops            = &clkops_omap2_dflt,
2286         .enable_reg     = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2287         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2288         .clkdm_name     = "l4_ao_clkdm",
2289         .parent         = &l4_wkup_clk_mux_ck,
2290         .recalc         = &followparent_recalc,
2291 };
2292
2293 static struct clk smartreflex_mpu_fck = {
2294         .name           = "smartreflex_mpu_fck",
2295         .ops            = &clkops_omap2_dflt,
2296         .enable_reg     = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2297         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2298         .clkdm_name     = "l4_ao_clkdm",
2299         .parent         = &l4_wkup_clk_mux_ck,
2300         .recalc         = &followparent_recalc,
2301 };
2302
2303 /* Merged dmt1_clk_mux into timer1 */
2304 static struct clk timer1_fck = {
2305         .name           = "timer1_fck",
2306         .parent         = &sys_clkin_ck,
2307         .clksel         = abe_dpll_bypass_clk_mux_sel,
2308         .init           = &omap2_init_clksel_parent,
2309         .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2310         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2311         .ops            = &clkops_omap2_dflt,
2312         .recalc         = &omap2_clksel_recalc,
2313         .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2314         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2315         .clkdm_name     = "l4_wkup_clkdm",
2316 };
2317
2318 /* Merged cm2_dm10_mux into timer10 */
2319 static struct clk timer10_fck = {
2320         .name           = "timer10_fck",
2321         .parent         = &sys_clkin_ck,
2322         .clksel         = abe_dpll_bypass_clk_mux_sel,
2323         .init           = &omap2_init_clksel_parent,
2324         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2325         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2326         .ops            = &clkops_omap2_dflt,
2327         .recalc         = &omap2_clksel_recalc,
2328         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2329         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2330         .clkdm_name     = "l4_per_clkdm",
2331 };
2332
2333 /* Merged cm2_dm11_mux into timer11 */
2334 static struct clk timer11_fck = {
2335         .name           = "timer11_fck",
2336         .parent         = &sys_clkin_ck,
2337         .clksel         = abe_dpll_bypass_clk_mux_sel,
2338         .init           = &omap2_init_clksel_parent,
2339         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2340         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2341         .ops            = &clkops_omap2_dflt,
2342         .recalc         = &omap2_clksel_recalc,
2343         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2344         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2345         .clkdm_name     = "l4_per_clkdm",
2346 };
2347
2348 /* Merged cm2_dm2_mux into timer2 */
2349 static struct clk timer2_fck = {
2350         .name           = "timer2_fck",
2351         .parent         = &sys_clkin_ck,
2352         .clksel         = abe_dpll_bypass_clk_mux_sel,
2353         .init           = &omap2_init_clksel_parent,
2354         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2355         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2356         .ops            = &clkops_omap2_dflt,
2357         .recalc         = &omap2_clksel_recalc,
2358         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2359         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2360         .clkdm_name     = "l4_per_clkdm",
2361 };
2362
2363 /* Merged cm2_dm3_mux into timer3 */
2364 static struct clk timer3_fck = {
2365         .name           = "timer3_fck",
2366         .parent         = &sys_clkin_ck,
2367         .clksel         = abe_dpll_bypass_clk_mux_sel,
2368         .init           = &omap2_init_clksel_parent,
2369         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2370         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2371         .ops            = &clkops_omap2_dflt,
2372         .recalc         = &omap2_clksel_recalc,
2373         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2374         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2375         .clkdm_name     = "l4_per_clkdm",
2376 };
2377
2378 /* Merged cm2_dm4_mux into timer4 */
2379 static struct clk timer4_fck = {
2380         .name           = "timer4_fck",
2381         .parent         = &sys_clkin_ck,
2382         .clksel         = abe_dpll_bypass_clk_mux_sel,
2383         .init           = &omap2_init_clksel_parent,
2384         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2385         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2386         .ops            = &clkops_omap2_dflt,
2387         .recalc         = &omap2_clksel_recalc,
2388         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2389         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2390         .clkdm_name     = "l4_per_clkdm",
2391 };
2392
2393 static const struct clksel timer5_sync_mux_sel[] = {
2394         { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2395         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2396         { .parent = NULL },
2397 };
2398
2399 /* Merged timer5_sync_mux into timer5 */
2400 static struct clk timer5_fck = {
2401         .name           = "timer5_fck",
2402         .parent         = &syc_clk_div_ck,
2403         .clksel         = timer5_sync_mux_sel,
2404         .init           = &omap2_init_clksel_parent,
2405         .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2406         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2407         .ops            = &clkops_omap2_dflt,
2408         .recalc         = &omap2_clksel_recalc,
2409         .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2410         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2411         .clkdm_name     = "abe_clkdm",
2412 };
2413
2414 /* Merged timer6_sync_mux into timer6 */
2415 static struct clk timer6_fck = {
2416         .name           = "timer6_fck",
2417         .parent         = &syc_clk_div_ck,
2418         .clksel         = timer5_sync_mux_sel,
2419         .init           = &omap2_init_clksel_parent,
2420         .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2421         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2422         .ops            = &clkops_omap2_dflt,
2423         .recalc         = &omap2_clksel_recalc,
2424         .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2425         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2426         .clkdm_name     = "abe_clkdm",
2427 };
2428
2429 /* Merged timer7_sync_mux into timer7 */
2430 static struct clk timer7_fck = {
2431         .name           = "timer7_fck",
2432         .parent         = &syc_clk_div_ck,
2433         .clksel         = timer5_sync_mux_sel,
2434         .init           = &omap2_init_clksel_parent,
2435         .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2436         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2437         .ops            = &clkops_omap2_dflt,
2438         .recalc         = &omap2_clksel_recalc,
2439         .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2440         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2441         .clkdm_name     = "abe_clkdm",
2442 };
2443
2444 /* Merged timer8_sync_mux into timer8 */
2445 static struct clk timer8_fck = {
2446         .name           = "timer8_fck",
2447         .parent         = &syc_clk_div_ck,
2448         .clksel         = timer5_sync_mux_sel,
2449         .init           = &omap2_init_clksel_parent,
2450         .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2451         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2452         .ops            = &clkops_omap2_dflt,
2453         .recalc         = &omap2_clksel_recalc,
2454         .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2455         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2456         .clkdm_name     = "abe_clkdm",
2457 };
2458
2459 /* Merged cm2_dm9_mux into timer9 */
2460 static struct clk timer9_fck = {
2461         .name           = "timer9_fck",
2462         .parent         = &sys_clkin_ck,
2463         .clksel         = abe_dpll_bypass_clk_mux_sel,
2464         .init           = &omap2_init_clksel_parent,
2465         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2466         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2467         .ops            = &clkops_omap2_dflt,
2468         .recalc         = &omap2_clksel_recalc,
2469         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2470         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2471         .clkdm_name     = "l4_per_clkdm",
2472 };
2473
2474 static struct clk uart1_fck = {
2475         .name           = "uart1_fck",
2476         .ops            = &clkops_omap2_dflt,
2477         .enable_reg     = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2478         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2479         .clkdm_name     = "l4_per_clkdm",
2480         .parent         = &func_48m_fclk,
2481         .recalc         = &followparent_recalc,
2482 };
2483
2484 static struct clk uart2_fck = {
2485         .name           = "uart2_fck",
2486         .ops            = &clkops_omap2_dflt,
2487         .enable_reg     = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2488         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2489         .clkdm_name     = "l4_per_clkdm",
2490         .parent         = &func_48m_fclk,
2491         .recalc         = &followparent_recalc,
2492 };
2493
2494 static struct clk uart3_fck = {
2495         .name           = "uart3_fck",
2496         .ops            = &clkops_omap2_dflt,
2497         .enable_reg     = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2498         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2499         .clkdm_name     = "l4_per_clkdm",
2500         .parent         = &func_48m_fclk,
2501         .recalc         = &followparent_recalc,
2502 };
2503
2504 static struct clk uart4_fck = {
2505         .name           = "uart4_fck",
2506         .ops            = &clkops_omap2_dflt,
2507         .enable_reg     = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2508         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2509         .clkdm_name     = "l4_per_clkdm",
2510         .parent         = &func_48m_fclk,
2511         .recalc         = &followparent_recalc,
2512 };
2513
2514 static struct clk usb_host_fs_fck = {
2515         .name           = "usb_host_fs_fck",
2516         .ops            = &clkops_omap2_dflt,
2517         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2518         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2519         .clkdm_name     = "l3_init_clkdm",
2520         .parent         = &func_48mc_fclk,
2521         .recalc         = &followparent_recalc,
2522 };
2523
2524 static const struct clksel utmi_p1_gfclk_sel[] = {
2525         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2526         { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2527         { .parent = NULL },
2528 };
2529
2530 static struct clk utmi_p1_gfclk = {
2531         .name           = "utmi_p1_gfclk",
2532         .parent         = &init_60m_fclk,
2533         .clksel         = utmi_p1_gfclk_sel,
2534         .init           = &omap2_init_clksel_parent,
2535         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2536         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
2537         .ops            = &clkops_null,
2538         .recalc         = &omap2_clksel_recalc,
2539 };
2540
2541 static struct clk usb_host_hs_utmi_p1_clk = {
2542         .name           = "usb_host_hs_utmi_p1_clk",
2543         .ops            = &clkops_omap2_dflt,
2544         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2545         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2546         .clkdm_name     = "l3_init_clkdm",
2547         .parent         = &utmi_p1_gfclk,
2548         .recalc         = &followparent_recalc,
2549 };
2550
2551 static const struct clksel utmi_p2_gfclk_sel[] = {
2552         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2553         { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2554         { .parent = NULL },
2555 };
2556
2557 static struct clk utmi_p2_gfclk = {
2558         .name           = "utmi_p2_gfclk",
2559         .parent         = &init_60m_fclk,
2560         .clksel         = utmi_p2_gfclk_sel,
2561         .init           = &omap2_init_clksel_parent,
2562         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2563         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
2564         .ops            = &clkops_null,
2565         .recalc         = &omap2_clksel_recalc,
2566 };
2567
2568 static struct clk usb_host_hs_utmi_p2_clk = {
2569         .name           = "usb_host_hs_utmi_p2_clk",
2570         .ops            = &clkops_omap2_dflt,
2571         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2572         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2573         .clkdm_name     = "l3_init_clkdm",
2574         .parent         = &utmi_p2_gfclk,
2575         .recalc         = &followparent_recalc,
2576 };
2577
2578 static struct clk usb_host_hs_utmi_p3_clk = {
2579         .name           = "usb_host_hs_utmi_p3_clk",
2580         .ops            = &clkops_omap2_dflt,
2581         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2582         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2583         .clkdm_name     = "l3_init_clkdm",
2584         .parent         = &init_60m_fclk,
2585         .recalc         = &followparent_recalc,
2586 };
2587
2588 static struct clk usb_host_hs_hsic480m_p1_clk = {
2589         .name           = "usb_host_hs_hsic480m_p1_clk",
2590         .ops            = &clkops_omap2_dflt,
2591         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2592         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2593         .clkdm_name     = "l3_init_clkdm",
2594         .parent         = &dpll_usb_m2_ck,
2595         .recalc         = &followparent_recalc,
2596 };
2597
2598 static struct clk usb_host_hs_hsic60m_p1_clk = {
2599         .name           = "usb_host_hs_hsic60m_p1_clk",
2600         .ops            = &clkops_omap2_dflt,
2601         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2602         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2603         .clkdm_name     = "l3_init_clkdm",
2604         .parent         = &init_60m_fclk,
2605         .recalc         = &followparent_recalc,
2606 };
2607
2608 static struct clk usb_host_hs_hsic60m_p2_clk = {
2609         .name           = "usb_host_hs_hsic60m_p2_clk",
2610         .ops            = &clkops_omap2_dflt,
2611         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2612         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2613         .clkdm_name     = "l3_init_clkdm",
2614         .parent         = &init_60m_fclk,
2615         .recalc         = &followparent_recalc,
2616 };
2617
2618 static struct clk usb_host_hs_hsic480m_p2_clk = {
2619         .name           = "usb_host_hs_hsic480m_p2_clk",
2620         .ops            = &clkops_omap2_dflt,
2621         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2622         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2623         .clkdm_name     = "l3_init_clkdm",
2624         .parent         = &dpll_usb_m2_ck,
2625         .recalc         = &followparent_recalc,
2626 };
2627
2628 static struct clk usb_host_hs_func48mclk = {
2629         .name           = "usb_host_hs_func48mclk",
2630         .ops            = &clkops_omap2_dflt,
2631         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2632         .enable_bit     = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2633         .clkdm_name     = "l3_init_clkdm",
2634         .parent         = &func_48mc_fclk,
2635         .recalc         = &followparent_recalc,
2636 };
2637
2638 static struct clk usb_host_hs_fck = {
2639         .name           = "usb_host_hs_fck",
2640         .ops            = &clkops_omap2_dflt,
2641         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2642         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2643         .clkdm_name     = "l3_init_clkdm",
2644         .parent         = &init_60m_fclk,
2645         .recalc         = &followparent_recalc,
2646 };
2647
2648 static const struct clksel otg_60m_gfclk_sel[] = {
2649         { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2650         { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2651         { .parent = NULL },
2652 };
2653
2654 static struct clk otg_60m_gfclk = {
2655         .name           = "otg_60m_gfclk",
2656         .parent         = &utmi_phy_clkout_ck,
2657         .clksel         = otg_60m_gfclk_sel,
2658         .init           = &omap2_init_clksel_parent,
2659         .clksel_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2660         .clksel_mask    = OMAP4430_CLKSEL_60M_MASK,
2661         .ops            = &clkops_null,
2662         .recalc         = &omap2_clksel_recalc,
2663 };
2664
2665 static struct clk usb_otg_hs_xclk = {
2666         .name           = "usb_otg_hs_xclk",
2667         .ops            = &clkops_omap2_dflt,
2668         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2669         .enable_bit     = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2670         .clkdm_name     = "l3_init_clkdm",
2671         .parent         = &otg_60m_gfclk,
2672         .recalc         = &followparent_recalc,
2673 };
2674
2675 static struct clk usb_otg_hs_ick = {
2676         .name           = "usb_otg_hs_ick",
2677         .ops            = &clkops_omap2_dflt,
2678         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2679         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2680         .clkdm_name     = "l3_init_clkdm",
2681         .parent         = &l3_div_ck,
2682         .recalc         = &followparent_recalc,
2683 };
2684
2685 static struct clk usb_phy_cm_clk32k = {
2686         .name           = "usb_phy_cm_clk32k",
2687         .ops            = &clkops_omap2_dflt,
2688         .enable_reg     = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2689         .enable_bit     = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2690         .clkdm_name     = "l4_ao_clkdm",
2691         .parent         = &sys_32k_ck,
2692         .recalc         = &followparent_recalc,
2693 };
2694
2695 static struct clk usb_tll_hs_usb_ch2_clk = {
2696         .name           = "usb_tll_hs_usb_ch2_clk",
2697         .ops            = &clkops_omap2_dflt,
2698         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2699         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2700         .clkdm_name     = "l3_init_clkdm",
2701         .parent         = &init_60m_fclk,
2702         .recalc         = &followparent_recalc,
2703 };
2704
2705 static struct clk usb_tll_hs_usb_ch0_clk = {
2706         .name           = "usb_tll_hs_usb_ch0_clk",
2707         .ops            = &clkops_omap2_dflt,
2708         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2709         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2710         .clkdm_name     = "l3_init_clkdm",
2711         .parent         = &init_60m_fclk,
2712         .recalc         = &followparent_recalc,
2713 };
2714
2715 static struct clk usb_tll_hs_usb_ch1_clk = {
2716         .name           = "usb_tll_hs_usb_ch1_clk",
2717         .ops            = &clkops_omap2_dflt,
2718         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2719         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2720         .clkdm_name     = "l3_init_clkdm",
2721         .parent         = &init_60m_fclk,
2722         .recalc         = &followparent_recalc,
2723 };
2724
2725 static struct clk usb_tll_hs_ick = {
2726         .name           = "usb_tll_hs_ick",
2727         .ops            = &clkops_omap2_dflt,
2728         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2729         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2730         .clkdm_name     = "l3_init_clkdm",
2731         .parent         = &l4_div_ck,
2732         .recalc         = &followparent_recalc,
2733 };
2734
2735 static const struct clksel_rate div2_14to18_rates[] = {
2736         { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2737         { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2738         { .div = 0 },
2739 };
2740
2741 static const struct clksel usim_fclk_div[] = {
2742         { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
2743         { .parent = NULL },
2744 };
2745
2746 static struct clk usim_ck = {
2747         .name           = "usim_ck",
2748         .parent         = &dpll_per_m4x2_ck,
2749         .clksel         = usim_fclk_div,
2750         .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2751         .clksel_mask    = OMAP4430_CLKSEL_DIV_MASK,
2752         .ops            = &clkops_null,
2753         .recalc         = &omap2_clksel_recalc,
2754         .round_rate     = &omap2_clksel_round_rate,
2755         .set_rate       = &omap2_clksel_set_rate,
2756 };
2757
2758 static struct clk usim_fclk = {
2759         .name           = "usim_fclk",
2760         .ops            = &clkops_omap2_dflt,
2761         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2762         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2763         .clkdm_name     = "l4_wkup_clkdm",
2764         .parent         = &usim_ck,
2765         .recalc         = &followparent_recalc,
2766 };
2767
2768 static struct clk usim_fck = {
2769         .name           = "usim_fck",
2770         .ops            = &clkops_omap2_dflt,
2771         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2772         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2773         .clkdm_name     = "l4_wkup_clkdm",
2774         .parent         = &sys_32k_ck,
2775         .recalc         = &followparent_recalc,
2776 };
2777
2778 static struct clk wd_timer2_fck = {
2779         .name           = "wd_timer2_fck",
2780         .ops            = &clkops_omap2_dflt,
2781         .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2782         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2783         .clkdm_name     = "l4_wkup_clkdm",
2784         .parent         = &sys_32k_ck,
2785         .recalc         = &followparent_recalc,
2786 };
2787
2788 static struct clk wd_timer3_fck = {
2789         .name           = "wd_timer3_fck",
2790         .ops            = &clkops_omap2_dflt,
2791         .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2792         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2793         .clkdm_name     = "abe_clkdm",
2794         .parent         = &sys_32k_ck,
2795         .recalc         = &followparent_recalc,
2796 };
2797
2798 /* Remaining optional clocks */
2799 static const struct clksel stm_clk_div_div[] = {
2800         { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2801         { .parent = NULL },
2802 };
2803
2804 static struct clk stm_clk_div_ck = {
2805         .name           = "stm_clk_div_ck",
2806         .parent         = &pmd_stm_clock_mux_ck,
2807         .clksel         = stm_clk_div_div,
2808         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2809         .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2810         .ops            = &clkops_null,
2811         .recalc         = &omap2_clksel_recalc,
2812         .round_rate     = &omap2_clksel_round_rate,
2813         .set_rate       = &omap2_clksel_set_rate,
2814 };
2815
2816 static const struct clksel trace_clk_div_div[] = {
2817         { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2818         { .parent = NULL },
2819 };
2820
2821 static struct clk trace_clk_div_ck = {
2822         .name           = "trace_clk_div_ck",
2823         .parent         = &pmd_trace_clk_mux_ck,
2824         .clksel         = trace_clk_div_div,
2825         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2826         .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2827         .ops            = &clkops_null,
2828         .recalc         = &omap2_clksel_recalc,
2829         .round_rate     = &omap2_clksel_round_rate,
2830         .set_rate       = &omap2_clksel_set_rate,
2831 };
2832
2833 /* SCRM aux clk nodes */
2834
2835 static const struct clksel auxclk_sel[] = {
2836         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2837         { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2838         { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2839         { .parent = NULL },
2840 };
2841
2842 static struct clk auxclk0_ck = {
2843         .name           = "auxclk0_ck",
2844         .parent         = &sys_clkin_ck,
2845         .init           = &omap2_init_clksel_parent,
2846         .ops            = &clkops_omap2_dflt,
2847         .clksel         = auxclk_sel,
2848         .clksel_reg     = OMAP4_SCRM_AUXCLK0,
2849         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2850         .recalc         = &omap2_clksel_recalc,
2851         .enable_reg     = OMAP4_SCRM_AUXCLK0,
2852         .enable_bit     = OMAP4_ENABLE_SHIFT,
2853 };
2854
2855 static struct clk auxclk1_ck = {
2856         .name           = "auxclk1_ck",
2857         .parent         = &sys_clkin_ck,
2858         .init           = &omap2_init_clksel_parent,
2859         .ops            = &clkops_omap2_dflt,
2860         .clksel         = auxclk_sel,
2861         .clksel_reg     = OMAP4_SCRM_AUXCLK1,
2862         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2863         .recalc         = &omap2_clksel_recalc,
2864         .enable_reg     = OMAP4_SCRM_AUXCLK1,
2865         .enable_bit     = OMAP4_ENABLE_SHIFT,
2866 };
2867
2868 static struct clk auxclk2_ck = {
2869         .name           = "auxclk2_ck",
2870         .parent         = &sys_clkin_ck,
2871         .init           = &omap2_init_clksel_parent,
2872         .ops            = &clkops_omap2_dflt,
2873         .clksel         = auxclk_sel,
2874         .clksel_reg     = OMAP4_SCRM_AUXCLK2,
2875         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2876         .recalc         = &omap2_clksel_recalc,
2877         .enable_reg     = OMAP4_SCRM_AUXCLK2,
2878         .enable_bit     = OMAP4_ENABLE_SHIFT,
2879 };
2880 static struct clk auxclk3_ck = {
2881         .name           = "auxclk3_ck",
2882         .parent         = &sys_clkin_ck,
2883         .init           = &omap2_init_clksel_parent,
2884         .ops            = &clkops_omap2_dflt,
2885         .clksel         = auxclk_sel,
2886         .clksel_reg     = OMAP4_SCRM_AUXCLK3,
2887         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2888         .recalc         = &omap2_clksel_recalc,
2889         .enable_reg     = OMAP4_SCRM_AUXCLK3,
2890         .enable_bit     = OMAP4_ENABLE_SHIFT,
2891 };
2892
2893 static struct clk auxclk4_ck = {
2894         .name           = "auxclk4_ck",
2895         .parent         = &sys_clkin_ck,
2896         .init           = &omap2_init_clksel_parent,
2897         .ops            = &clkops_omap2_dflt,
2898         .clksel         = auxclk_sel,
2899         .clksel_reg     = OMAP4_SCRM_AUXCLK4,
2900         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2901         .recalc         = &omap2_clksel_recalc,
2902         .enable_reg     = OMAP4_SCRM_AUXCLK4,
2903         .enable_bit     = OMAP4_ENABLE_SHIFT,
2904 };
2905
2906 static struct clk auxclk5_ck = {
2907         .name           = "auxclk5_ck",
2908         .parent         = &sys_clkin_ck,
2909         .init           = &omap2_init_clksel_parent,
2910         .ops            = &clkops_omap2_dflt,
2911         .clksel         = auxclk_sel,
2912         .clksel_reg     = OMAP4_SCRM_AUXCLK5,
2913         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2914         .recalc         = &omap2_clksel_recalc,
2915         .enable_reg     = OMAP4_SCRM_AUXCLK5,
2916         .enable_bit     = OMAP4_ENABLE_SHIFT,
2917 };
2918
2919 static const struct clksel auxclkreq_sel[] = {
2920         { .parent = &auxclk0_ck, .rates = div_1_0_rates },
2921         { .parent = &auxclk1_ck, .rates = div_1_1_rates },
2922         { .parent = &auxclk2_ck, .rates = div_1_2_rates },
2923         { .parent = &auxclk3_ck, .rates = div_1_3_rates },
2924         { .parent = &auxclk4_ck, .rates = div_1_4_rates },
2925         { .parent = &auxclk5_ck, .rates = div_1_5_rates },
2926         { .parent = NULL },
2927 };
2928
2929 static struct clk auxclkreq0_ck = {
2930         .name           = "auxclkreq0_ck",
2931         .parent         = &auxclk0_ck,
2932         .init           = &omap2_init_clksel_parent,
2933         .ops            = &clkops_null,
2934         .clksel         = auxclkreq_sel,
2935         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ0,
2936         .clksel_mask    = OMAP4_MAPPING_MASK,
2937         .recalc         = &omap2_clksel_recalc,
2938 };
2939
2940 static struct clk auxclkreq1_ck = {
2941         .name           = "auxclkreq1_ck",
2942         .parent         = &auxclk1_ck,
2943         .init           = &omap2_init_clksel_parent,
2944         .ops            = &clkops_null,
2945         .clksel         = auxclkreq_sel,
2946         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ1,
2947         .clksel_mask    = OMAP4_MAPPING_MASK,
2948         .recalc         = &omap2_clksel_recalc,
2949 };
2950
2951 static struct clk auxclkreq2_ck = {
2952         .name           = "auxclkreq2_ck",
2953         .parent         = &auxclk2_ck,
2954         .init           = &omap2_init_clksel_parent,
2955         .ops            = &clkops_null,
2956         .clksel         = auxclkreq_sel,
2957         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ2,
2958         .clksel_mask    = OMAP4_MAPPING_MASK,
2959         .recalc         = &omap2_clksel_recalc,
2960 };
2961
2962 static struct clk auxclkreq3_ck = {
2963         .name           = "auxclkreq3_ck",
2964         .parent         = &auxclk3_ck,
2965         .init           = &omap2_init_clksel_parent,
2966         .ops            = &clkops_null,
2967         .clksel         = auxclkreq_sel,
2968         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ3,
2969         .clksel_mask    = OMAP4_MAPPING_MASK,
2970         .recalc         = &omap2_clksel_recalc,
2971 };
2972
2973 static struct clk auxclkreq4_ck = {
2974         .name           = "auxclkreq4_ck",
2975         .parent         = &auxclk4_ck,
2976         .init           = &omap2_init_clksel_parent,
2977         .ops            = &clkops_null,
2978         .clksel         = auxclkreq_sel,
2979         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ4,
2980         .clksel_mask    = OMAP4_MAPPING_MASK,
2981         .recalc         = &omap2_clksel_recalc,
2982 };
2983
2984 static struct clk auxclkreq5_ck = {
2985         .name           = "auxclkreq5_ck",
2986         .parent         = &auxclk5_ck,
2987         .init           = &omap2_init_clksel_parent,
2988         .ops            = &clkops_null,
2989         .clksel         = auxclkreq_sel,
2990         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ5,
2991         .clksel_mask    = OMAP4_MAPPING_MASK,
2992         .recalc         = &omap2_clksel_recalc,
2993 };
2994
2995 /*
2996  * clkdev
2997  */
2998
2999 static struct omap_clk omap44xx_clks[] = {
3000         CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
3001         CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
3002         CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
3003         CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
3004         CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
3005         CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
3006         CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
3007         CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
3008         CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
3009         CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
3010         CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
3011         CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
3012         CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
3013         CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
3014         CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
3015         CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
3016         CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
3017         CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
3018         CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
3019         CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
3020         CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
3021         CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
3022         CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
3023         CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
3024         CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
3025         CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
3026         CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
3027         CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
3028         CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
3029         CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
3030         CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
3031         CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
3032         CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
3033         CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
3034         CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
3035         CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
3036         CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
3037         CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
3038         CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
3039         CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
3040         CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
3041         CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
3042         CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
3043         CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
3044         CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
3045         CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
3046         CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
3047         CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
3048         CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
3049         CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
3050         CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
3051         CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
3052         CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
3053         CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
3054         CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
3055         CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
3056         CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
3057         CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
3058         CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
3059         CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
3060         CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
3061         CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
3062         CLK(NULL,       "dpll_unipro_ck",               &dpll_unipro_ck,        CK_443X),
3063         CLK(NULL,       "dpll_unipro_x2_ck",            &dpll_unipro_x2_ck,     CK_443X),
3064         CLK(NULL,       "dpll_unipro_m2x2_ck",          &dpll_unipro_m2x2_ck,   CK_443X),
3065         CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
3066         CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
3067         CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
3068         CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
3069         CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
3070         CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
3071         CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
3072         CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
3073         CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
3074         CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
3075         CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
3076         CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
3077         CLK(NULL,       "hsmmc6_fclk",                  &hsmmc6_fclk,   CK_443X),
3078         CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
3079         CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
3080         CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
3081         CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
3082         CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
3083         CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
3084         CLK(NULL,       "mcasp2_fclk",                  &mcasp2_fclk,   CK_443X),
3085         CLK(NULL,       "mcasp3_fclk",                  &mcasp3_fclk,   CK_443X),
3086         CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
3087         CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
3088         CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
3089         CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
3090         CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
3091         CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
3092         CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
3093         CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
3094         CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
3095         CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
3096         CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
3097         CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
3098         CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
3099         CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
3100         CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
3101         CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
3102         CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
3103         CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
3104         CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
3105         CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
3106         CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
3107         CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
3108         CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
3109         CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
3110         CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
3111         CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
3112         CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
3113         CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
3114         CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
3115         CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
3116         CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
3117         CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
3118         CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
3119         CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
3120         CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
3121         CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
3122         CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
3123         CLK("omap2_hdq.0",      "fck",                          &hdq1w_fck,     CK_443X),
3124         CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
3125         CLK("omap_i2c.1",       "fck",                          &i2c1_fck,      CK_443X),
3126         CLK("omap_i2c.2",       "fck",                          &i2c2_fck,      CK_443X),
3127         CLK("omap_i2c.3",       "fck",                          &i2c3_fck,      CK_443X),
3128         CLK("omap_i2c.4",       "fck",                          &i2c4_fck,      CK_443X),
3129         CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
3130         CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
3131         CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
3132         CLK(NULL,       "iva_fck",                      &iva_fck,       CK_443X),
3133         CLK(NULL,       "kbd_fck",                      &kbd_fck,       CK_443X),
3134         CLK(NULL,       "l3_instr_ick",                 &l3_instr_ick,  CK_443X),
3135         CLK(NULL,       "l3_main_3_ick",                &l3_main_3_ick, CK_443X),
3136         CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
3137         CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
3138         CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
3139         CLK("omap-mcbsp.1",     "fck",                          &mcbsp1_fck,    CK_443X),
3140         CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
3141         CLK("omap-mcbsp.2",     "fck",                          &mcbsp2_fck,    CK_443X),
3142         CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
3143         CLK("omap-mcbsp.3",     "fck",                          &mcbsp3_fck,    CK_443X),
3144         CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
3145         CLK("omap-mcbsp.4",     "fck",                          &mcbsp4_fck,    CK_443X),
3146         CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
3147         CLK("omap2_mcspi.1",    "fck",                          &mcspi1_fck,    CK_443X),
3148         CLK("omap2_mcspi.2",    "fck",                          &mcspi2_fck,    CK_443X),
3149         CLK("omap2_mcspi.3",    "fck",                          &mcspi3_fck,    CK_443X),
3150         CLK("omap2_mcspi.4",    "fck",                          &mcspi4_fck,    CK_443X),
3151         CLK("mmci-omap-hs.0",   "fck",                          &mmc1_fck,      CK_443X),
3152         CLK("mmci-omap-hs.1",   "fck",                          &mmc2_fck,      CK_443X),
3153         CLK("mmci-omap-hs.2",   "fck",                          &mmc3_fck,      CK_443X),
3154         CLK("mmci-omap-hs.3",   "fck",                          &mmc4_fck,      CK_443X),
3155         CLK("mmci-omap-hs.4",   "fck",                          &mmc5_fck,      CK_443X),
3156         CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
3157         CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
3158         CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
3159         CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
3160         CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
3161         CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
3162         CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
3163         CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
3164         CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
3165         CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
3166         CLK(NULL,       "slimbus1_fck",                 &slimbus1_fck,  CK_443X),
3167         CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
3168         CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
3169         CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
3170         CLK(NULL,       "slimbus2_fck",                 &slimbus2_fck,  CK_443X),
3171         CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
3172         CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
3173         CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
3174         CLK(NULL,       "gpt1_fck",                     &timer1_fck,    CK_443X),
3175         CLK(NULL,       "gpt10_fck",                    &timer10_fck,   CK_443X),
3176         CLK(NULL,       "gpt11_fck",                    &timer11_fck,   CK_443X),
3177         CLK(NULL,       "gpt2_fck",                     &timer2_fck,    CK_443X),
3178         CLK(NULL,       "gpt3_fck",                     &timer3_fck,    CK_443X),
3179         CLK(NULL,       "gpt4_fck",                     &timer4_fck,    CK_443X),
3180         CLK(NULL,       "gpt5_fck",                     &timer5_fck,    CK_443X),
3181         CLK(NULL,       "gpt6_fck",                     &timer6_fck,    CK_443X),
3182         CLK(NULL,       "gpt7_fck",                     &timer7_fck,    CK_443X),
3183         CLK(NULL,       "gpt8_fck",                     &timer8_fck,    CK_443X),
3184         CLK(NULL,       "gpt9_fck",                     &timer9_fck,    CK_443X),
3185         CLK(NULL,       "uart1_fck",                    &uart1_fck,     CK_443X),
3186         CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
3187         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
3188         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
3189         CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
3190         CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
3191         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
3192         CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
3193         CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
3194         CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
3195         CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
3196         CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
3197         CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
3198         CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
3199         CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
3200         CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
3201         CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
3202         CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
3203         CLK("musb_hdrc",        "ick",                          &usb_otg_hs_ick,        CK_443X),
3204         CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
3205         CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
3206         CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
3207         CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
3208         CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
3209         CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
3210         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
3211         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
3212         CLK("omap_wdt", "fck",                          &wd_timer2_fck, CK_443X),
3213         CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
3214         CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
3215         CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
3216         CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
3217         CLK(NULL,       "gpmc_ck",                      &dummy_ck,      CK_443X),
3218         CLK(NULL,       "gpt1_ick",                     &dummy_ck,      CK_443X),
3219         CLK(NULL,       "gpt2_ick",                     &dummy_ck,      CK_443X),
3220         CLK(NULL,       "gpt3_ick",                     &dummy_ck,      CK_443X),
3221         CLK(NULL,       "gpt4_ick",                     &dummy_ck,      CK_443X),
3222         CLK(NULL,       "gpt5_ick",                     &dummy_ck,      CK_443X),
3223         CLK(NULL,       "gpt6_ick",                     &dummy_ck,      CK_443X),
3224         CLK(NULL,       "gpt7_ick",                     &dummy_ck,      CK_443X),
3225         CLK(NULL,       "gpt8_ick",                     &dummy_ck,      CK_443X),
3226         CLK(NULL,       "gpt9_ick",                     &dummy_ck,      CK_443X),
3227         CLK(NULL,       "gpt10_ick",                    &dummy_ck,      CK_443X),
3228         CLK(NULL,       "gpt11_ick",                    &dummy_ck,      CK_443X),
3229         CLK("omap_i2c.1",       "ick",                          &dummy_ck,      CK_443X),
3230         CLK("omap_i2c.2",       "ick",                          &dummy_ck,      CK_443X),
3231         CLK("omap_i2c.3",       "ick",                          &dummy_ck,      CK_443X),
3232         CLK("omap_i2c.4",       "ick",                          &dummy_ck,      CK_443X),
3233         CLK("mmci-omap-hs.0",   "ick",                          &dummy_ck,      CK_443X),
3234         CLK("mmci-omap-hs.1",   "ick",                          &dummy_ck,      CK_443X),
3235         CLK("mmci-omap-hs.2",   "ick",                          &dummy_ck,      CK_443X),
3236         CLK("mmci-omap-hs.3",   "ick",                          &dummy_ck,      CK_443X),
3237         CLK("mmci-omap-hs.4",   "ick",                          &dummy_ck,      CK_443X),
3238         CLK("omap-mcbsp.1",     "ick",                          &dummy_ck,      CK_443X),
3239         CLK("omap-mcbsp.2",     "ick",                          &dummy_ck,      CK_443X),
3240         CLK("omap-mcbsp.3",     "ick",                          &dummy_ck,      CK_443X),
3241         CLK("omap-mcbsp.4",     "ick",                          &dummy_ck,      CK_443X),
3242         CLK("omap2_mcspi.1",    "ick",                          &dummy_ck,      CK_443X),
3243         CLK("omap2_mcspi.2",    "ick",                          &dummy_ck,      CK_443X),
3244         CLK("omap2_mcspi.3",    "ick",                          &dummy_ck,      CK_443X),
3245         CLK("omap2_mcspi.4",    "ick",                          &dummy_ck,      CK_443X),
3246         CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
3247         CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
3248         CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
3249         CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
3250         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
3251         CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
3252         CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
3253         CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
3254         CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
3255         CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
3256         CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
3257         CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
3258         CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
3259         CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
3260         CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
3261         CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
3262         CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
3263 };
3264
3265 int __init omap4xxx_clk_init(void)
3266 {
3267         struct omap_clk *c;
3268         u32 cpu_clkflg;
3269
3270         if (cpu_is_omap44xx()) {
3271                 cpu_mask = RATE_IN_4430;
3272                 cpu_clkflg = CK_443X;
3273         }
3274
3275         clk_init(&omap2_clk_functions);
3276
3277         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3278                                                                           c++)
3279                 clk_preinit(c->lk.clk);
3280
3281         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3282                                                                           c++)
3283                 if (c->cpu & cpu_clkflg) {
3284                         clkdev_add(&c->lk);
3285                         clk_register(c->lk.clk);
3286                         omap2_init_clk_clkdm(c->lk.clk);
3287                 }
3288
3289         recalculate_root_clocks();
3290
3291         /*
3292          * Only enable those clocks we will need, let the drivers
3293          * enable other clocks as necessary
3294          */
3295         clk_enable_init_clocks();
3296
3297         return 0;
3298 }