2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/list.h>
19 #include <linux/errno.h>
20 #include <linux/err.h>
21 #include <linux/delay.h>
22 #include <linux/clk.h>
24 #include <linux/bitops.h>
28 #include <plat/clock.h>
29 #include <plat/prcm.h>
31 #include <trace/events/power.h>
34 #include "clockdomain.h"
36 #include "cm2xxx_3xxx.h"
37 #include "cm-regbits-24xx.h"
38 #include "cm-regbits-34xx.h"
43 * clkdm_control: if true, then when a clock is enabled in the
44 * hardware, its clockdomain will first be enabled; and when a clock
45 * is disabled in the hardware, its clockdomain will be disabled
48 static bool clkdm_control = true;
51 * OMAP2+ specific clock functions
54 /* Private functions */
57 * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE
58 * @clk: struct clk * belonging to the module
60 * If the necessary clocks for the OMAP hardware IP block that
61 * corresponds to clock @clk are enabled, then wait for the module to
62 * indicate readiness (i.e., to leave IDLE). This code does not
63 * belong in the clock code and will be moved in the medium term to
64 * module-dependent code. No return value.
66 static void _omap2_module_wait_ready(struct clk *clk)
68 void __iomem *companion_reg, *idlest_reg;
69 u8 other_bit, idlest_bit, idlest_val;
71 /* Not all modules have multiple clocks that their IDLEST depends on */
72 if (clk->ops->find_companion) {
73 clk->ops->find_companion(clk, &companion_reg, &other_bit);
74 if (!(__raw_readl(companion_reg) & (1 << other_bit)))
78 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
80 omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val,
84 /* Public functions */
87 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
88 * @clk: OMAP clock struct ptr to use
90 * Convert a clockdomain name stored in a struct clk 'clk' into a
91 * clockdomain pointer, and save it into the struct clk. Intended to be
92 * called during clk_register(). No return value.
94 void omap2_init_clk_clkdm(struct clk *clk)
96 struct clockdomain *clkdm;
101 clkdm = clkdm_lookup(clk->clkdm_name);
103 pr_debug("clock: associated clk %s to clkdm %s\n",
104 clk->name, clk->clkdm_name);
107 pr_debug("clock: could not associate clk %s to "
108 "clkdm %s\n", clk->name, clk->clkdm_name);
113 * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable
115 * Prevent the OMAP clock code from calling into the clockdomain code
116 * when a hardware clock in that clockdomain is enabled or disabled.
117 * Intended to be called at init time from omap*_clk_init(). No
120 void __init omap2_clk_disable_clkdm_control(void)
122 clkdm_control = false;
126 * omap2_clk_dflt_find_companion - find companion clock to @clk
127 * @clk: struct clk * to find the companion clock of
128 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
129 * @other_bit: u8 ** to return the companion clock bit shift in
131 * Note: We don't need special code here for INVERT_ENABLE for the
132 * time being since INVERT_ENABLE only applies to clocks enabled by
135 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's
136 * just a matter of XORing the bits.
138 * Some clocks don't have companion clocks. For example, modules with
139 * only an interface clock (such as MAILBOXES) don't have a companion
140 * clock. Right now, this code relies on the hardware exporting a bit
141 * in the correct companion register that indicates that the
142 * nonexistent 'companion clock' is active. Future patches will
143 * associate this type of code with per-module data structures to
144 * avoid this issue, and remove the casts. No return value.
146 void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
152 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
153 * it's just a matter of XORing the bits.
155 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
157 *other_reg = (__force void __iomem *)r;
158 *other_bit = clk->enable_bit;
162 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
163 * @clk: struct clk * to find IDLEST info for
164 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in
165 * @idlest_bit: u8 * to return the CM_IDLEST bit shift in
166 * @idlest_val: u8 * to return the idle status indicator
168 * Return the CM_IDLEST register address and bit shift corresponding
169 * to the module that "owns" this clock. This default code assumes
170 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
171 * the IDLEST register address ID corresponds to the CM_*CLKEN
172 * register address ID (e.g., that CM_FCLKEN2 corresponds to
173 * CM_IDLEST2). This is not true for all modules. No return value.
175 void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
176 u8 *idlest_bit, u8 *idlest_val)
180 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
181 *idlest_reg = (__force void __iomem *)r;
182 *idlest_bit = clk->enable_bit;
185 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
186 * 34xx reverses this, just to keep us on our toes
187 * AM35xx uses both, depending on the module.
189 if (cpu_is_omap24xx())
190 *idlest_val = OMAP24XX_CM_IDLEST_VAL;
191 else if (cpu_is_omap34xx())
192 *idlest_val = OMAP34XX_CM_IDLEST_VAL;
198 int omap2_dflt_clk_enable(struct clk *clk)
202 if (unlikely(clk->enable_reg == NULL)) {
203 pr_err("clock.c: Enable for %s without enable code\n",
205 return 0; /* REVISIT: -EINVAL */
208 v = __raw_readl(clk->enable_reg);
209 if (clk->flags & INVERT_ENABLE)
210 v &= ~(1 << clk->enable_bit);
212 v |= (1 << clk->enable_bit);
213 __raw_writel(v, clk->enable_reg);
214 v = __raw_readl(clk->enable_reg); /* OCP barrier */
216 if (clk->ops->find_idlest)
217 _omap2_module_wait_ready(clk);
222 void omap2_dflt_clk_disable(struct clk *clk)
226 if (!clk->enable_reg) {
228 * 'Independent' here refers to a clock which is not
229 * controlled by its parent.
231 printk(KERN_ERR "clock: clk_disable called on independent "
232 "clock %s which has no enable_reg\n", clk->name);
236 v = __raw_readl(clk->enable_reg);
237 if (clk->flags & INVERT_ENABLE)
238 v |= (1 << clk->enable_bit);
240 v &= ~(1 << clk->enable_bit);
241 __raw_writel(v, clk->enable_reg);
242 /* No OCP barrier needed here since it is a disable operation */
245 const struct clkops clkops_omap2_dflt_wait = {
246 .enable = omap2_dflt_clk_enable,
247 .disable = omap2_dflt_clk_disable,
248 .find_companion = omap2_clk_dflt_find_companion,
249 .find_idlest = omap2_clk_dflt_find_idlest,
252 const struct clkops clkops_omap2_dflt = {
253 .enable = omap2_dflt_clk_enable,
254 .disable = omap2_dflt_clk_disable,
258 * omap2_clk_disable - disable a clock, if the system is not using it
259 * @clk: struct clk * to disable
261 * Decrements the usecount on struct clk @clk. If there are no users
262 * left, call the clkops-specific clock disable function to disable it
263 * in hardware. If the clock is part of a clockdomain (which they all
264 * should be), request that the clockdomain be disabled. (It too has
265 * a usecount, and so will not be disabled in the hardware until it no
266 * longer has any users.) If the clock has a parent clock (most of
267 * them do), then call ourselves, recursing on the parent clock. This
268 * can cause an entire branch of the clock tree to be powered off by
269 * simply disabling one clock. Intended to be called with the clockfw_lock
270 * spinlock held. No return value.
272 void omap2_clk_disable(struct clk *clk)
274 if (clk->usecount == 0) {
275 WARN(1, "clock: %s: omap2_clk_disable() called, but usecount "
276 "already 0?", clk->name);
280 pr_debug("clock: %s: decrementing usecount\n", clk->name);
284 if (clk->usecount > 0)
287 pr_debug("clock: %s: disabling in hardware\n", clk->name);
289 if (clk->ops && clk->ops->disable) {
290 trace_clock_disable(clk->name, 0, smp_processor_id());
291 clk->ops->disable(clk);
294 if (clkdm_control && clk->clkdm)
295 clkdm_clk_disable(clk->clkdm, clk);
298 omap2_clk_disable(clk->parent);
302 * omap2_clk_enable - request that the system enable a clock
303 * @clk: struct clk * to enable
305 * Increments the usecount on struct clk @clk. If there were no users
306 * previously, then recurse up the clock tree, enabling all of the
307 * clock's parents and all of the parent clockdomains, and finally,
308 * enabling @clk's clockdomain, and @clk itself. Intended to be
309 * called with the clockfw_lock spinlock held. Returns 0 upon success
310 * or a negative error code upon failure.
312 int omap2_clk_enable(struct clk *clk)
316 pr_debug("clock: %s: incrementing usecount\n", clk->name);
320 if (clk->usecount > 1)
323 pr_debug("clock: %s: enabling in hardware\n", clk->name);
326 ret = omap2_clk_enable(clk->parent);
328 WARN(1, "clock: %s: could not enable parent %s: %d\n",
329 clk->name, clk->parent->name, ret);
334 if (clkdm_control && clk->clkdm) {
335 ret = clkdm_clk_enable(clk->clkdm, clk);
337 WARN(1, "clock: %s: could not enable clockdomain %s: "
338 "%d\n", clk->name, clk->clkdm->name, ret);
343 if (clk->ops && clk->ops->enable) {
344 trace_clock_enable(clk->name, 1, smp_processor_id());
345 ret = clk->ops->enable(clk);
347 WARN(1, "clock: %s: could not enable: %d\n",
356 if (clkdm_control && clk->clkdm)
357 clkdm_clk_disable(clk->clkdm, clk);
360 omap2_clk_disable(clk->parent);
367 /* Given a clock and a rate apply a clock specific rounding function */
368 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
371 return clk->round_rate(clk, rate);
376 /* Set the clock rate for a clock source */
377 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
381 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
383 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
385 trace_clock_set_rate(clk->name, rate, smp_processor_id());
386 ret = clk->set_rate(clk, rate);
392 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
397 if (clk->parent == new_parent)
400 return omap2_clksel_set_parent(clk, new_parent);
404 * OMAP2+ clock reset and init functions
407 #ifdef CONFIG_OMAP_RESET_CLOCKS
408 void omap2_clk_disable_unused(struct clk *clk)
412 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
414 regval32 = __raw_readl(clk->enable_reg);
415 if ((regval32 & (1 << clk->enable_bit)) == v)
418 pr_debug("Disabling unused clock \"%s\"\n", clk->name);
419 if (cpu_is_omap34xx()) {
420 omap2_clk_enable(clk);
421 omap2_clk_disable(clk);
423 clk->ops->disable(clk);
425 if (clk->clkdm != NULL)
426 pwrdm_state_switch(clk->clkdm->pwrdm.ptr);
431 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
432 * @mpurate_ck_name: clk name of the clock to change rate
434 * Change the ARM MPU clock rate to the rate specified on the command
435 * line, if one was specified. @mpurate_ck_name should be
436 * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx.
437 * XXX Does not handle voltage scaling - on OMAP2xxx this is currently
438 * handled by the virt_prcm_set clock, but this should be handled by
439 * the OPP layer. XXX This is intended to be handled by the OPP layer
440 * code in the near future and should be removed from the clock code.
441 * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects
442 * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name
443 * cannot be found, or 0 upon success.
445 int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name)
447 struct clk *mpurate_ck;
453 mpurate_ck = clk_get(NULL, mpurate_ck_name);
454 if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name))
457 r = clk_set_rate(mpurate_ck, mpurate);
458 if (IS_ERR_VALUE(r)) {
459 WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
460 mpurate_ck->name, mpurate, r);
466 recalculate_root_clocks();
474 * omap2_clk_print_new_rates - print summary of current clock tree rates
475 * @hfclkin_ck_name: clk name for the off-chip HF oscillator
476 * @core_ck_name: clk name for the on-chip CORE_CLK
477 * @mpu_ck_name: clk name for the ARM MPU clock
479 * Prints a short message to the console with the HFCLKIN oscillator
480 * rate, the rate of the CORE clock, and the rate of the ARM MPU clock.
481 * Called by the boot-time MPU rate switching code. XXX This is intended
482 * to be handled by the OPP layer code in the near future and should be
483 * removed from the clock code. No return value.
485 void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
486 const char *core_ck_name,
487 const char *mpu_ck_name)
489 struct clk *hfclkin_ck, *core_ck, *mpu_ck;
490 unsigned long hfclkin_rate;
492 mpu_ck = clk_get(NULL, mpu_ck_name);
493 if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name))
496 core_ck = clk_get(NULL, core_ck_name);
497 if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
500 hfclkin_ck = clk_get(NULL, hfclkin_ck_name);
501 if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name))
504 hfclkin_rate = clk_get_rate(hfclkin_ck);
506 pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
507 "%ld.%01ld/%ld/%ld MHz\n",
508 (hfclkin_rate / 1000000),
509 ((hfclkin_rate / 100000) % 10),
510 (clk_get_rate(core_ck) / 1000000),
511 (clk_get_rate(mpu_ck) / 1000000));
516 struct clk_functions omap2_clk_functions = {
517 .clk_enable = omap2_clk_enable,
518 .clk_disable = omap2_clk_disable,
519 .clk_round_rate = omap2_clk_round_rate,
520 .clk_set_rate = omap2_clk_set_rate,
521 .clk_set_parent = omap2_clk_set_parent,
522 .clk_disable_unused = omap2_clk_disable_unused,