1 // SPDX-License-Identifier: GPL-2.0+
5 * Common bootmode functions for omap based boards
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
13 #include <dm/uclass.h>
14 #include <fs_loader.h>
16 #include <asm/global_data.h>
17 #include <asm/omap_common.h>
18 #include <asm/omap_sec_common.h>
19 #include <asm/arch/omap.h>
20 #include <asm/arch/mmc_host_def.h>
21 #include <asm/arch/sys_proto.h>
25 #include <remoteproc.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 #define IPU1_LOAD_ADDR (0xa17ff000)
31 #define MAX_REMOTECORE_BIN_SIZE (8 * 0x100000)
32 #define IPU2_LOAD_ADDR (IPU1_LOAD_ADDR + MAX_REMOTECORE_BIN_SIZE)
34 __weak u32 omap_sys_boot_device(void)
36 return BOOT_DEVICE_NONE;
39 void save_omap_boot_params(void)
41 u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
42 struct omap_boot_parameters *omap_boot_params;
43 int sys_boot_device = 0;
47 if ((boot_params < NON_SECURE_SRAM_START) ||
48 (boot_params > NON_SECURE_SRAM_END))
51 omap_boot_params = (struct omap_boot_parameters *)boot_params;
53 boot_device = omap_boot_params->boot_device;
54 boot_mode = MMCSD_MODE_UNDEFINED;
58 #ifdef BOOT_DEVICE_NAND_I2C
60 * Re-map NAND&I2C boot-device to the "normal" NAND boot-device.
61 * Otherwise the SPL boot IF can't handle this device correctly.
62 * Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens
63 * Draco leads to this boot-device passed to SPL from the BootROM.
65 if (boot_device == BOOT_DEVICE_NAND_I2C)
66 boot_device = BOOT_DEVICE_NAND;
68 #ifdef BOOT_DEVICE_QSPI_4
70 * We get different values for QSPI_1 and QSPI_4 being used, but
71 * don't actually care about this difference. Rather than
72 * mangle the later code, if we're coming in as QSPI_4 just
73 * change to the QSPI_1 value.
75 if (boot_device == BOOT_DEVICE_QSPI_4)
76 boot_device = BOOT_DEVICE_SPI;
79 * When booting from peripheral booting, the boot device is not usable
80 * as-is (unless there is support for it), so the boot device is instead
81 * figured out using the SYS_BOOT pins.
83 switch (boot_device) {
84 #if defined(BOOT_DEVICE_UART) && !defined(CONFIG_SPL_YMODEM_SUPPORT)
85 case BOOT_DEVICE_UART:
89 #if defined(BOOT_DEVICE_USB) && !defined(CONFIG_SPL_USB_STORAGE)
94 #if defined(BOOT_DEVICE_USBETH) && !defined(CONFIG_SPL_USB_ETHER)
95 case BOOT_DEVICE_USBETH:
99 #if defined(BOOT_DEVICE_CPGMAC) && !defined(CONFIG_SPL_ETH)
100 case BOOT_DEVICE_CPGMAC:
104 #if defined(BOOT_DEVICE_DFU) && !defined(CONFIG_SPL_DFU)
105 case BOOT_DEVICE_DFU:
111 if (sys_boot_device) {
112 boot_device = omap_sys_boot_device();
114 /* MMC raw mode will fallback to FS mode. */
115 if ((boot_device >= MMC_BOOT_DEVICES_START) &&
116 (boot_device <= MMC_BOOT_DEVICES_END))
117 boot_mode = MMCSD_MODE_RAW;
120 gd->arch.omap_boot_device = boot_device;
124 #ifdef CONFIG_OMAP34XX
125 if ((boot_device >= MMC_BOOT_DEVICES_START) &&
126 (boot_device <= MMC_BOOT_DEVICES_END)) {
127 switch (boot_device) {
128 case BOOT_DEVICE_MMC1:
129 boot_mode = MMCSD_MODE_FS;
131 case BOOT_DEVICE_MMC2:
132 boot_mode = MMCSD_MODE_RAW;
138 * If the boot device was dynamically changed and doesn't match what
139 * the bootrom initially booted, we cannot use the boot device
140 * descriptor to figure out the boot mode.
142 if ((boot_device == omap_boot_params->boot_device) &&
143 (boot_device >= MMC_BOOT_DEVICES_START) &&
144 (boot_device <= MMC_BOOT_DEVICES_END)) {
145 boot_params = omap_boot_params->boot_device_descriptor;
146 if ((boot_params < NON_SECURE_SRAM_START) ||
147 (boot_params > NON_SECURE_SRAM_END))
150 boot_params = *((u32 *)(boot_params + DEVICE_DATA_OFFSET));
151 if ((boot_params < NON_SECURE_SRAM_START) ||
152 (boot_params > NON_SECURE_SRAM_END))
155 boot_mode = *((u32 *)(boot_params + BOOT_MODE_OFFSET));
157 if (boot_mode != MMCSD_MODE_FS &&
158 boot_mode != MMCSD_MODE_RAW)
159 #ifdef CONFIG_SUPPORT_EMMC_BOOT
160 boot_mode = MMCSD_MODE_EMMCBOOT;
162 boot_mode = MMCSD_MODE_UNDEFINED;
167 gd->arch.omap_boot_mode = boot_mode;
169 #if !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX)
173 gd->arch.omap_ch_flags = omap_boot_params->ch_flags;
177 #ifdef CONFIG_SPL_BUILD
178 u32 spl_boot_device(void)
180 return gd->arch.omap_boot_device;
183 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
185 return gd->arch.omap_boot_mode;
188 int load_firmware(char *name_fw, u32 *loadaddr)
190 struct udevice *fsdev;
193 if (!IS_ENABLED(CONFIG_FS_LOADER))
199 if (!get_fs_loader(&fsdev)) {
200 size = request_firmware_into_buf(fsdev, name_fw,
201 (void *)*loadaddr, 0, 0);
207 void spl_boot_ipu(void)
210 u32 loadaddr = IPU1_LOAD_ADDR;
212 if (!IS_ENABLED(CONFIG_SPL_BUILD) ||
213 !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
216 size = load_firmware("dra7-ipu1-fw.xem4", &loadaddr);
218 pr_err("Firmware loading failed\n");
222 enable_ipu1_clocks();
223 ret = rproc_dev_init(0);
225 debug("%s: IPU1 failed to initialize on rproc (%d)\n",
230 ret = rproc_load(0, IPU1_LOAD_ADDR, 0x2000000);
232 debug("%s: IPU1 failed to load on rproc (%d)\n", __func__,
237 debug("Starting IPU1...\n");
239 ret = rproc_start(0);
241 debug("%s: IPU1 failed to start (%d)\n", __func__, ret);
244 loadaddr = IPU2_LOAD_ADDR;
245 size = load_firmware("dra7-ipu2-fw.xem4", &loadaddr);
247 pr_err("Firmware loading failed for ipu2\n");
251 enable_ipu2_clocks();
252 ret = rproc_dev_init(1);
254 debug("%s: IPU2 failed to initialize on rproc (%d)\n", __func__,
259 ret = rproc_load(1, IPU2_LOAD_ADDR, 0x2000000);
261 debug("%s: IPU2 failed to load on rproc (%d)\n", __func__,
266 debug("Starting IPU2...\n");
268 ret = rproc_start(1);
270 debug("%s: IPU2 failed to start (%d)\n", __func__, ret);
273 void spl_board_init(void)
275 /* Prepare console output */
276 preloader_console_init();
278 #if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
281 #if defined(CONFIG_SPL_I2C) && !CONFIG_IS_ENABLED(DM_I2C)
282 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
284 #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW)
287 #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
291 am33xx_spl_board_init();
293 if (IS_ENABLED(CONFIG_SPL_BUILD) &&
294 IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
298 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
300 typedef void __noreturn (*image_entry_noargs_t)(u32 *);
301 image_entry_noargs_t image_entry =
302 (image_entry_noargs_t) spl_image->entry_point;
304 u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
306 debug("image entry point: 0x%lX\n", spl_image->entry_point);
307 /* Pass the saved boot_params from rom code */
308 image_entry((u32 *)boot_params);
312 #ifdef CONFIG_SCSI_AHCI_PLAT
313 void arch_preboot_os(void)
315 ahci_reset((void __iomem *)DWC_AHSATA_BASE);
319 #ifdef CONFIG_TI_SECURE_DEVICE
320 void board_fit_image_post_process(const void *fit, int node, void **p_image,
323 secure_boot_verify_image(p_image, p_size);
326 static void tee_image_process(ulong tee_image, size_t tee_size)
328 secure_tee_install((u32)tee_image);
330 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, tee_image_process);