1 // SPDX-License-Identifier: GPL-2.0+
5 * Common bootmode functions for omap based boards
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
13 #include <dm/uclass.h>
14 #include <fs_loader.h>
16 #include <asm/global_data.h>
17 #include <asm/omap_common.h>
18 #include <asm/arch/omap.h>
19 #include <asm/arch/mmc_host_def.h>
20 #include <asm/arch/sys_proto.h>
24 #include <remoteproc.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #define IPU1_LOAD_ADDR (0xa17ff000)
29 #define MAX_REMOTECORE_BIN_SIZE (8 * 0x100000)
30 #define IPU2_LOAD_ADDR (IPU1_LOAD_ADDR + MAX_REMOTECORE_BIN_SIZE)
32 __weak u32 omap_sys_boot_device(void)
34 return BOOT_DEVICE_NONE;
37 void save_omap_boot_params(void)
39 u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
40 struct omap_boot_parameters *omap_boot_params;
41 int sys_boot_device = 0;
45 if ((boot_params < NON_SECURE_SRAM_START) ||
46 (boot_params > NON_SECURE_SRAM_END))
49 omap_boot_params = (struct omap_boot_parameters *)boot_params;
51 boot_device = omap_boot_params->boot_device;
52 boot_mode = MMCSD_MODE_UNDEFINED;
56 #ifdef BOOT_DEVICE_NAND_I2C
58 * Re-map NAND&I2C boot-device to the "normal" NAND boot-device.
59 * Otherwise the SPL boot IF can't handle this device correctly.
60 * Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens
61 * Draco leads to this boot-device passed to SPL from the BootROM.
63 if (boot_device == BOOT_DEVICE_NAND_I2C)
64 boot_device = BOOT_DEVICE_NAND;
66 #ifdef BOOT_DEVICE_QSPI_4
68 * We get different values for QSPI_1 and QSPI_4 being used, but
69 * don't actually care about this difference. Rather than
70 * mangle the later code, if we're coming in as QSPI_4 just
71 * change to the QSPI_1 value.
73 if (boot_device == BOOT_DEVICE_QSPI_4)
74 boot_device = BOOT_DEVICE_SPI;
78 * On PG2.0 and later TI816x the values we get when booting are not the
79 * same as on PG1.0, which is what the defines are based on. Update
82 if (get_cpu_rev() != 1) {
83 if (boot_device == 0x05) {
84 omap_boot_params->boot_device = BOOT_DEVICE_NAND;
85 boot_device = BOOT_DEVICE_NAND;
87 if (boot_device == 0x08) {
88 omap_boot_params->boot_device = BOOT_DEVICE_MMC1;
89 boot_device = BOOT_DEVICE_MMC1;
94 * When booting from peripheral booting, the boot device is not usable
95 * as-is (unless there is support for it), so the boot device is instead
96 * figured out using the SYS_BOOT pins.
98 switch (boot_device) {
99 #if defined(BOOT_DEVICE_UART) && !defined(CONFIG_SPL_YMODEM_SUPPORT)
100 case BOOT_DEVICE_UART:
104 #if defined(BOOT_DEVICE_USB) && !defined(CONFIG_SPL_USB_STORAGE)
105 case BOOT_DEVICE_USB:
109 #if defined(BOOT_DEVICE_USBETH) && !defined(CONFIG_SPL_USB_ETHER)
110 case BOOT_DEVICE_USBETH:
114 #if defined(BOOT_DEVICE_CPGMAC) && !defined(CONFIG_SPL_ETH)
115 case BOOT_DEVICE_CPGMAC:
119 #if defined(BOOT_DEVICE_DFU) && !defined(CONFIG_SPL_DFU)
120 case BOOT_DEVICE_DFU:
126 if (sys_boot_device) {
127 boot_device = omap_sys_boot_device();
129 /* MMC raw mode will fallback to FS mode. */
130 if ((boot_device >= MMC_BOOT_DEVICES_START) &&
131 (boot_device <= MMC_BOOT_DEVICES_END))
132 boot_mode = MMCSD_MODE_RAW;
135 gd->arch.omap_boot_device = boot_device;
139 #ifdef CONFIG_OMAP34XX
140 if ((boot_device >= MMC_BOOT_DEVICES_START) &&
141 (boot_device <= MMC_BOOT_DEVICES_END)) {
142 switch (boot_device) {
143 case BOOT_DEVICE_MMC1:
144 boot_mode = MMCSD_MODE_FS;
146 case BOOT_DEVICE_MMC2:
147 boot_mode = MMCSD_MODE_RAW;
153 * If the boot device was dynamically changed and doesn't match what
154 * the bootrom initially booted, we cannot use the boot device
155 * descriptor to figure out the boot mode.
157 if ((boot_device == omap_boot_params->boot_device) &&
158 (boot_device >= MMC_BOOT_DEVICES_START) &&
159 (boot_device <= MMC_BOOT_DEVICES_END)) {
160 boot_params = omap_boot_params->boot_device_descriptor;
161 if ((boot_params < NON_SECURE_SRAM_START) ||
162 (boot_params > NON_SECURE_SRAM_END))
165 boot_params = *((u32 *)(boot_params + DEVICE_DATA_OFFSET));
166 if ((boot_params < NON_SECURE_SRAM_START) ||
167 (boot_params > NON_SECURE_SRAM_END))
170 boot_mode = *((u32 *)(boot_params + BOOT_MODE_OFFSET));
172 if (boot_mode != MMCSD_MODE_FS &&
173 boot_mode != MMCSD_MODE_RAW)
174 #ifdef CONFIG_SUPPORT_EMMC_BOOT
175 boot_mode = MMCSD_MODE_EMMCBOOT;
177 boot_mode = MMCSD_MODE_UNDEFINED;
182 gd->arch.omap_boot_mode = boot_mode;
184 #if !defined(CONFIG_TI814X) && !defined(CONFIG_TI816X) && \
185 !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX)
189 gd->arch.omap_ch_flags = omap_boot_params->ch_flags;
193 #ifdef CONFIG_SPL_BUILD
194 u32 spl_boot_device(void)
196 return gd->arch.omap_boot_device;
199 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
201 return gd->arch.omap_boot_mode;
204 int load_firmware(char *name_fw, u32 *loadaddr)
206 struct udevice *fsdev;
209 if (!IS_ENABLED(CONFIG_FS_LOADER))
215 if (!uclass_get_device(UCLASS_FS_FIRMWARE_LOADER, 0, &fsdev)) {
216 size = request_firmware_into_buf(fsdev, name_fw,
217 (void *)*loadaddr, 0, 0);
223 void spl_boot_ipu(void)
226 u32 loadaddr = IPU1_LOAD_ADDR;
228 if (!IS_ENABLED(CONFIG_SPL_BUILD) ||
229 !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
232 size = load_firmware("dra7-ipu1-fw.xem4", &loadaddr);
234 pr_err("Firmware loading failed\n");
238 enable_ipu1_clocks();
239 ret = rproc_dev_init(0);
241 debug("%s: IPU1 failed to initialize on rproc (%d)\n",
246 ret = rproc_load(0, IPU1_LOAD_ADDR, 0x2000000);
248 debug("%s: IPU1 failed to load on rproc (%d)\n", __func__,
253 debug("Starting IPU1...\n");
255 ret = rproc_start(0);
257 debug("%s: IPU1 failed to start (%d)\n", __func__, ret);
260 loadaddr = IPU2_LOAD_ADDR;
261 size = load_firmware("dra7-ipu2-fw.xem4", &loadaddr);
263 pr_err("Firmware loading failed for ipu2\n");
267 enable_ipu2_clocks();
268 ret = rproc_dev_init(1);
270 debug("%s: IPU2 failed to initialize on rproc (%d)\n", __func__,
275 ret = rproc_load(1, IPU2_LOAD_ADDR, 0x2000000);
277 debug("%s: IPU2 failed to load on rproc (%d)\n", __func__,
282 debug("Starting IPU2...\n");
284 ret = rproc_start(1);
286 debug("%s: IPU2 failed to start (%d)\n", __func__, ret);
289 void spl_board_init(void)
291 /* Prepare console output */
292 preloader_console_init();
294 #if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
297 #if defined(CONFIG_SPL_I2C) && !CONFIG_IS_ENABLED(DM_I2C)
298 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
300 #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW)
303 #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
307 am33xx_spl_board_init();
309 if (IS_ENABLED(CONFIG_SPL_BUILD) &&
310 IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
314 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
316 typedef void __noreturn (*image_entry_noargs_t)(u32 *);
317 image_entry_noargs_t image_entry =
318 (image_entry_noargs_t) spl_image->entry_point;
320 u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
322 debug("image entry point: 0x%lX\n", spl_image->entry_point);
323 /* Pass the saved boot_params from rom code */
324 image_entry((u32 *)boot_params);
328 #ifdef CONFIG_SCSI_AHCI_PLAT
329 void arch_preboot_os(void)
331 ahci_reset((void __iomem *)DWC_AHSATA_BASE);