arch/arm/mach-omap2/am33xx/emif4.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * emif4.c
   4  *
   5  * AM33XX emif4 configuration file
   6  *
   7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch/cpu.h>
  12 #include <asm/arch/ddr_defs.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/io.h>
  17 #include <asm/emif.h>
  18
  19 static struct vtp_reg *vtpreg[2] = {
  20                                 (struct vtp_reg *)VTP0_CTRL_ADDR,
  21                                 (struct vtp_reg *)VTP1_CTRL_ADDR};
  22 #ifdef CONFIG_AM33XX
  23 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
  24 #endif
  25 #ifdef CONFIG_AM43XX
  26 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
  27 static struct cm_device_inst *cm_device =
  28                                 (struct cm_device_inst *)CM_DEVICE_INST;
  29 #endif
  30
  31 static void config_vtp(int nr)
  32 {
  33         writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
  34                         &vtpreg[nr]->vtp0ctrlreg);
  35         writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
  36                         &vtpreg[nr]->vtp0ctrlreg);
  37         writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
  38                         &vtpreg[nr]->vtp0ctrlreg);
  39
  40         /* Poll for READY */
  41         while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
  42                         VTP_CTRL_READY)
  43                 ;
  44 }
  45
  46 void __weak ddr_pll_config(unsigned int ddrpll_m)
  47 {
  48 }
  49
  50 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
  51                 const struct ddr_data *data, const struct cmd_control *ctrl,
  52                 const struct emif_regs *regs, int nr)
  53 {
  54         ddr_pll_config(pll);
  55         config_vtp(nr);
  56         config_cmd_ctrl(ctrl, nr);
  57
  58         config_ddr_data(data, nr);
  59 #ifdef CONFIG_AM33XX
  60         config_io_ctrl(ioregs);
  61
  62         /* Set CKE to be controlled by EMIF/DDR PHY */
  63         writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
  64
  65 #endif
  66 #ifdef CONFIG_AM43XX
  67         writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
  68         while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
  69                 ;
  70
  71         config_io_ctrl(ioregs);
  72
  73         /* Set CKE to be controlled by EMIF/DDR PHY */
  74         writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
  75
  76         if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
  77 #ifndef CONFIG_SPL_RTC_DDR_SUPPORT
  78                 /* Allow EMIF to control DDR_RESET */
  79                 writel(0x00000000, &ddrctrl->ddrioctrl);
  80 #else
  81                 /* Override EMIF DDR_RESET control */
  82                 writel(0x80000000, &ddrctrl->ddrioctrl);
  83 #endif /* CONFIG_SPL_RTC_DDR_SUPPORT */
  84 #endif
  85
  86         /* Program EMIF instance */
  87         config_ddr_phy(regs, nr);
  88         set_sdram_timings(regs, nr);
  89         if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
  90                 config_sdram_emif4d5(regs, nr);
  91         else
  92                 config_sdram(regs, nr);
  93 }