arch/arm/mach-omap2/am33xx/emif4.c

   1 /*
   2  * emif4.c
   3  *
   4  * AM33XX emif4 configuration file
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/ddr_defs.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/io.h>
  18 #include <asm/emif.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 int dram_init(void)
  23 {
  24 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  25         sdram_init();
  26 #endif
  27
  28         /* dram_init must store complete ramsize in gd->ram_size */
  29         gd->ram_size = get_ram_size(
  30                         (void *)CONFIG_SYS_SDRAM_BASE,
  31                         CONFIG_MAX_RAM_BANK_SIZE);
  32         return 0;
  33 }
  34
  35 int dram_init_banksize(void)
  36 {
  37         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  38         gd->bd->bi_dram[0].size = gd->ram_size;
  39
  40         return 0;
  41 }
  42
  43
  44 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  45 #ifdef CONFIG_TI81XX
  46 static struct dmm_lisa_map_regs *hw_lisa_map_regs =
  47                                 (struct dmm_lisa_map_regs *)DMM_BASE;
  48 #endif
  49 #ifndef CONFIG_TI816X
  50 static struct vtp_reg *vtpreg[2] = {
  51                                 (struct vtp_reg *)VTP0_CTRL_ADDR,
  52                                 (struct vtp_reg *)VTP1_CTRL_ADDR};
  53 #endif
  54 #ifdef CONFIG_AM33XX
  55 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
  56 #endif
  57 #ifdef CONFIG_AM43XX
  58 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
  59 static struct cm_device_inst *cm_device =
  60                                 (struct cm_device_inst *)CM_DEVICE_INST;
  61 #endif
  62
  63 #ifdef CONFIG_TI81XX
  64 void config_dmm(const struct dmm_lisa_map_regs *regs)
  65 {
  66         enable_dmm_clocks();
  67
  68         writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
  69         writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
  70         writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
  71         writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
  72
  73         writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
  74         writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
  75         writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
  76         writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
  77 }
  78 #endif
  79
  80 #ifndef CONFIG_TI816X
  81 static void config_vtp(int nr)
  82 {
  83         writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
  84                         &vtpreg[nr]->vtp0ctrlreg);
  85         writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
  86                         &vtpreg[nr]->vtp0ctrlreg);
  87         writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
  88                         &vtpreg[nr]->vtp0ctrlreg);
  89
  90         /* Poll for READY */
  91         while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
  92                         VTP_CTRL_READY)
  93                 ;
  94 }
  95 #endif
  96
  97 void __weak ddr_pll_config(unsigned int ddrpll_m)
  98 {
  99 }
 100
 101 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
 102                 const struct ddr_data *data, const struct cmd_control *ctrl,
 103                 const struct emif_regs *regs, int nr)
 104 {
 105         ddr_pll_config(pll);
 106 #ifndef CONFIG_TI816X
 107         config_vtp(nr);
 108 #endif
 109         config_cmd_ctrl(ctrl, nr);
 110
 111         config_ddr_data(data, nr);
 112 #ifdef CONFIG_AM33XX
 113         config_io_ctrl(ioregs);
 114
 115         /* Set CKE to be controlled by EMIF/DDR PHY */
 116         writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
 117
 118 #endif
 119 #ifdef CONFIG_AM43XX
 120         writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
 121         while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
 122                 ;
 123
 124         config_io_ctrl(ioregs);
 125
 126         /* Set CKE to be controlled by EMIF/DDR PHY */
 127         writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
 128
 129         if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
 130                 /* Allow EMIF to control DDR_RESET */
 131                 writel(0x00000000, &ddrctrl->ddrioctrl);
 132 #endif
 133
 134         /* Program EMIF instance */
 135         config_ddr_phy(regs, nr);
 136         set_sdram_timings(regs, nr);
 137         if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
 138                 config_sdram_emif4d5(regs, nr);
 139         else
 140                 config_sdram(regs, nr);
 141 }
 142 #endif