1 // SPDX-License-Identifier: GPL-2.0+
5 * clocks for AM43XX based boards
6 * Derived from AM33XX based boards
8 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
18 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
19 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
20 struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
22 const struct dpll_regs dpll_mpu_regs = {
23 .cm_clkmode_dpll = CM_WKUP + 0x560,
24 .cm_idlest_dpll = CM_WKUP + 0x564,
25 .cm_clksel_dpll = CM_WKUP + 0x56c,
26 .cm_div_m2_dpll = CM_WKUP + 0x570,
29 const struct dpll_regs dpll_core_regs = {
30 .cm_clkmode_dpll = CM_WKUP + 0x520,
31 .cm_idlest_dpll = CM_WKUP + 0x524,
32 .cm_clksel_dpll = CM_WKUP + 0x52C,
33 .cm_div_m4_dpll = CM_WKUP + 0x538,
34 .cm_div_m5_dpll = CM_WKUP + 0x53C,
35 .cm_div_m6_dpll = CM_WKUP + 0x540,
38 const struct dpll_regs dpll_per_regs = {
39 .cm_clkmode_dpll = CM_WKUP + 0x5E0,
40 .cm_idlest_dpll = CM_WKUP + 0x5E4,
41 .cm_clksel_dpll = CM_WKUP + 0x5EC,
42 .cm_div_m2_dpll = CM_WKUP + 0x5F0,
45 const struct dpll_regs dpll_ddr_regs = {
46 .cm_clkmode_dpll = CM_WKUP + 0x5A0,
47 .cm_idlest_dpll = CM_WKUP + 0x5A4,
48 .cm_clksel_dpll = CM_WKUP + 0x5AC,
49 .cm_div_m2_dpll = CM_WKUP + 0x5B0,
50 .cm_div_m4_dpll = CM_WKUP + 0x5B8,
53 void setup_clocks_for_console(void)
55 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
57 /* Do not add any spl_debug prints in this function */
58 clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
59 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
60 CD_CLKCTRL_CLKTRCTRL_SHIFT);
63 clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
64 MODULE_CLKCTRL_MODULEMODE_MASK,
65 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
66 MODULE_CLKCTRL_MODULEMODE_SHIFT);
68 while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
69 (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
70 clkctrl = readl(&cmwkup->wkup_uart0ctrl);
71 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
72 MODULE_CLKCTRL_IDLEST_SHIFT;
76 void enable_basic_clocks(void)
78 u32 *const clk_domains[] = {
81 &cmper->l4lsclkstctrl,
83 &cmper->emifclkstctrl,
87 u32 *const clk_modules_explicit_en[] = {
91 &cmwkup->wkl4wkclkctrl,
92 &cmper->l3instrclkctrl,
94 &cmwkup->wkgpio0clkctrl,
95 &cmwkup->wkctrlclkctrl,
96 &cmper->timer2clkctrl,
101 &cmwkup->wkup_i2c0ctrl,
102 &cmper->gpio1clkctrl,
103 &cmper->gpio2clkctrl,
104 &cmper->gpio3clkctrl,
105 &cmper->gpio4clkctrl,
106 &cmper->gpio5clkctrl,
108 &cmper->cpgmac0clkctrl,
109 &cmper->emiffwclkctrl,
111 &cmper->otfaemifclkctrl,
117 do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
119 /* Select the Master osc clk as Timer2 clock source */
120 writel(0x1, &cmdpll->clktimer2clk);
122 /* For OPP100 the mac clock should be /5. */
123 writel(0x4, &cmdpll->clkselmacclk);
126 void rtc_only_enable_basic_clocks(void)
128 u32 *const clk_domains[] = {
129 &cmper->emifclkstctrl,
133 u32 *const clk_modules_explicit_en[] = {
134 &cmper->gpio5clkctrl,
135 &cmper->emiffwclkctrl,
137 &cmper->otfaemifclkctrl,
141 do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
143 /* Select the Master osc clk as Timer2 clock source */
144 writel(0x1, &cmdpll->clktimer2clk);
147 #ifdef CONFIG_TI_EDMA3
148 void enable_edma3_clocks(void)
150 u32 *const clk_domains_edma3[] = {
154 u32 *const clk_modules_explicit_en_edma3[] = {
156 &cmper->tptc0clkctrl,
160 do_enable_clocks(clk_domains_edma3,
161 clk_modules_explicit_en_edma3,
165 void disable_edma3_clocks(void)
167 u32 *const clk_domains_edma3[] = {
171 u32 *const clk_modules_disable_edma3[] = {
173 &cmper->tptc0clkctrl,
177 do_disable_clocks(clk_domains_edma3,
178 clk_modules_disable_edma3,
183 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
184 void enable_usb_clocks(int index)
187 u32 *usbphyocp2scpclkctrl = 0;
190 usbclkctrl = &cmper->usb0clkctrl;
191 usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl;
192 setbits_le32(&cmper->usb0clkctrl,
193 USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
194 setbits_le32(&cmwkup->usbphy0clkctrl,
195 USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
196 } else if (index == 1) {
197 usbclkctrl = &cmper->usb1clkctrl;
198 usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl;
199 setbits_le32(&cmper->usb1clkctrl,
200 USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
201 setbits_le32(&cmwkup->usbphy1clkctrl,
202 USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
205 u32 *const clk_domains_usb[] = {
209 u32 *const clk_modules_explicit_en_usb[] = {
211 usbphyocp2scpclkctrl,
215 do_enable_clocks(clk_domains_usb, clk_modules_explicit_en_usb, 1);
218 void disable_usb_clocks(int index)
221 u32 *usbphyocp2scpclkctrl = 0;
224 usbclkctrl = &cmper->usb0clkctrl;
225 usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl;
226 clrbits_le32(&cmper->usb0clkctrl,
227 USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
228 clrbits_le32(&cmwkup->usbphy0clkctrl,
229 USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
230 } else if (index == 1) {
231 usbclkctrl = &cmper->usb1clkctrl;
232 usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl;
233 clrbits_le32(&cmper->usb1clkctrl,
234 USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
235 clrbits_le32(&cmwkup->usbphy1clkctrl,
236 USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
239 u32 *const clk_domains_usb[] = {
243 u32 *const clk_modules_disable_usb[] = {
245 usbphyocp2scpclkctrl,
249 do_disable_clocks(clk_domains_usb, clk_modules_disable_usb, 1);