1 // SPDX-License-Identifier: GPL-2.0+
5 * Common board functions for AM33XX based boards
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
12 #include <debug_uart.h>
18 #include <omap3_spi.h>
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/hardware.h>
22 #include <asm/arch/omap.h>
23 #include <asm/arch/ddr_defs.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/i2c.h>
27 #if IS_ENABLED(CONFIG_TARGET_AM335X_GUARDIAN)
28 #include <asm/arch/mem-guardian.h>
30 #include <asm/arch/mem.h>
32 #include <asm/arch/mmc_host_def.h>
33 #include <asm/arch/sys_proto.h>
34 #include <asm/global_data.h>
38 #include <asm/omap_common.h>
42 #include <linux/delay.h>
43 #include <linux/errno.h>
44 #include <linux/compiler.h>
45 #include <linux/usb/ch9.h>
46 #include <linux/usb/gadget.h>
47 #include <linux/usb/musb.h>
48 #include <asm/omap_musb.h>
49 #include <asm/davinci_rtc.h>
51 #define AM43XX_EMIF_BASE 0x4C000000
52 #define AM43XX_SDRAM_CONFIG_OFFSET 0x8
53 #define AM43XX_SDRAM_TYPE_MASK 0xE0000000
54 #define AM43XX_SDRAM_TYPE_SHIFT 29
55 #define AM43XX_SDRAM_TYPE_DDR3 3
56 #define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC
57 #define AM43XX_RDWRLVLFULL_START 0x80000000
60 #if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
61 #define AM33XX_SPI0_BASE 0x48030000
62 #define AM33XX_SPI0_OFFSET (AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET)
65 DECLARE_GLOBAL_DATA_PTR;
69 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
73 /* dram_init must store complete ramsize in gd->ram_size */
74 gd->ram_size = get_ram_size(
75 (void *)CONFIG_SYS_SDRAM_BASE,
76 CONFIG_MAX_RAM_BANK_SIZE);
80 int dram_init_banksize(void)
82 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
83 gd->bd->bi_dram[0].size = gd->ram_size;
88 #if !CONFIG_IS_ENABLED(OF_CONTROL)
89 static const struct ns16550_plat am33xx_serial[] = {
90 { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
91 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
92 # ifdef CONFIG_SYS_NS16550_COM2
93 { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
94 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
95 # ifdef CONFIG_SYS_NS16550_COM3
96 { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
97 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
98 { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
99 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
100 { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
101 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
102 { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
103 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
108 U_BOOT_DRVINFOS(am33xx_uarts) = {
109 { "ns16550_serial", &am33xx_serial[0] },
110 # ifdef CONFIG_SYS_NS16550_COM2
111 { "ns16550_serial", &am33xx_serial[1] },
112 # ifdef CONFIG_SYS_NS16550_COM3
113 { "ns16550_serial", &am33xx_serial[2] },
114 { "ns16550_serial", &am33xx_serial[3] },
115 { "ns16550_serial", &am33xx_serial[4] },
116 { "ns16550_serial", &am33xx_serial[5] },
121 #if CONFIG_IS_ENABLED(DM_I2C)
122 static const struct omap_i2c_plat am33xx_i2c[] = {
123 { I2C_BASE1, 100000, OMAP_I2C_REV_V2},
124 { I2C_BASE2, 100000, OMAP_I2C_REV_V2},
125 { I2C_BASE3, 100000, OMAP_I2C_REV_V2},
128 U_BOOT_DRVINFOS(am33xx_i2c) = {
129 { "i2c_omap", &am33xx_i2c[0] },
130 { "i2c_omap", &am33xx_i2c[1] },
131 { "i2c_omap", &am33xx_i2c[2] },
135 #if CONFIG_IS_ENABLED(DM_GPIO)
136 static const struct omap_gpio_plat am33xx_gpio[] = {
137 { 0, AM33XX_GPIO0_BASE },
138 { 1, AM33XX_GPIO1_BASE },
139 { 2, AM33XX_GPIO2_BASE },
140 { 3, AM33XX_GPIO3_BASE },
142 { 4, AM33XX_GPIO4_BASE },
143 { 5, AM33XX_GPIO5_BASE },
147 U_BOOT_DRVINFOS(am33xx_gpios) = {
148 { "gpio_omap", &am33xx_gpio[0] },
149 { "gpio_omap", &am33xx_gpio[1] },
150 { "gpio_omap", &am33xx_gpio[2] },
151 { "gpio_omap", &am33xx_gpio[3] },
153 { "gpio_omap", &am33xx_gpio[4] },
154 { "gpio_omap", &am33xx_gpio[5] },
158 #if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
159 static const struct omap3_spi_plat omap3_spi_pdata = {
160 .regs = (struct mcspi *)AM33XX_SPI0_OFFSET,
161 .pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
164 U_BOOT_DRVINFO(am33xx_spi) = {
166 .plat = &omap3_spi_pdata,
171 #if !CONFIG_IS_ENABLED(DM_GPIO)
172 static const struct gpio_bank gpio_bank_am33xx[] = {
173 { (void *)AM33XX_GPIO0_BASE },
174 { (void *)AM33XX_GPIO1_BASE },
175 { (void *)AM33XX_GPIO2_BASE },
176 { (void *)AM33XX_GPIO3_BASE },
178 { (void *)AM33XX_GPIO4_BASE },
179 { (void *)AM33XX_GPIO5_BASE },
183 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
186 #if defined(CONFIG_MMC_OMAP_HS)
187 int cpu_mmc_init(struct bd_info *bis)
191 ret = omap_mmc_init(0, 0, 0, -1, -1);
195 return omap_mmc_init(1, 0, 0, -1, -1);
200 * RTC only with DDR in self-refresh mode magic value, checked against during
201 * boot to see if we have a valid config. This should be in sync with the value
202 * that will be in drivers/soc/ti/pm33xx.c.
204 #define RTC_MAGIC_VAL 0x8cd0
206 /* Board type field bit shift for RTC only with DDR in self-refresh mode */
207 #define RTC_BOARD_TYPE_SHIFT 16
209 /* AM33XX has two MUSB controllers which can be host or gadget */
210 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
211 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
212 (!CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL)) && \
213 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_MUSB_NEW))
215 static struct musb_hdrc_config musb_config = {
222 #if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL)
223 static struct ti_musb_plat usb0 = {
224 .base = (void *)USB0_OTG_BASE,
225 .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
227 .config = &musb_config,
229 .platform_ops = &musb_dsps_ops,
233 static struct ti_musb_plat usb1 = {
234 .base = (void *)USB1_OTG_BASE,
235 .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
237 .config = &musb_config,
239 .platform_ops = &musb_dsps_ops,
243 U_BOOT_DRVINFOS(am33xx_usbs) = {
244 #ifdef CONFIG_AM335X_USB0_PERIPHERAL
245 { "ti-musb-peripheral", &usb0 },
246 #elif defined(CONFIG_AM335X_USB0_HOST)
247 { "ti-musb-host", &usb0 },
249 #ifdef CONFIG_AM335X_USB1_PERIPHERAL
250 { "ti-musb-peripheral", &usb1 },
251 #elif defined(CONFIG_AM335X_USB1_HOST)
252 { "ti-musb-host", &usb1 },
256 int arch_misc_init(void)
261 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
263 /* USB 2.0 PHY Control */
264 #define CM_PHY_PWRDN (1 << 0)
265 #define CM_PHY_OTG_PWRDN (1 << 1)
266 #define OTGVDET_EN (1 << 19)
267 #define OTGSESSENDEN (1 << 20)
269 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
272 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
273 OTGVDET_EN | OTGSESSENDEN);
275 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
279 #ifdef CONFIG_AM335X_USB0
280 static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
282 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
285 struct omap_musb_board_data otg0_board_data = {
286 .set_phy_power = am33xx_otg0_set_phy_power,
289 static struct musb_hdrc_platform_data otg0_plat = {
290 .mode = CONFIG_AM335X_USB0_MODE,
291 .config = &musb_config,
293 .platform_ops = &musb_dsps_ops,
294 .board_data = &otg0_board_data,
298 #ifdef CONFIG_AM335X_USB1
299 static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
301 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
304 struct omap_musb_board_data otg1_board_data = {
305 .set_phy_power = am33xx_otg1_set_phy_power,
308 static struct musb_hdrc_platform_data otg1_plat = {
309 .mode = CONFIG_AM335X_USB1_MODE,
310 .config = &musb_config,
312 .platform_ops = &musb_dsps_ops,
313 .board_data = &otg1_board_data,
317 int arch_misc_init(void)
319 #ifdef CONFIG_AM335X_USB0
320 musb_register(&otg0_plat, &otg0_board_data,
321 (void *)USB0_OTG_BASE);
323 #ifdef CONFIG_AM335X_USB1
324 musb_register(&otg1_plat, &otg1_board_data,
325 (void *)USB1_OTG_BASE);
331 #else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
333 int arch_misc_init(void)
338 ret = uclass_first_device(UCLASS_MISC, &dev);
342 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
343 ret = usb_ether_init();
345 pr_err("USB ether init failed\n");
353 #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
355 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
357 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
358 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
359 static void rtc32k_unlock(struct davinci_rtc *rtc)
362 * Unlock the RTC's registers. For more details please see the
363 * RTC_SS section of the TRM. In order to unlock we need to
364 * write these specific values (keys) in this order.
366 writel(RTC_KICK0R_WE, &rtc->kick0r);
367 writel(RTC_KICK1R_WE, &rtc->kick1r);
371 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
373 * Write contents of the RTC_SCRATCH1 register based on board type
374 * Two things are passed
375 * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
376 * control gets to kernel, kernel reads the scratchpad register and gets to
377 * know that bootloader has rtc_only support.
379 * Second important thing is the board type (16:31). This is needed in the
380 * rtc_only boot where in we want to avoid costly i2c reads to eeprom to
381 * identify the board type and we go ahead and copy the board strings to
384 void update_rtc_magic(void)
386 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
387 u32 magic = RTC_MAGIC_VAL;
389 magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
394 writel(magic, &rtc->scratch1);
399 * In the case of non-SPL based booting we'll want to call these
400 * functions a tiny bit later as it will require gd to be set and cleared
401 * and that's not true in s_init in this case so we cannot do it there.
403 int board_early_init_f(void)
407 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
414 * This function is the place to do per-board things such as ramp up the
415 * MPU clock frequency.
417 __weak void am33xx_spl_board_init(void)
421 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
422 static void rtc32k_enable(void)
424 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
428 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
429 writel((1 << 3) | (1 << 6), &rtc->osc);
433 static void uart_soft_reset(void)
435 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
438 regval = readl(&uart_base->uartsyscfg);
439 regval |= UART_RESET;
440 writel(regval, &uart_base->uartsyscfg);
441 while ((readl(&uart_base->uartsyssts) &
442 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
445 /* Disable smart idle */
446 regval = readl(&uart_base->uartsyscfg);
447 regval |= UART_SMART_IDLE_EN;
448 writel(regval, &uart_base->uartsyscfg);
451 static void watchdog_disable(void)
453 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
455 writel(0xAAAA, &wdtimer->wdtwspr);
456 while (readl(&wdtimer->wdtwwps) != 0x0)
458 writel(0x5555, &wdtimer->wdtwspr);
459 while (readl(&wdtimer->wdtwwps) != 0x0)
463 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
465 * Check if we are executing rtc-only + DDR mode, and resume from it if needed
467 static void rtc_only(void)
469 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
470 struct prm_device_inst *prm_device =
471 (struct prm_device_inst *)PRM_DEVICE_INST;
474 void (*resume_func)(void);
476 scratch1 = readl(&rtc->scratch1);
479 * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
480 * written to this register when we want to wake up from RTC only
481 * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:
482 * bits 0-15: RTC_MAGIC_VAL
483 * bits 16-31: board type (needed for sdram_init)
485 if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
490 /* Clear RTC magic */
491 writel(0, &rtc->scratch1);
494 * Update board type based on value stored on RTC_SCRATCH1, this
495 * is done so that we don't need to read the board type from eeprom
496 * over i2c bus which is expensive
498 rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
501 * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we
502 * are resuming from self-refresh. This avoids an unnecessary re-init
503 * of the DDR. The re-init takes time and we would need to wait for
504 * it to complete before accessing DDR to avoid L3 NOC errors.
506 writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);
508 rtc_only_prcm_init();
511 /* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */
512 /* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */
513 sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET);
515 sdrc &= AM43XX_SDRAM_TYPE_MASK;
516 sdrc >>= AM43XX_SDRAM_TYPE_SHIFT;
518 if (sdrc == AM43XX_SDRAM_TYPE_DDR3) {
519 writel(AM43XX_RDWRLVLFULL_START,
521 AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
525 sdrc = readl(AM43XX_EMIF_BASE +
526 AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
527 if (sdrc == AM43XX_RDWRLVLFULL_START)
531 resume_func = (void *)readl(&rtc->scratch0);
539 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
544 void early_system_init(void)
547 * The ROM will only have set up sufficient pinmux to allow for the
548 * first 4KiB NOR to be read, we must finish doing what we know of
549 * the NOR mux in this space in order to continue.
551 #ifdef CONFIG_NOR_BOOT
552 enable_norboot_pin_mux();
556 setup_early_clocks();
558 #ifdef CONFIG_SPL_BUILD
560 * Save the boot parameters passed from romcode.
561 * We cannot delay the saving further than this,
562 * to prevent overwrites.
564 save_omap_boot_params();
566 #ifdef CONFIG_DEBUG_UART_OMAP
570 #ifdef CONFIG_SPL_BUILD
574 #ifdef CONFIG_TI_I2C_BOARD_DETECT
578 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
579 /* Enable RTC32K clock */
584 #ifdef CONFIG_SPL_BUILD
585 void board_init_f(ulong dummy)
589 board_early_init_f();
591 /* dram_init must store complete ramsize in gd->ram_size */
592 gd->ram_size = get_ram_size(
593 (void *)CONFIG_SYS_SDRAM_BASE,
594 CONFIG_MAX_RAM_BANK_SIZE);
600 static int am33xx_dm_post_init(void *ctx, struct event *event)
603 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
608 EVENT_SPY(EVT_DM_POST_INIT, am33xx_dm_post_init);