1 // SPDX-License-Identifier: GPL-2.0+
5 * Common board functions for AM33XX based boards
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
12 #include <debug_uart.h>
17 #include <omap3_spi.h>
19 #include <asm/arch/cpu.h>
20 #include <asm/arch/hardware.h>
21 #include <asm/arch/omap.h>
22 #include <asm/arch/ddr_defs.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/i2c.h>
26 #include <asm/arch/mem.h>
27 #include <asm/arch/mmc_host_def.h>
28 #include <asm/arch/sys_proto.h>
32 #include <asm/omap_common.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/compiler.h>
39 #include <linux/usb/ch9.h>
40 #include <linux/usb/gadget.h>
41 #include <linux/usb/musb.h>
42 #include <asm/omap_musb.h>
43 #include <asm/davinci_rtc.h>
45 #define AM43XX_EMIF_BASE 0x4C000000
46 #define AM43XX_SDRAM_CONFIG_OFFSET 0x8
47 #define AM43XX_SDRAM_TYPE_MASK 0xE0000000
48 #define AM43XX_SDRAM_TYPE_SHIFT 29
49 #define AM43XX_SDRAM_TYPE_DDR3 3
50 #define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC
51 #define AM43XX_RDWRLVLFULL_START 0x80000000
54 #if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
55 #define AM33XX_SPI0_BASE 0x48030000
56 #define AM33XX_SPI0_OFFSET (AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET)
59 DECLARE_GLOBAL_DATA_PTR;
63 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
67 /* dram_init must store complete ramsize in gd->ram_size */
68 gd->ram_size = get_ram_size(
69 (void *)CONFIG_SYS_SDRAM_BASE,
70 CONFIG_MAX_RAM_BANK_SIZE);
74 int dram_init_banksize(void)
76 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
77 gd->bd->bi_dram[0].size = gd->ram_size;
82 #if !CONFIG_IS_ENABLED(OF_CONTROL)
83 static const struct ns16550_plat am33xx_serial[] = {
84 { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
85 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
86 # ifdef CONFIG_SYS_NS16550_COM2
87 { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
88 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
89 # ifdef CONFIG_SYS_NS16550_COM3
90 { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
91 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
92 { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
93 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
94 { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
95 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
96 { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
97 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
102 U_BOOT_DEVICES(am33xx_uarts) = {
103 { "ns16550_serial", &am33xx_serial[0] },
104 # ifdef CONFIG_SYS_NS16550_COM2
105 { "ns16550_serial", &am33xx_serial[1] },
106 # ifdef CONFIG_SYS_NS16550_COM3
107 { "ns16550_serial", &am33xx_serial[2] },
108 { "ns16550_serial", &am33xx_serial[3] },
109 { "ns16550_serial", &am33xx_serial[4] },
110 { "ns16550_serial", &am33xx_serial[5] },
116 static const struct omap_i2c_plat am33xx_i2c[] = {
117 { I2C_BASE1, 100000, OMAP_I2C_REV_V2},
118 { I2C_BASE2, 100000, OMAP_I2C_REV_V2},
119 { I2C_BASE3, 100000, OMAP_I2C_REV_V2},
122 U_BOOT_DEVICES(am33xx_i2c) = {
123 { "i2c_omap", &am33xx_i2c[0] },
124 { "i2c_omap", &am33xx_i2c[1] },
125 { "i2c_omap", &am33xx_i2c[2] },
129 #if CONFIG_IS_ENABLED(DM_GPIO)
130 static const struct omap_gpio_plat am33xx_gpio[] = {
131 { 0, AM33XX_GPIO0_BASE },
132 { 1, AM33XX_GPIO1_BASE },
133 { 2, AM33XX_GPIO2_BASE },
134 { 3, AM33XX_GPIO3_BASE },
136 { 4, AM33XX_GPIO4_BASE },
137 { 5, AM33XX_GPIO5_BASE },
141 U_BOOT_DEVICES(am33xx_gpios) = {
142 { "gpio_omap", &am33xx_gpio[0] },
143 { "gpio_omap", &am33xx_gpio[1] },
144 { "gpio_omap", &am33xx_gpio[2] },
145 { "gpio_omap", &am33xx_gpio[3] },
147 { "gpio_omap", &am33xx_gpio[4] },
148 { "gpio_omap", &am33xx_gpio[5] },
152 #if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
153 static const struct omap3_spi_plat omap3_spi_pdata = {
154 .regs = (struct mcspi *)AM33XX_SPI0_OFFSET,
155 .pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
158 U_BOOT_DEVICE(am33xx_spi) = {
160 .plat = &omap3_spi_pdata,
165 #if !CONFIG_IS_ENABLED(DM_GPIO)
166 static const struct gpio_bank gpio_bank_am33xx[] = {
167 { (void *)AM33XX_GPIO0_BASE },
168 { (void *)AM33XX_GPIO1_BASE },
169 { (void *)AM33XX_GPIO2_BASE },
170 { (void *)AM33XX_GPIO3_BASE },
172 { (void *)AM33XX_GPIO4_BASE },
173 { (void *)AM33XX_GPIO5_BASE },
177 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
180 #if defined(CONFIG_MMC_OMAP_HS)
181 int cpu_mmc_init(struct bd_info *bis)
185 ret = omap_mmc_init(0, 0, 0, -1, -1);
189 return omap_mmc_init(1, 0, 0, -1, -1);
194 * RTC only with DDR in self-refresh mode magic value, checked against during
195 * boot to see if we have a valid config. This should be in sync with the value
196 * that will be in drivers/soc/ti/pm33xx.c.
198 #define RTC_MAGIC_VAL 0x8cd0
200 /* Board type field bit shift for RTC only with DDR in self-refresh mode */
201 #define RTC_BOARD_TYPE_SHIFT 16
203 /* AM33XX has two MUSB controllers which can be host or gadget */
204 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
205 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
206 (!CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL)) && \
207 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_MUSB_NEW_SUPPORT))
209 static struct musb_hdrc_config musb_config = {
216 #if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL)
217 static struct ti_musb_plat usb0 = {
218 .base = (void *)USB0_OTG_BASE,
219 .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
221 .config = &musb_config,
223 .platform_ops = &musb_dsps_ops,
227 static struct ti_musb_plat usb1 = {
228 .base = (void *)USB1_OTG_BASE,
229 .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
231 .config = &musb_config,
233 .platform_ops = &musb_dsps_ops,
237 U_BOOT_DEVICES(am33xx_usbs) = {
238 #if CONFIG_AM335X_USB0_MODE == MUSB_PERIPHERAL
239 { "ti-musb-peripheral", &usb0 },
240 #elif CONFIG_AM335X_USB0_MODE == MUSB_HOST
241 { "ti-musb-host", &usb0 },
243 #if CONFIG_AM335X_USB1_MODE == MUSB_PERIPHERAL
244 { "ti-musb-peripheral", &usb1 },
245 #elif CONFIG_AM335X_USB1_MODE == MUSB_HOST
246 { "ti-musb-host", &usb1 },
250 int arch_misc_init(void)
255 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
257 /* USB 2.0 PHY Control */
258 #define CM_PHY_PWRDN (1 << 0)
259 #define CM_PHY_OTG_PWRDN (1 << 1)
260 #define OTGVDET_EN (1 << 19)
261 #define OTGSESSENDEN (1 << 20)
263 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
266 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
267 OTGVDET_EN | OTGSESSENDEN);
269 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
273 #ifdef CONFIG_AM335X_USB0
274 static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
276 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
279 struct omap_musb_board_data otg0_board_data = {
280 .set_phy_power = am33xx_otg0_set_phy_power,
283 static struct musb_hdrc_platform_data otg0_plat = {
284 .mode = CONFIG_AM335X_USB0_MODE,
285 .config = &musb_config,
287 .platform_ops = &musb_dsps_ops,
288 .board_data = &otg0_board_data,
292 #ifdef CONFIG_AM335X_USB1
293 static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
295 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
298 struct omap_musb_board_data otg1_board_data = {
299 .set_phy_power = am33xx_otg1_set_phy_power,
302 static struct musb_hdrc_platform_data otg1_plat = {
303 .mode = CONFIG_AM335X_USB1_MODE,
304 .config = &musb_config,
306 .platform_ops = &musb_dsps_ops,
307 .board_data = &otg1_board_data,
311 int arch_misc_init(void)
313 #ifdef CONFIG_AM335X_USB0
314 musb_register(&otg0_plat, &otg0_board_data,
315 (void *)USB0_OTG_BASE);
317 #ifdef CONFIG_AM335X_USB1
318 musb_register(&otg1_plat, &otg1_board_data,
319 (void *)USB1_OTG_BASE);
325 #else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
327 int arch_misc_init(void)
332 ret = uclass_first_device(UCLASS_MISC, &dev);
336 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
337 ret = usb_ether_init();
339 pr_err("USB ether init failed\n");
347 #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
349 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
351 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
352 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
353 static void rtc32k_unlock(struct davinci_rtc *rtc)
356 * Unlock the RTC's registers. For more details please see the
357 * RTC_SS section of the TRM. In order to unlock we need to
358 * write these specific values (keys) in this order.
360 writel(RTC_KICK0R_WE, &rtc->kick0r);
361 writel(RTC_KICK1R_WE, &rtc->kick1r);
365 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
367 * Write contents of the RTC_SCRATCH1 register based on board type
368 * Two things are passed
369 * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
370 * control gets to kernel, kernel reads the scratchpad register and gets to
371 * know that bootloader has rtc_only support.
373 * Second important thing is the board type (16:31). This is needed in the
374 * rtc_only boot where in we want to avoid costly i2c reads to eeprom to
375 * identify the board type and we go ahead and copy the board strings to
378 void update_rtc_magic(void)
380 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
381 u32 magic = RTC_MAGIC_VAL;
383 magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
388 writel(magic, &rtc->scratch1);
393 * In the case of non-SPL based booting we'll want to call these
394 * functions a tiny bit later as it will require gd to be set and cleared
395 * and that's not true in s_init in this case so we cannot do it there.
397 int board_early_init_f(void)
401 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
408 * This function is the place to do per-board things such as ramp up the
409 * MPU clock frequency.
411 __weak void am33xx_spl_board_init(void)
415 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
416 static void rtc32k_enable(void)
418 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
422 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
423 writel((1 << 3) | (1 << 6), &rtc->osc);
427 static void uart_soft_reset(void)
429 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
432 regval = readl(&uart_base->uartsyscfg);
433 regval |= UART_RESET;
434 writel(regval, &uart_base->uartsyscfg);
435 while ((readl(&uart_base->uartsyssts) &
436 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
439 /* Disable smart idle */
440 regval = readl(&uart_base->uartsyscfg);
441 regval |= UART_SMART_IDLE_EN;
442 writel(regval, &uart_base->uartsyscfg);
445 static void watchdog_disable(void)
447 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
449 writel(0xAAAA, &wdtimer->wdtwspr);
450 while (readl(&wdtimer->wdtwwps) != 0x0)
452 writel(0x5555, &wdtimer->wdtwspr);
453 while (readl(&wdtimer->wdtwwps) != 0x0)
457 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
459 * Check if we are executing rtc-only + DDR mode, and resume from it if needed
461 static void rtc_only(void)
463 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
464 struct prm_device_inst *prm_device =
465 (struct prm_device_inst *)PRM_DEVICE_INST;
468 void (*resume_func)(void);
470 scratch1 = readl(&rtc->scratch1);
473 * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
474 * written to this register when we want to wake up from RTC only
475 * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:
476 * bits 0-15: RTC_MAGIC_VAL
477 * bits 16-31: board type (needed for sdram_init)
479 if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
484 /* Clear RTC magic */
485 writel(0, &rtc->scratch1);
488 * Update board type based on value stored on RTC_SCRATCH1, this
489 * is done so that we don't need to read the board type from eeprom
490 * over i2c bus which is expensive
492 rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
495 * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we
496 * are resuming from self-refresh. This avoids an unnecessary re-init
497 * of the DDR. The re-init takes time and we would need to wait for
498 * it to complete before accessing DDR to avoid L3 NOC errors.
500 writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);
502 rtc_only_prcm_init();
505 /* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */
506 /* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */
507 sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET);
509 sdrc &= AM43XX_SDRAM_TYPE_MASK;
510 sdrc >>= AM43XX_SDRAM_TYPE_SHIFT;
512 if (sdrc == AM43XX_SDRAM_TYPE_DDR3) {
513 writel(AM43XX_RDWRLVLFULL_START,
515 AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
519 sdrc = readl(AM43XX_EMIF_BASE +
520 AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
521 if (sdrc == AM43XX_RDWRLVLFULL_START)
525 resume_func = (void *)readl(&rtc->scratch0);
533 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
538 void early_system_init(void)
541 * The ROM will only have set up sufficient pinmux to allow for the
542 * first 4KiB NOR to be read, we must finish doing what we know of
543 * the NOR mux in this space in order to continue.
545 #ifdef CONFIG_NOR_BOOT
546 enable_norboot_pin_mux();
550 setup_early_clocks();
552 #ifdef CONFIG_SPL_BUILD
554 * Save the boot parameters passed from romcode.
555 * We cannot delay the saving further than this,
556 * to prevent overwrites.
558 save_omap_boot_params();
560 #ifdef CONFIG_DEBUG_UART_OMAP
564 #ifdef CONFIG_SPL_BUILD
568 #ifdef CONFIG_TI_I2C_BOARD_DETECT
572 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
573 /* Enable RTC32K clock */
578 #ifdef CONFIG_SPL_BUILD
579 void board_init_f(ulong dummy)
583 board_early_init_f();
585 /* dram_init must store complete ramsize in gd->ram_size */
586 gd->ram_size = get_ram_size(
587 (void *)CONFIG_SYS_SDRAM_BASE,
588 CONFIG_MAX_RAM_BANK_SIZE);
594 int arch_cpu_init_dm(void)
597 #ifndef CONFIG_SKIP_LOWLEVEL_INIT