4 * Common board functions for AM33XX based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <debug_uart.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/hardware.h>
19 #include <asm/arch/omap.h>
20 #include <asm/arch/ddr_defs.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/mem.h>
24 #include <asm/arch/mmc_host_def.h>
25 #include <asm/arch/sys_proto.h>
32 #include <linux/errno.h>
33 #include <linux/compiler.h>
34 #include <linux/usb/ch9.h>
35 #include <linux/usb/gadget.h>
36 #include <linux/usb/musb.h>
37 #include <asm/omap_musb.h>
38 #include <asm/davinci_rtc.h>
40 DECLARE_GLOBAL_DATA_PTR;
42 #if !CONFIG_IS_ENABLED(OF_CONTROL)
43 static const struct ns16550_platdata am33xx_serial[] = {
44 { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
45 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
46 # ifdef CONFIG_SYS_NS16550_COM2
47 { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
48 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
49 # ifdef CONFIG_SYS_NS16550_COM3
50 { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
51 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
52 { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
53 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
54 { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
55 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
56 { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
57 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
62 U_BOOT_DEVICES(am33xx_uarts) = {
63 { "ns16550_serial", &am33xx_serial[0] },
64 # ifdef CONFIG_SYS_NS16550_COM2
65 { "ns16550_serial", &am33xx_serial[1] },
66 # ifdef CONFIG_SYS_NS16550_COM3
67 { "ns16550_serial", &am33xx_serial[2] },
68 { "ns16550_serial", &am33xx_serial[3] },
69 { "ns16550_serial", &am33xx_serial[4] },
70 { "ns16550_serial", &am33xx_serial[5] },
76 static const struct omap_gpio_platdata am33xx_gpio[] = {
77 { 0, AM33XX_GPIO0_BASE },
78 { 1, AM33XX_GPIO1_BASE },
79 { 2, AM33XX_GPIO2_BASE },
80 { 3, AM33XX_GPIO3_BASE },
82 { 4, AM33XX_GPIO4_BASE },
83 { 5, AM33XX_GPIO5_BASE },
87 U_BOOT_DEVICES(am33xx_gpios) = {
88 { "gpio_omap", &am33xx_gpio[0] },
89 { "gpio_omap", &am33xx_gpio[1] },
90 { "gpio_omap", &am33xx_gpio[2] },
91 { "gpio_omap", &am33xx_gpio[3] },
93 { "gpio_omap", &am33xx_gpio[4] },
94 { "gpio_omap", &am33xx_gpio[5] },
100 #ifndef CONFIG_DM_GPIO
101 static const struct gpio_bank gpio_bank_am33xx[] = {
102 { (void *)AM33XX_GPIO0_BASE },
103 { (void *)AM33XX_GPIO1_BASE },
104 { (void *)AM33XX_GPIO2_BASE },
105 { (void *)AM33XX_GPIO3_BASE },
107 { (void *)AM33XX_GPIO4_BASE },
108 { (void *)AM33XX_GPIO5_BASE },
112 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
115 #if defined(CONFIG_MMC_OMAP_HS)
116 int cpu_mmc_init(bd_t *bis)
120 ret = omap_mmc_init(0, 0, 0, -1, -1);
124 return omap_mmc_init(1, 0, 0, -1, -1);
128 /* AM33XX has two MUSB controllers which can be host or gadget */
129 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
130 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
131 (!defined(CONFIG_DM_USB))
132 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
134 /* USB 2.0 PHY Control */
135 #define CM_PHY_PWRDN (1 << 0)
136 #define CM_PHY_OTG_PWRDN (1 << 1)
137 #define OTGVDET_EN (1 << 19)
138 #define OTGSESSENDEN (1 << 20)
140 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
143 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
144 OTGVDET_EN | OTGSESSENDEN);
146 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
150 static struct musb_hdrc_config musb_config = {
157 #ifdef CONFIG_AM335X_USB0
158 static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
160 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
163 struct omap_musb_board_data otg0_board_data = {
164 .set_phy_power = am33xx_otg0_set_phy_power,
167 static struct musb_hdrc_platform_data otg0_plat = {
168 .mode = CONFIG_AM335X_USB0_MODE,
169 .config = &musb_config,
171 .platform_ops = &musb_dsps_ops,
172 .board_data = &otg0_board_data,
176 #ifdef CONFIG_AM335X_USB1
177 static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
179 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
182 struct omap_musb_board_data otg1_board_data = {
183 .set_phy_power = am33xx_otg1_set_phy_power,
186 static struct musb_hdrc_platform_data otg1_plat = {
187 .mode = CONFIG_AM335X_USB1_MODE,
188 .config = &musb_config,
190 .platform_ops = &musb_dsps_ops,
191 .board_data = &otg1_board_data,
196 int arch_misc_init(void)
198 #ifndef CONFIG_DM_USB
199 #ifdef CONFIG_AM335X_USB0
200 musb_register(&otg0_plat, &otg0_board_data,
201 (void *)USB0_OTG_BASE);
203 #ifdef CONFIG_AM335X_USB1
204 musb_register(&otg1_plat, &otg1_board_data,
205 (void *)USB1_OTG_BASE);
211 ret = uclass_first_device(UCLASS_MISC, &dev);
215 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
216 ret = usb_ether_init();
218 error("USB ether init failed\n");
226 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
228 * In the case of non-SPL based booting we'll want to call these
229 * functions a tiny bit later as it will require gd to be set and cleared
230 * and that's not true in s_init in this case so we cannot do it there.
232 int board_early_init_f(void)
241 * This function is the place to do per-board things such as ramp up the
242 * MPU clock frequency.
244 __weak void am33xx_spl_board_init(void)
248 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
249 static void rtc32k_enable(void)
251 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
254 * Unlock the RTC's registers. For more details please see the
255 * RTC_SS section of the TRM. In order to unlock we need to
256 * write these specific values (keys) in this order.
258 writel(RTC_KICK0R_WE, &rtc->kick0r);
259 writel(RTC_KICK1R_WE, &rtc->kick1r);
261 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
262 writel((1 << 3) | (1 << 6), &rtc->osc);
266 static void uart_soft_reset(void)
268 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
271 regval = readl(&uart_base->uartsyscfg);
272 regval |= UART_RESET;
273 writel(regval, &uart_base->uartsyscfg);
274 while ((readl(&uart_base->uartsyssts) &
275 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
278 /* Disable smart idle */
279 regval = readl(&uart_base->uartsyscfg);
280 regval |= UART_SMART_IDLE_EN;
281 writel(regval, &uart_base->uartsyscfg);
284 static void watchdog_disable(void)
286 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
288 writel(0xAAAA, &wdtimer->wdtwspr);
289 while (readl(&wdtimer->wdtwwps) != 0x0)
291 writel(0x5555, &wdtimer->wdtwspr);
292 while (readl(&wdtimer->wdtwwps) != 0x0)
300 void early_system_init(void)
303 * The ROM will only have set up sufficient pinmux to allow for the
304 * first 4KiB NOR to be read, we must finish doing what we know of
305 * the NOR mux in this space in order to continue.
307 #ifdef CONFIG_NOR_BOOT
308 enable_norboot_pin_mux();
312 setup_early_clocks();
314 #ifdef CONFIG_DEBUG_UART_OMAP
317 #ifdef CONFIG_TI_I2C_BOARD_DETECT
320 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
321 /* Enable RTC32K clock */
326 #ifdef CONFIG_SPL_BUILD
327 void board_init_f(ulong dummy)
330 board_early_init_f();
332 /* dram_init must store complete ramsize in gd->ram_size */
333 gd->ram_size = get_ram_size(
334 (void *)CONFIG_SYS_SDRAM_BASE,
335 CONFIG_MAX_RAM_BANK_SIZE);
341 int arch_cpu_init_dm(void)
343 #ifndef CONFIG_SKIP_LOWLEVEL_INIT