arch/arm/mach-octeontx2/cpu.c

   1 // SPDX-License-Identifier:    GPL-2.0
   2 /*
   3  * Copyright (C) 2018 Marvell International Ltd.
   4  *
   5  * https://spdx.org/licenses
   6  */
   7
   8 #include <common.h>
   9 #include <asm/armv8/mmu.h>
  10 #include <asm/global_data.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/board.h>
  13
  14 DECLARE_GLOBAL_DATA_PTR;
  15
  16 #define OTX2_MEM_MAP_USED 4
  17
  18 /* +1 is end of list which needs to be empty */
  19 #define OTX2_MEM_MAP_MAX (OTX2_MEM_MAP_USED + CONFIG_NR_DRAM_BANKS + 1)
  20
  21 static struct mm_region otx2_mem_map[OTX2_MEM_MAP_MAX] = {
  22         {
  23                 .virt = 0x800000000000UL,
  24                 .phys = 0x800000000000UL,
  25                 .size = 0x40000000000UL,
  26                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  27                          PTE_BLOCK_NON_SHARE
  28         }, {
  29                 .virt = 0x840000000000UL,
  30                 .phys = 0x840000000000UL,
  31                 .size = 0x40000000000UL,
  32                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  33                          PTE_BLOCK_NON_SHARE
  34         }, {
  35                 .virt = 0x880000000000UL,
  36                 .phys = 0x880000000000UL,
  37                 .size = 0x40000000000UL,
  38                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  39                          PTE_BLOCK_NON_SHARE
  40         }, {
  41                 .virt = 0x8c0000000000UL,
  42                 .phys = 0x8c0000000000UL,
  43                 .size = 0x40000000000UL,
  44                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  45                          PTE_BLOCK_NON_SHARE
  46         }
  47 };
  48
  49 struct mm_region *mem_map = otx2_mem_map;
  50
  51 void mem_map_fill(void)
  52 {
  53         int banks = OTX2_MEM_MAP_USED;
  54         u32 dram_start = CONFIG_SYS_TEXT_BASE;
  55
  56         for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  57                 otx2_mem_map[banks].virt = dram_start;
  58                 otx2_mem_map[banks].phys = dram_start;
  59                 otx2_mem_map[banks].size = gd->ram_size;
  60                 otx2_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  61                                             PTE_BLOCK_NON_SHARE;
  62                 banks = banks + 1;
  63         }
  64 }
  65
  66 u64 get_page_table_size(void)
  67 {
  68         return 0x80000;
  69 }
  70
  71 void reset_cpu(void)
  72 {
  73 }