arch/arm/mach-octeontx2/cpu.c

   1 // SPDX-License-Identifier:    GPL-2.0
   2 /*
   3  * Copyright (C) 2018 Marvell International Ltd.
   4  *
   5  * https://spdx.org/licenses
   6  */
   7
   8 #include <common.h>
   9 #include <asm/armv8/mmu.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/board.h>
  12
  13 DECLARE_GLOBAL_DATA_PTR;
  14
  15 #define OTX2_MEM_MAP_USED 4
  16
  17 /* +1 is end of list which needs to be empty */
  18 #define OTX2_MEM_MAP_MAX (OTX2_MEM_MAP_USED + CONFIG_NR_DRAM_BANKS + 1)
  19
  20 static struct mm_region otx2_mem_map[OTX2_MEM_MAP_MAX] = {
  21         {
  22                 .virt = 0x800000000000UL,
  23                 .phys = 0x800000000000UL,
  24                 .size = 0x40000000000UL,
  25                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  26                          PTE_BLOCK_NON_SHARE
  27         }, {
  28                 .virt = 0x840000000000UL,
  29                 .phys = 0x840000000000UL,
  30                 .size = 0x40000000000UL,
  31                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  32                          PTE_BLOCK_NON_SHARE
  33         }, {
  34                 .virt = 0x880000000000UL,
  35                 .phys = 0x880000000000UL,
  36                 .size = 0x40000000000UL,
  37                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  38                          PTE_BLOCK_NON_SHARE
  39         }, {
  40                 .virt = 0x8c0000000000UL,
  41                 .phys = 0x8c0000000000UL,
  42                 .size = 0x40000000000UL,
  43                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  44                          PTE_BLOCK_NON_SHARE
  45         }
  46 };
  47
  48 struct mm_region *mem_map = otx2_mem_map;
  49
  50 void mem_map_fill(void)
  51 {
  52         int banks = OTX2_MEM_MAP_USED;
  53         u32 dram_start = CONFIG_SYS_TEXT_BASE;
  54
  55         for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  56                 otx2_mem_map[banks].virt = dram_start;
  57                 otx2_mem_map[banks].phys = dram_start;
  58                 otx2_mem_map[banks].size = gd->ram_size;
  59                 otx2_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  60                                             PTE_BLOCK_NON_SHARE;
  61                 banks = banks + 1;
  62         }
  63 }
  64
  65 u64 get_page_table_size(void)
  66 {
  67         return 0x80000;
  68 }
  69
  70 void reset_cpu(ulong addr)
  71 {
  72 }