2 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/i2c.h>
16 #include <linux/gpio.h>
17 #include <linux/delay.h>
19 #include <linux/input.h>
20 #include <linux/spi/flash.h>
21 #include <linux/spi/spi.h>
23 #include <mach/common.h>
24 #include <mach/hardware.h>
25 #include <mach/iomux-mx51.h>
28 #include <asm/setup.h>
29 #include <asm/mach-types.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/time.h>
33 #include "devices-imx51.h"
35 #include "cpu_op-mx51.h"
37 #define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7)
38 #define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27)
39 #define BABBAGE_USB_PHY_RESET IMX_GPIO_NR(2, 5)
40 #define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14)
41 #define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21)
42 #define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24)
43 #define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25)
44 #define BABBAGE_SD1_CD IMX_GPIO_NR(1, 0)
45 #define BABBAGE_SD1_WP IMX_GPIO_NR(1, 1)
46 #define BABBAGE_SD2_CD IMX_GPIO_NR(1, 6)
47 #define BABBAGE_SD2_WP IMX_GPIO_NR(1, 5)
50 #define MX51_USB_CTRL_1_OFFSET 0x10
51 #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
53 #define MX51_USB_PLLDIV_12_MHZ 0x00
54 #define MX51_USB_PLL_DIV_19_2_MHZ 0x01
55 #define MX51_USB_PLL_DIV_24_MHZ 0x02
57 static struct gpio_keys_button babbage_buttons[] = {
59 .gpio = BABBAGE_POWER_KEY,
67 static const struct gpio_keys_platform_data imx_button_data __initconst = {
68 .buttons = babbage_buttons,
69 .nbuttons = ARRAY_SIZE(babbage_buttons),
72 static iomux_v3_cfg_t mx51babbage_pads[] = {
74 MX51_PAD_UART1_RXD__UART1_RXD,
75 MX51_PAD_UART1_TXD__UART1_TXD,
76 MX51_PAD_UART1_RTS__UART1_RTS,
77 MX51_PAD_UART1_CTS__UART1_CTS,
80 MX51_PAD_UART2_RXD__UART2_RXD,
81 MX51_PAD_UART2_TXD__UART2_TXD,
84 MX51_PAD_EIM_D25__UART3_RXD,
85 MX51_PAD_EIM_D26__UART3_TXD,
86 MX51_PAD_EIM_D27__UART3_RTS,
87 MX51_PAD_EIM_D24__UART3_CTS,
90 MX51_PAD_EIM_D16__I2C1_SDA,
91 MX51_PAD_EIM_D19__I2C1_SCL,
94 MX51_PAD_KEY_COL4__I2C2_SCL,
95 MX51_PAD_KEY_COL5__I2C2_SDA,
98 MX51_PAD_I2C1_CLK__I2C1_CLK,
99 MX51_PAD_I2C1_DAT__I2C1_DAT,
102 MX51_PAD_USBH1_CLK__USBH1_CLK,
103 MX51_PAD_USBH1_DIR__USBH1_DIR,
104 MX51_PAD_USBH1_NXT__USBH1_NXT,
105 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
106 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
107 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
108 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
109 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
110 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
111 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
112 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
114 /* USB HUB reset line*/
115 MX51_PAD_GPIO1_7__GPIO1_7,
117 /* USB PHY reset line */
118 MX51_PAD_EIM_D21__GPIO2_5,
121 MX51_PAD_EIM_EB2__FEC_MDIO,
122 MX51_PAD_EIM_EB3__FEC_RDATA1,
123 MX51_PAD_EIM_CS2__FEC_RDATA2,
124 MX51_PAD_EIM_CS3__FEC_RDATA3,
125 MX51_PAD_EIM_CS4__FEC_RX_ER,
126 MX51_PAD_EIM_CS5__FEC_CRS,
127 MX51_PAD_NANDF_RB2__FEC_COL,
128 MX51_PAD_NANDF_RB3__FEC_RX_CLK,
129 MX51_PAD_NANDF_D9__FEC_RDATA0,
130 MX51_PAD_NANDF_D8__FEC_TDATA0,
131 MX51_PAD_NANDF_CS2__FEC_TX_ER,
132 MX51_PAD_NANDF_CS3__FEC_MDC,
133 MX51_PAD_NANDF_CS4__FEC_TDATA1,
134 MX51_PAD_NANDF_CS5__FEC_TDATA2,
135 MX51_PAD_NANDF_CS6__FEC_TDATA3,
136 MX51_PAD_NANDF_CS7__FEC_TX_EN,
137 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
139 /* FEC PHY reset line */
140 MX51_PAD_EIM_A20__GPIO2_14,
143 MX51_PAD_SD1_CMD__SD1_CMD,
144 MX51_PAD_SD1_CLK__SD1_CLK,
145 MX51_PAD_SD1_DATA0__SD1_DATA0,
146 MX51_PAD_SD1_DATA1__SD1_DATA1,
147 MX51_PAD_SD1_DATA2__SD1_DATA2,
148 MX51_PAD_SD1_DATA3__SD1_DATA3,
149 MX51_PAD_GPIO1_0__GPIO1_0,
150 MX51_PAD_GPIO1_1__GPIO1_1,
153 MX51_PAD_SD2_CMD__SD2_CMD,
154 MX51_PAD_SD2_CLK__SD2_CLK,
155 MX51_PAD_SD2_DATA0__SD2_DATA0,
156 MX51_PAD_SD2_DATA1__SD2_DATA1,
157 MX51_PAD_SD2_DATA2__SD2_DATA2,
158 MX51_PAD_SD2_DATA3__SD2_DATA3,
159 MX51_PAD_GPIO1_6__GPIO1_6,
160 MX51_PAD_GPIO1_5__GPIO1_5,
163 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
164 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
165 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
166 MX51_PAD_CSPI1_SS0__GPIO4_24,
167 MX51_PAD_CSPI1_SS1__GPIO4_25,
171 static const struct imxuart_platform_data uart_pdata __initconst = {
172 .flags = IMXUART_HAVE_RTSCTS,
175 static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
179 static struct imxi2c_platform_data babbage_hsi2c_data = {
183 static struct gpio mx51_babbage_usbh1_gpios[] = {
184 { BABBAGE_USBH1_STP, GPIOF_OUT_INIT_LOW, "usbh1_stp" },
185 { BABBAGE_USB_PHY_RESET, GPIOF_OUT_INIT_LOW, "usbh1_phy_reset" },
188 static int gpio_usbh1_active(void)
190 iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
193 /* Set USBH1_STP to GPIO and toggle it */
194 mxc_iomux_v3_setup_pad(usbh1stp_gpio);
195 ret = gpio_request_array(mx51_babbage_usbh1_gpios,
196 ARRAY_SIZE(mx51_babbage_usbh1_gpios));
199 pr_debug("failed to get USBH1 pins: %d\n", ret);
204 gpio_set_value(BABBAGE_USBH1_STP, 1);
205 gpio_set_value(BABBAGE_USB_PHY_RESET, 1);
206 gpio_free_array(mx51_babbage_usbh1_gpios,
207 ARRAY_SIZE(mx51_babbage_usbh1_gpios));
211 static inline void babbage_usbhub_reset(void)
216 ret = gpio_request_one(BABBAGE_USB_HUB_RESET,
217 GPIOF_OUT_INIT_LOW, "GPIO1_7");
219 printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
225 gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
228 static inline void babbage_fec_reset(void)
233 ret = gpio_request_one(BABBAGE_FEC_PHY_RESET,
234 GPIOF_OUT_INIT_LOW, "fec-phy-reset");
236 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
240 gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
243 /* This function is board specific as the bit mask for the plldiv will also
244 be different for other Freescale SoCs, thus a common bitmask is not
245 possible and cannot get place in /plat-mxc/ehci.c.*/
246 static int initialize_otg_port(struct platform_device *pdev)
249 void __iomem *usb_base;
250 void __iomem *usbother_base;
252 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
255 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
257 /* Set the PHY clock to 19.2MHz */
258 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
259 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
260 v |= MX51_USB_PLL_DIV_19_2_MHZ;
261 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
266 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
269 static int initialize_usbh1_port(struct platform_device *pdev)
272 void __iomem *usb_base;
273 void __iomem *usbother_base;
275 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
278 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
280 /* The clock for the USBH1 ULPI port will come externally from the PHY. */
281 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
282 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
287 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
288 MXC_EHCI_ITC_NO_THRESHOLD);
291 static struct mxc_usbh_platform_data dr_utmi_config = {
292 .init = initialize_otg_port,
293 .portsc = MXC_EHCI_UTMI_16BIT,
296 static struct fsl_usb2_platform_data usb_pdata = {
297 .operating_mode = FSL_USB2_DR_DEVICE,
298 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
301 static struct mxc_usbh_platform_data usbh1_config = {
302 .init = initialize_usbh1_port,
303 .portsc = MXC_EHCI_MODE_ULPI,
306 static int otg_mode_host;
308 static int __init babbage_otg_mode(char *options)
310 if (!strcmp(options, "host"))
312 else if (!strcmp(options, "device"))
315 pr_info("otg_mode neither \"host\" nor \"device\". "
316 "Defaulting to device\n");
319 __setup("otg_mode=", babbage_otg_mode);
321 static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
323 .modalias = "mtd_dataflash",
324 .max_speed_hz = 25000000,
328 .platform_data = NULL,
332 static int mx51_babbage_spi_cs[] = {
337 static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
338 .chipselect = mx51_babbage_spi_cs,
339 .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
342 static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = {
343 .cd_gpio = BABBAGE_SD1_CD,
344 .wp_gpio = BABBAGE_SD1_WP,
347 static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
348 .cd_gpio = BABBAGE_SD2_CD,
349 .wp_gpio = BABBAGE_SD2_WP,
353 * Board specific initialization.
355 static void __init mx51_babbage_init(void)
357 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
358 iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
359 MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
363 #if defined(CONFIG_CPU_FREQ_IMX)
364 get_cpu_op = mx51_get_cpu_op;
366 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
367 ARRAY_SIZE(mx51babbage_pads));
369 imx51_add_imx_uart(0, &uart_pdata);
370 imx51_add_imx_uart(1, &uart_pdata);
371 imx51_add_imx_uart(2, &uart_pdata);
376 /* Set the PAD settings for the pwr key. */
377 mxc_iomux_v3_setup_pad(power_key);
378 imx_add_gpio_keys(&imx_button_data);
380 imx51_add_imx_i2c(0, &babbage_i2c_data);
381 imx51_add_imx_i2c(1, &babbage_i2c_data);
382 mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
385 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
387 initialize_otg_port(NULL);
388 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
392 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
393 /* setback USBH1_STP to be function */
394 mxc_iomux_v3_setup_pad(usbh1stp);
395 babbage_usbhub_reset();
397 imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data);
398 imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data);
400 spi_register_board_info(mx51_babbage_spi_board_info,
401 ARRAY_SIZE(mx51_babbage_spi_board_info));
402 imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
403 imx51_add_imx2_wdt(0, NULL);
406 static void __init mx51_babbage_timer_init(void)
408 mx51_clocks_init(32768, 24000000, 22579200, 0);
411 static struct sys_timer mx51_babbage_timer = {
412 .init = mx51_babbage_timer_init,
415 MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
416 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
417 .boot_params = MX51_PHYS_OFFSET + 0x100,
418 .map_io = mx51_map_io,
419 .init_early = imx51_init_early,
420 .init_irq = mx51_init_irq,
421 .timer = &mx51_babbage_timer,
422 .init_machine = mx51_babbage_init,