1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
14 #include <asm/global_data.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/soc.h>
19 #if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) || defined(CONFIG_SPL_MMC) || \
20 defined(CONFIG_SPL_SATA)
23 * When loading U-Boot via SPL from SPI NOR, CONFIG_SYS_SPI_U_BOOT_OFFS must
24 * point to the offset of kwbimage main header which is always at offset zero
25 * (defined by BootROM). Therefore other values of CONFIG_SYS_SPI_U_BOOT_OFFS
26 * makes U-Boot non-bootable.
28 #ifdef CONFIG_SPL_SPI_FLASH_SUPPORT
29 #if defined(CONFIG_SYS_SPI_U_BOOT_OFFS) && CONFIG_SYS_SPI_U_BOOT_OFFS != 0
30 #error CONFIG_SYS_SPI_U_BOOT_OFFS must be set to 0
35 * When loading U-Boot via SPL from eMMC (in Marvell terminology SDIO), the
36 * kwbimage main header is stored at sector 0. U-Boot SPL needs to parse this
37 * header and figure out at which sector the U-Boot proper binary is stored.
38 * Partition booting is therefore not supported and CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
39 * and CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET need to point to the
40 * kwbimage main header.
43 #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
44 #error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is unsupported
46 #if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR) && CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR != 0
47 #error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR must be set to 0
49 #if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET) && CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET != 0
50 #error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET must be set to 0
55 * When loading U-Boot via SPL from SATA disk, the kwbimage main header is
56 * stored at sector 1. Therefore CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR must be
57 * set to 1. Otherwise U-Boot SPL would not be able to load U-Boot proper.
59 #ifdef CONFIG_SPL_SATA
60 #if !defined(CONFIG_SPL_SATA_RAW_U_BOOT_USE_SECTOR) || !defined(CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR) || CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR != 1
61 #error CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR must be set to 1
65 /* Boot Type - block ID */
66 #define IBR_HDR_I2C_ID 0x4D
67 #define IBR_HDR_SPI_ID 0x5A
68 #define IBR_HDR_NAND_ID 0x8B
69 #define IBR_HDR_SATA_ID 0x78
70 #define IBR_HDR_PEX_ID 0x9C
71 #define IBR_HDR_UART_ID 0x69
72 #define IBR_HDR_SDIO_ID 0xAE
74 /* Structure of the main header, version 1 (Armada 370/XP/375/38x/39x) */
75 struct kwbimage_main_hdr_v1 {
78 u16 nandpagesize; /* 0x2-0x3 */
79 u32 blocksize; /* 0x4-0x7 */
81 u8 headersz_msb; /* 0x9 */
82 u16 headersz_lsb; /* 0xA-0xB */
83 u32 srcaddr; /* 0xC-0xF */
84 u32 destaddr; /* 0x10-0x13 */
85 u32 execaddr; /* 0x14-0x17 */
86 u8 options; /* 0x18 */
87 u8 nandblocksize; /* 0x19 */
88 u8 nandbadblklocation; /* 0x1A */
89 u8 reserved4; /* 0x1B */
90 u16 reserved5; /* 0x1C-0x1D */
92 u8 checksum; /* 0x1F */
96 u32 spl_mmc_boot_mode(const u32 boot_device)
98 return MMCSD_MODE_RAW;
102 static u32 checksum32(void *start, u32 len)
115 int spl_check_board_image(struct spl_image_info *spl_image,
116 const struct spl_boot_device *bootdev)
118 u32 csum = *(u32 *)(spl_image->load_addr + spl_image->size - 4);
120 if (checksum32((void *)spl_image->load_addr,
121 spl_image->size - 4) != csum) {
122 printf("ERROR: Invalid data checksum in kwbimage\n");
129 int spl_parse_board_header(struct spl_image_info *spl_image,
130 const struct spl_boot_device *bootdev,
131 const void *image_header, size_t size)
133 const struct kwbimage_main_hdr_v1 *mhdr = image_header;
135 if (size < sizeof(*mhdr)) {
136 /* This should be compile time assert */
137 printf("FATAL ERROR: Image header size is too small\n");
142 * Very basic check for image validity. We cannot check mhdr->checksum
143 * as it is calculated also from variable length extended headers
144 * (including SPL content) which is not included in U-Boot image_header.
146 if (mhdr->version != 1 ||
147 ((mhdr->headersz_msb << 16) | mhdr->headersz_lsb) < sizeof(*mhdr)) {
148 printf("ERROR: Invalid kwbimage v1\n");
152 #ifdef CONFIG_SPL_SPI_FLASH_SUPPORT
153 if (bootdev->boot_device == BOOT_DEVICE_SPI &&
154 mhdr->blockid != IBR_HDR_SPI_ID) {
155 printf("ERROR: Wrong blockid (0x%x) in SPI kwbimage\n",
161 #ifdef CONFIG_SPL_SATA
162 if (bootdev->boot_device == BOOT_DEVICE_SATA &&
163 mhdr->blockid != IBR_HDR_SATA_ID) {
164 printf("ERROR: Wrong blockid (0x%x) in SATA kwbimage\n",
170 #ifdef CONFIG_SPL_MMC
171 if ((bootdev->boot_device == BOOT_DEVICE_MMC1 ||
172 bootdev->boot_device == BOOT_DEVICE_MMC2 ||
173 bootdev->boot_device == BOOT_DEVICE_MMC2_2) &&
174 mhdr->blockid != IBR_HDR_SDIO_ID) {
175 printf("ERROR: Wrong blockid (0x%x) in SDIO kwbimage\n",
181 spl_image->offset = mhdr->srcaddr;
183 #ifdef CONFIG_SPL_SATA
185 * For SATA srcaddr is specified in number of sectors.
186 * The main header is must be stored at sector number 1.
187 * This expects that sector size is 512 bytes and recalculates
188 * data offset to bytes relative to the main header.
190 if (mhdr->blockid == IBR_HDR_SATA_ID) {
191 if (spl_image->offset < 1) {
192 printf("ERROR: Wrong srcaddr (0x%08x) in SATA kwbimage\n",
196 spl_image->offset -= 1;
197 spl_image->offset *= 512;
201 #ifdef CONFIG_SPL_MMC
203 * For SDIO (eMMC) srcaddr is specified in number of sectors.
204 * This expects that sector size is 512 bytes and recalculates
205 * data offset to bytes.
207 if (mhdr->blockid == IBR_HDR_SDIO_ID)
208 spl_image->offset *= 512;
211 if (spl_image->offset % 4 != 0) {
212 printf("ERROR: Wrong srcaddr (0x%08x) in kwbimage\n",
217 if (mhdr->blocksize <= 4 || mhdr->blocksize % 4 != 0) {
218 printf("ERROR: Wrong blocksize (0x%08x) in kwbimage\n",
223 spl_image->size = mhdr->blocksize;
224 spl_image->entry_point = mhdr->execaddr;
225 spl_image->load_addr = mhdr->destaddr;
226 spl_image->os = IH_OS_U_BOOT;
227 spl_image->name = "U-Boot";
232 u32 spl_boot_device(void)
234 u32 boot_device = get_boot_device();
236 switch (boot_device) {
238 * Return to the BootROM to continue the Marvell xmodem
239 * UART boot protocol. As initiated by the kwboot tool.
241 * This can only be done by the BootROM since the beginning
242 * of the image is already read and interpreted by the BootROM.
243 * SPL has no chance to receive this information. So we
244 * need to return to the BootROM to enable this xmodem
245 * UART download. Use SPL infrastructure to return to BootROM.
247 case BOOT_DEVICE_UART:
248 return BOOT_DEVICE_BOOTROM;
251 * If SPL is compiled with chosen boot_device support
252 * then use SPL driver for loading U-Boot proper.
254 #ifdef CONFIG_SPL_MMC
255 case BOOT_DEVICE_MMC1:
256 return BOOT_DEVICE_MMC1;
258 #ifdef CONFIG_SPL_SATA
259 case BOOT_DEVICE_SATA:
260 return BOOT_DEVICE_SATA;
262 #ifdef CONFIG_SPL_SPI_FLASH_SUPPORT
263 case BOOT_DEVICE_SPI:
264 return BOOT_DEVICE_SPI;
268 * If SPL is not compiled with chosen boot_device support
269 * then return to the BootROM. BootROM supports loading
270 * U-Boot proper from any valid boot_device present in SAR
274 return BOOT_DEVICE_BOOTROM;
280 u32 spl_boot_device(void)
282 return BOOT_DEVICE_BOOTROM;
287 int board_return_to_bootrom(struct spl_image_info *spl_image,
288 struct spl_boot_device *bootdev)
290 u32 *regs = *(u32 **)CONFIG_SPL_BOOTROM_SAVE;
292 printf("Returning to BootROM (return address 0x%08x)...\n", regs[13]);
295 /* NOTREACHED - return_to_bootrom() does not return */
299 void board_init_f(ulong dummy)
304 * Pin muxing needs to be done before UART output, since
305 * on A38x the UART pins need some re-muxing for output
308 board_early_init_f();
311 * Use special translation offset for SPL. This needs to be
312 * configured *before* spl_init() is called as this function
313 * calls dm_init() which calls the bind functions of the
314 * device drivers. Here the base address needs to be configured
315 * (translated) correctly.
317 gd->translation_offset = 0xd0000000 - 0xf1000000;
321 printf("spl_init() failed: %d\n", ret);
325 preloader_console_init();
329 /* Armada 375 does not support SerDes and DDR3 init yet */
330 #if !defined(CONFIG_ARMADA_375)
331 /* First init the serdes PHY's */
337 printf("ddr3_init() failed: %d\n", ret);
342 /* Initialize Auto Voltage Scaling */
345 /* Update read timing control for PCIe */