2 * Copyright (C) Marvell International Ltd. and its affiliates
4 * SPDX-License-Identifier: GPL-2.0
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/soc.h>
13 #include "high_speed_env_spec.h"
14 #include "sys_env_lib.h"
17 #if defined(CONFIG_ARMADA_38X)
18 #elif defined(CONFIG_ARMADA_39X)
20 #error "No device is defined"
24 * The board topology map, initialized in the beginning of
25 * ctrl_high_speed_serdes_phy_config
27 struct serdes_map serdes_configuration_map[MAX_SERDES_LANES];
30 * serdes_seq_db - holds all serdes sequences, their size and the
31 * relevant index in the data array initialized in serdes_seq_init
33 struct cfg_seq serdes_seq_db[SERDES_LAST_SEQ];
35 #define SERDES_VERION "2.0"
36 #define ENDED_OK "High speed PHY - Ended Successfully\n"
38 #define LINK_WAIT_CNTR 100
39 #define LINK_WAIT_SLEEP 100
41 #define MAX_UNIT_NUMB 4
42 #define TOPOLOGY_TEST_OK 0
43 #define WRONG_NUMBER_OF_UNITS 1
44 #define SERDES_ALREADY_IN_USE 2
45 #define UNIT_NUMBER_VIOLATION 3
48 * serdes_lane_in_use_count contains the exact amount of serdes lanes
51 u8 serdes_lane_in_use_count[MAX_UNITS_ID][MAX_UNIT_NUMB] = {
53 { 1, 1, 1, 1 }, /* PEX */
54 { 1, 1, 1, 1 }, /* ETH_GIG */
55 { 1, 1, 0, 0 }, /* USB3H */
56 { 1, 1, 1, 0 }, /* USB3D */
57 { 1, 1, 1, 1 }, /* SATA */
58 { 1, 0, 0, 0 }, /* QSGMII */
59 { 4, 0, 0, 0 }, /* XAUI */
60 { 2, 0, 0, 0 } /* RXAUI */
64 * serdes_unit_count count unit number.
65 * (i.e a single XAUI is counted as 1 unit)
67 u8 serdes_unit_count[MAX_UNITS_ID] = { 0 };
69 /* Selector mapping for A380-A0 and A390-Z1 */
70 u8 selectors_serdes_rev2_map[LAST_SERDES_TYPE][MAX_SERDES_LANES] = {
72 { 0x1, 0x1, NA, NA, NA, NA, NA }, /* PEX0 */
73 { NA, NA, 0x1, NA, 0x1, NA, 0x1 }, /* PEX1 */
74 { NA, NA, NA, NA, 0x7, 0x1, NA }, /* PEX2 */
75 { NA, NA, NA, 0x1, NA, NA, NA }, /* PEX3 */
76 { 0x2, 0x3, NA, NA, NA, NA, NA }, /* SATA0 */
77 { NA, NA, 0x3, NA, NA, NA, NA }, /* SATA1 */
78 { NA, NA, NA, NA, 0x6, 0x2, NA }, /* SATA2 */
79 { NA, NA, NA, 0x3, NA, NA, NA }, /* SATA3 */
80 { 0x3, 0x4, NA, NA, NA, NA, NA }, /* SGMII0 */
81 { NA, 0x5, 0x4, NA, 0x3, NA, NA }, /* SGMII1 */
82 { NA, NA, NA, 0x4, NA, 0x3, NA }, /* SGMII2 */
83 { NA, 0x7, NA, NA, NA, NA, NA }, /* QSGMII */
84 { NA, 0x6, NA, NA, 0x4, NA, NA }, /* USB3_HOST0 */
85 { NA, NA, NA, 0x5, NA, 0x4, NA }, /* USB3_HOST1 */
86 { NA, NA, NA, 0x6, 0x5, 0x5, NA }, /* USB3_DEVICE */
87 #ifdef CONFIG_ARMADA_39X
88 { NA, NA, 0x5, NA, 0x8, NA, 0x2 }, /* SGMII3 */
89 { NA, NA, NA, 0x8, 0x9, 0x8, 0x4 }, /* XAUI */
90 { NA, NA, NA, NA, NA, 0x8, 0x4 }, /* RXAUI */
92 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, NA } /* DEFAULT_SERDES */
95 /* Selector mapping for PEX by 4 confiuration */
96 u8 common_phys_selectors_pex_by4_lanes[] = { 0x1, 0x2, 0x2, 0x2 };
98 static const char *const serdes_type_to_string[] = {
121 struct serdes_unit_data {
126 static struct serdes_unit_data serdes_type_to_unit_info[] = {
135 {ETH_GIG_UNIT_ID, 0,},
136 {ETH_GIG_UNIT_ID, 1,},
137 {ETH_GIG_UNIT_ID, 2,},
138 {QSGMII_UNIT_ID, 0,},
142 {ETH_GIG_UNIT_ID, 3,},
153 struct op_params sata_port0_power_up_params[] = {
155 * unit_base_reg, unit_offset, mask, SATA data, wait_time,
158 /* Access to reg 0x48(OOB param 1) */
159 {SATA_VENDOR_PORT_0_REG_ADDR, 0x38000, 0xffffffff, {0x48,}, 0, 0},
160 /* OOB Com_wake and Com_reset spacing upper limit data */
161 {SATA_VENDOR_PORT_0_REG_DATA, 0x38000, 0xf03f, {0x6018,}, 0, 0},
162 /* Access to reg 0xa(PHY Control) */
163 {SATA_VENDOR_PORT_0_REG_ADDR, 0x38000, 0xffffffff, {0xa,}, 0, 0},
164 /* Rx clk and Tx clk select non-inverted mode */
165 {SATA_VENDOR_PORT_0_REG_DATA, 0x38000, 0x3000, {0x0,}, 0, 0},
166 /* Power Down Sata addr */
167 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0,}, 0, 0},
168 /* Power Down Sata Port 0 */
169 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffff00ff, {0xc40040,}, 0, 0},
172 struct op_params sata_port1_power_up_params[] = {
174 * unit_base_reg, unit_offset, mask, SATA data, wait_time,
177 /* Access to reg 0x48(OOB param 1) */
178 {SATA_VENDOR_PORT_1_REG_ADDR, 0x38000, 0xffffffff, {0x48,}, 0, 0},
179 /* OOB Com_wake and Com_reset spacing upper limit data */
180 {SATA_VENDOR_PORT_1_REG_DATA, 0x38000, 0xf03f, {0x6018,}, 0, 0},
181 /* Access to reg 0xa(PHY Control) */
182 {SATA_VENDOR_PORT_1_REG_ADDR, 0x38000, 0xffffffff, {0xa,}, 0, 0},
183 /* Rx clk and Tx clk select non-inverted mode */
184 {SATA_VENDOR_PORT_1_REG_DATA, 0x38000, 0x3000, {0x0,}, 0, 0},
185 /* Power Down Sata addr */
186 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0,}, 0, 0},
187 /* Power Down Sata Port 1 */
188 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffff00, {0xc44000,}, 0, 0},
191 /* SATA and SGMII - power up seq */
192 struct op_params sata_and_sgmii_power_up_params[] = {
194 * unit_base_reg, unit_offset, mask, SATA data, SGMII data,
195 * wait_time, num_of_loops
198 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x90006, {0x80002, 0x80002},
201 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000, 0x6000}, 0, 0},
203 {POWER_AND_PLL_CTRL_REG, 0x800, 0x0e0, {0x0, 0x80}, 0, 0},
204 /* Ref clock source select */
205 {MISC_REG, 0x800, 0x440, {0x440, 0x400}, 0, 0}
208 /* SATA and SGMII - speed config seq */
209 struct op_params sata_and_sgmii_speed_config_params[] = {
211 * unit_base_reg, unit_offset, mask, SATA data,
212 * SGMII (1.25G), SGMII (3.125G), wait_time, num_of_loops
215 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc00000,
216 {0x8800000, 0x19800000, 0x22000000}, 0, 0},
217 /* Select Baud Rate for SATA only */
218 {INTERFACE_REG, 0x800, 0xc00, {0x800, NO_DATA, NO_DATA}, 0, 0},
219 /* Phy Gen RX and TX */
220 {ISOLATE_REG, 0x800, 0xff, {NO_DATA, 0x66, 0x66}, 0, 0},
222 {LOOPBACK_REG, 0x800, 0xe, {0x4, 0x2, 0x2}, 0, 0}
225 /* SATA and SGMII - TX config seq */
226 struct op_params sata_and_sgmii_tx_config_params1[] = {
228 * unitunit_base_reg, unit_offset, mask, SATA data, SGMII data,
229 * wait_time, num_of_loops
231 {GLUE_REG, 0x800, 0x1800, {NO_DATA, 0x800}, 0, 0},
232 /* Sft Reset pulse */
233 {RESET_DFE_REG, 0x800, 0x401, {0x401, 0x401}, 0, 0},
234 /* Sft Reset pulse */
235 {RESET_DFE_REG, 0x800, 0x401, {0x0, 0x0}, 0, 0},
236 /* Power up PLL, RX and TX */
237 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0xf0000, {0x70000, 0x70000},
241 struct op_params sata_port0_tx_config_params[] = {
243 * unit_base_reg, unit_offset, mask, SATA data, wait_time,
246 /* Power Down Sata addr */
247 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0}, 0, 0},
248 /* Power Down Sata Port 0 */
249 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffff00ff, {0xc40000}, 0, 0},
250 /* Regret bit addr */
251 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x4}, 0, 0},
252 /* Regret bit data */
253 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffffff, {0x80}, 0, 0}
256 struct op_params sata_port1_tx_config_params[] = {
258 * unit_base_reg, unit_offset, mask, SATA data, wait_time,
261 /* Power Down Sata addr */
262 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0}, 0, 0},
263 /* Power Down Sata Port 1 */
264 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffff00, {0xc40000}, 0, 0},
265 /* Regret bit addr */
266 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x4}, 0, 0},
267 /* Regret bit data */
268 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffffff, {0x80}, 0, 0}
271 struct op_params sata_and_sgmii_tx_config_serdes_rev1_params2[] = {
273 * unit_base_reg, unit_offset, mask, SATA data, SGMII data,
274 * wait_time, num_of_loops
276 /* Wait for PHY power up sequence to finish */
277 {COMMON_PHY_STATUS1_REG, 0x28, 0xc, {0xc, 0xc}, 10, 1000},
278 /* Wait for PHY power up sequence to finish */
279 {COMMON_PHY_STATUS1_REG, 0x28, 0x1, {0x1, 0x1}, 1, 1000}
282 struct op_params sata_and_sgmii_tx_config_serdes_rev2_params2[] = {
284 * unit_base_reg, unit_offset, mask, SATA data, SGMII data,
285 * wait_time, num_of_loops
287 /* Wait for PHY power up sequence to finish */
288 {COMMON_PHY_STATUS1_REG, 0x28, 0xc, {0xc, 0xc}, 10, 1000},
289 /* Assert Rx Init for SGMII */
290 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40000000, {NA, 0x40000000},
292 /* Assert Rx Init for SATA */
293 {ISOLATE_REG, 0x800, 0x400, {0x400, NA}, 0, 0},
294 /* Wait for PHY power up sequence to finish */
295 {COMMON_PHY_STATUS1_REG, 0x28, 0x1, {0x1, 0x1}, 1, 1000},
296 /* De-assert Rx Init for SGMII */
297 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40000000, {NA, 0x0}, 0, 0},
298 /* De-assert Rx Init for SATA */
299 {ISOLATE_REG, 0x800, 0x400, {0x0, NA}, 0, 0},
300 /* os_ph_offset_force (align 90) */
301 {RX_REG3, 0x800, 0xff, {0xde, NO_DATA}, 0, 0},
302 /* Set os_ph_valid */
303 {RX_REG3, 0x800, 0x100, {0x100, NO_DATA}, 0, 0},
304 /* Unset os_ph_valid */
305 {RX_REG3, 0x800, 0x100, {0x0, NO_DATA}, 0, 0},
308 struct op_params sata_electrical_config_serdes_rev1_params[] = {
310 * unit_base_reg, unit_offset, mask, SATA data, wait_time,
313 /* enable SSC and DFE update enable */
314 {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x400008, {0x400000,}, 0, 0},
315 /* tximpcal_th and rximpcal_th */
316 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x4000,}, 0, 0},
317 /* SQ_THRESH and FFE Setting */
318 {SQUELCH_FFE_SETTING_REG, 0x800, 0xfff, {0x6cf,}, 0, 0},
319 /* G1_TX SLEW, EMPH1 and AMP */
320 {G1_SETTINGS_0_REG, 0x800, 0xffff, {0x8a32,}, 0, 0},
321 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
322 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9,}, 0, 0},
323 /* G2_TX SLEW, EMPH1 and AMP */
324 {G2_SETTINGS_0_REG, 0x800, 0xffff, {0x8b5c,}, 0, 0},
325 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
326 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2,}, 0, 0},
327 /* G3_TX SLEW, EMPH1 and AMP */
328 {G3_SETTINGS_0_REG, 0x800, 0xffff, {0xe6e,}, 0, 0},
329 /* G3_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
330 {G3_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2,}, 0, 0},
331 /* Cal rxclkalign90 ext enable and Cal os ph ext */
332 {CAL_REG6, 0x800, 0xff00, {0xdd00,}, 0, 0},
333 /* Dtl Clamping disable and Dtl clamping Sel(6000ppm) */
334 {RX_REG2, 0x800, 0xf0, {0x70,}, 0, 0},
337 struct op_params sata_electrical_config_serdes_rev2_params[] = {
339 * unit_base_reg, unit_offset, mask, SATA data, wait_time,
342 /* SQ_THRESH and FFE Setting */
343 {SQUELCH_FFE_SETTING_REG, 0x800, 0xf00, {0x600}, 0, 0},
344 /* enable SSC and DFE update enable */
345 {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x400008, {0x400000}, 0, 0},
346 /* G1_TX SLEW, EMPH1 and AMP */
347 {G1_SETTINGS_0_REG, 0x800, 0xffff, {0x8a32}, 0, 0},
348 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
349 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
350 /* G2_TX SLEW, EMPH1 and AMP */
351 {G2_SETTINGS_0_REG, 0x800, 0xffff, {0x8b5c}, 0, 0},
352 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
353 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2}, 0, 0},
354 /* G3_TX SLEW, EMPH1 and AMP */
355 {G3_SETTINGS_0_REG, 0x800, 0xffff, {0xe6e}, 0, 0},
357 * G3_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI & DFE_En Gen3,
358 * DC wander calibration dis
360 {G3_SETTINGS_1_REG, 0x800, 0x47ff, {0x7d2}, 0, 0},
361 /* Bit[12]=0x0 idle_sync_en */
362 {PCIE_REG0, 0x800, 0x1000, {0x0}, 0, 0},
363 /* Dtl Clamping disable and Dtl clamping Sel(6000ppm) */
364 {RX_REG2, 0x800, 0xf0, {0x70,}, 0, 0},
365 /* tximpcal_th and rximpcal_th */
366 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0},
367 /* DFE_STEP_FINE_FX[3:0] =0xa */
368 {DFE_REG0, 0x800, 0xa00f, {0x800a}, 0, 0},
369 /* DFE_EN and Dis Update control from pin disable */
370 {DFE_REG3, 0x800, 0xc000, {0x0}, 0, 0},
371 /* FFE Force FFE_REs and cap settings for Gen1 */
372 {G1_SETTINGS_3_REG, 0x800, 0xff, {0xcf}, 0, 0},
373 /* FFE Force FFE_REs and cap settings for Gen2 */
374 {G2_SETTINGS_3_REG, 0x800, 0xff, {0xbf}, 0, 0},
375 /* FE Force FFE_REs=4 and cap settings for Gen3n */
376 {G3_SETTINGS_3_REG, 0x800, 0xff, {0xcf}, 0, 0},
377 /* Set DFE Gen 3 Resolution to 3 */
378 {G3_SETTINGS_4_REG, 0x800, 0x300, {0x300}, 0, 0},
381 struct op_params sgmii_electrical_config_serdes_rev1_params[] = {
383 * unit_base_reg, unit_offset, mask, SGMII (1.25G), SGMII (3.125G),
384 * wait_time, num_of_loops
386 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
387 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9, 0x3c9}, 0, 0},
388 /* SQ_THRESH and FFE Setting */
389 {SQUELCH_FFE_SETTING_REG, 0x800, 0xfff, {0x8f, 0xbf}, 0, 0},
390 /* tximpcal_th and rximpcal_th */
391 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x4000, 0x4000}, 0, 0},
394 struct op_params sgmii_electrical_config_serdes_rev2_params[] = {
396 * unit_base_reg, unit_offset, mask, SGMII (1.25G), SGMII (3.125G),
397 * wait_time, num_of_loops
399 /* Set Slew_rate, Emph and Amp */
400 {G1_SETTINGS_0_REG, 0x800, 0xffff, {0x8fa, 0x8fa}, 0, 0},
401 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
402 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9, 0x3c9}, 0, 0},
404 {RX_REG2, 0x800, 0x4, {0x0, 0x0}, 0, 0},
405 /* G1 FFE Setting Force, RES and CAP */
406 {G1_SETTINGS_3_REG, 0x800, 0xff, {0x8f, 0xbf}, 0, 0},
407 /* tximpcal_th and rximpcal_th */
408 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000, 0x3000}, 0, 0},
415 /* PEX and USB3 - power up seq for Serdes Rev 1.2 */
416 struct op_params pex_and_usb3_power_up_serdes_rev1_params[] = {
418 * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
419 * wait_time, num_of_loops
421 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc7f806,
422 {0x4471804, 0x4479804}, 0, 0},
423 {COMMON_PHY_CONFIGURATION2_REG, 0x28, 0x5c, {0x58, 0x58}, 0, 0},
424 {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x3, {0x1, 0x1}, 0, 0},
425 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000, 0xe000}, 0, 0},
426 {GLOBAL_CLK_CTRL, 0x800, 0xd, {0x5, 0x1}, 0, 0},
427 /* Ref clock source select */
428 {MISC_REG, 0x800, 0x4c0, {0x80, 0x4c0}, 0, 0}
431 /* PEX and USB3 - power up seq for Serdes Rev 2.1 */
432 struct op_params pex_and_usb3_power_up_serdes_rev2_params[] = {
434 * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
435 * wait_time, num_of_loops
437 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc7f806,
438 {0x4471804, 0x4479804}, 0, 0},
439 {COMMON_PHY_CONFIGURATION2_REG, 0x28, 0x5c, {0x58, 0x58}, 0, 0},
440 {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x3, {0x1, 0x1}, 0, 0},
441 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000, 0xe000}, 0, 0},
442 {GLOBAL_CLK_CTRL, 0x800, 0xd, {0x5, 0x1}, 0, 0},
443 {GLOBAL_MISC_CTRL, 0x800, 0xc0, {0x0, NO_DATA}, 0, 0},
444 /* Ref clock source select */
445 {MISC_REG, 0x800, 0x4c0, {0x80, 0x4c0}, 0, 0}
448 /* PEX and USB3 - speed config seq */
449 struct op_params pex_and_usb3_speed_config_params[] = {
451 * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
452 * wait_time, num_of_loops
454 /* Maximal PHY Generation Setting */
455 {INTERFACE_REG, 0x800, 0xc00, {0x400, 0x400, 0x400, 0x400, 0x400},
459 struct op_params usb3_electrical_config_serdes_rev1_params[] = {
460 /* Spread Spectrum Clock Enable */
461 {LANE_CFG4_REG, 0x800, 0x80, {0x80}, 0, 0},
462 /* G2_TX_SSC_AMP[6:0]=4.5k_p_pM and TX emphasis mode=m_v */
463 {G2_SETTINGS_2_REG, 0x800, 0xfe40, {0x4440}, 0, 0},
464 /* tximpcal_th and rximpcal_th */
465 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x4000}, 0, 0},
466 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
467 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2}, 0, 0},
468 /* FFE Setting Force, RES and CAP */
469 {SQUELCH_FFE_SETTING_REG, 0x800, 0xff, {0xef}, 0, 0},
470 /* Dtl Clamping disable and Dtl-clamping-Sel(6000ppm) */
471 {RX_REG2, 0x800, 0xf0, {0x70}, 0, 0},
472 /* cal_rxclkalign90_ext_en and cal_os_ph_ext */
473 {CAL_REG6, 0x800, 0xff00, {0xd500}, 0, 0},
474 /* vco_cal_vth_sel */
475 {REF_REG0, 0x800, 0x38, {0x20}, 0, 0},
478 struct op_params usb3_electrical_config_serdes_rev2_params[] = {
479 /* Spread Spectrum Clock Enable */
480 {LANE_CFG4_REG, 0x800, 0x80, {0x80}, 0, 0},
481 /* G2_TX_SSC_AMP[6:0]=4.5k_p_pM and TX emphasis mode=m_v */
482 {G2_SETTINGS_2_REG, 0x800, 0xfe40, {0x4440}, 0, 0},
483 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
484 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2}, 0, 0},
485 /* Dtl Clamping disable and Dtl-clamping-Sel(6000ppm) */
486 {RX_REG2, 0x800, 0xf0, {0x70}, 0, 0},
487 /* vco_cal_vth_sel */
488 {REF_REG0, 0x800, 0x38, {0x20}, 0, 0},
489 /* Spread Spectrum Clock Enable */
490 {LANE_CFG5_REG, 0x800, 0x4, {0x4}, 0, 0},
493 /* PEX and USB3 - TX config seq */
496 * For PEXx1: the pex_and_usb3_tx_config_params1/2/3 configurations should run
497 * one by one on the lane.
498 * For PEXx4: the pex_and_usb3_tx_config_params1/2/3 configurations should run
499 * by setting each sequence for all 4 lanes.
501 struct op_params pex_and_usb3_tx_config_params1[] = {
503 * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
504 * wait_time, num_of_loops
506 {GLOBAL_CLK_CTRL, 0x800, 0x1, {0x0, 0x0}, 0, 0},
508 {0x0, 0x0, 0x0, {0x0, 0x0}, 10, 0},
509 /* os_ph_offset_force (align 90) */
510 {RX_REG3, 0x800, 0xff, {0xdc, NO_DATA}, 0, 0},
511 /* Set os_ph_valid */
512 {RX_REG3, 0x800, 0x100, {0x100, NO_DATA}, 0, 0},
513 /* Unset os_ph_valid */
514 {RX_REG3, 0x800, 0x100, {0x0, NO_DATA}, 0, 0},
517 struct op_params pex_and_usb3_tx_config_params2[] = {
519 * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
520 * wait_time, num_of_loops
522 /* Sft Reset pulse */
523 {RESET_DFE_REG, 0x800, 0x401, {0x401, 0x401}, 0, 0},
526 struct op_params pex_and_usb3_tx_config_params3[] = {
528 * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
529 * wait_time, num_of_loops
531 /* Sft Reset pulse */
532 {RESET_DFE_REG, 0x800, 0x401, {0x0, 0x0}, 0, 0},
534 {0x0, 0x0, 0x0, {0x0, 0x0}, 10, 0}
537 /* PEX by 4 config seq */
538 struct op_params pex_by4_config_params[] = {
539 /* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */
540 {GLOBAL_CLK_SRC_HI, 0x800, 0x7, {0x5, 0x0, 0x0, 0x2}, 0, 0},
541 /* Lane Alignement enable */
542 {LANE_ALIGN_REG0, 0x800, 0x1000, {0x0, 0x0, 0x0, 0x0}, 0, 0},
543 /* Max PLL phy config */
544 {CALIBRATION_CTRL_REG, 0x800, 0x1000, {0x1000, 0x1000, 0x1000, 0x1000},
546 /* Max PLL pipe config */
547 {LANE_CFG1_REG, 0x800, 0x600, {0x600, 0x600, 0x600, 0x600}, 0, 0},
550 /* USB3 device donfig seq */
551 struct op_params usb3_device_config_params[] = {
552 /* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */
553 {LANE_CFG4_REG, 0x800, 0x200, {0x200}, 0, 0}
556 /* PEX - electrical configuration seq Rev 1.2 */
557 struct op_params pex_electrical_config_serdes_rev1_params[] = {
559 * unit_base_reg, unit_offset, mask, PEX data, wait_time,
562 /* G1_TX_SLEW_CTRL_EN and G1_TX_SLEW_RATE */
563 {G1_SETTINGS_0_REG, 0x800, 0xf000, {0xb000}, 0, 0},
564 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
565 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
566 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
567 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
569 {LANE_CFG4_REG, 0x800, 0x8, {0x8}, 0, 0},
570 /* FFE Setting Force, RES and CAP */
571 {SQUELCH_FFE_SETTING_REG, 0x800, 0xff, {0xaf}, 0, 0},
572 /* tximpcal_th and rximpcal_th */
573 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0},
574 /* cal_rxclkalign90_ext_en and cal_os_ph_ext */
575 {CAL_REG6, 0x800, 0xff00, {0xdc00}, 0, 0},
578 /* PEX - electrical configuration seq Rev 2.1 */
579 struct op_params pex_electrical_config_serdes_rev2_params[] = {
581 * unit_base_reg, unit_offset, mask, PEX data, wait_time,
584 /* G1_TX_SLEW_CTRL_EN and G1_TX_SLEW_RATE */
585 {G1_SETTINGS_0_REG, 0x800, 0xf000, {0xb000}, 0, 0},
586 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
587 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
588 /* G1 FFE Setting Force, RES and CAP */
589 {G1_SETTINGS_3_REG, 0x800, 0xff, {0xcf}, 0, 0},
590 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
591 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
592 /* G2 FFE Setting Force, RES and CAP */
593 {G2_SETTINGS_3_REG, 0x800, 0xff, {0xaf}, 0, 0},
594 /* G2 DFE resolution value */
595 {G2_SETTINGS_4_REG, 0x800, 0x300, {0x300}, 0, 0},
596 /* DFE resolution force */
597 {DFE_REG0, 0x800, 0x8000, {0x8000}, 0, 0},
598 /* Tx amplitude for Tx Margin 0 */
599 {PCIE_REG1, 0x800, 0xf80, {0xd00}, 0, 0},
600 /* Tx_Emph value for -3.5d_b and -6d_b */
601 {PCIE_REG3, 0x800, 0xff00, {0xaf00}, 0, 0},
603 {LANE_CFG4_REG, 0x800, 0x8, {0x8}, 0, 0},
604 /* tximpcal_th and rximpcal_th */
605 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0},
608 /* PEX - configuration seq for REF_CLOCK_25MHz */
609 struct op_params pex_config_ref_clock25_m_hz[] = {
611 * unit_base_reg, unit_offset, mask, PEX data, wait_time,
614 /* Bits[4:0]=0x2 - REF_FREF_SEL */
615 {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x2}, 0, 0},
616 /* Bit[10]=0x1 - REFCLK_SEL */
617 {MISC_REG, 0x800, 0x400, {0x400}, 0, 0},
618 /* Bits[7:0]=0x7 - CFG_PM_RXDLOZ_WAIT */
619 {GLOBAL_PM_CTRL, 0x800, 0xff, {0x7}, 0, 0},
622 /* PEX - configuration seq for REF_CLOCK_40MHz */
623 struct op_params pex_config_ref_clock40_m_hz[] = {
625 * unit_base_reg, unit_offset, mask, PEX data, wait_time,
628 /* Bits[4:0]=0x3 - REF_FREF_SEL */
629 {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x3}, 0, 0},
630 /* Bits[10]=0x1 - REFCLK_SEL */
631 {MISC_REG, 0x800, 0x400, {0x400}, 0, 0},
632 /* Bits[7:0]=0xc - CFG_PM_RXDLOZ_WAIT */
633 {GLOBAL_PM_CTRL, 0x800, 0xff, {0xc}, 0, 0},
636 /* PEX - configuration seq for REF_CLOCK_100MHz */
637 struct op_params pex_config_ref_clock100_m_hz[] = {
639 * unit_base_reg, unit_offset, mask, PEX data, wait_time,
642 /* Bits[4:0]=0x0 - REF_FREF_SEL */
643 {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x0}, 0, 0},
644 /* Bit[10]=0x0 - REFCLK_SEL */
645 {MISC_REG, 0x800, 0x400, {0x0}, 0, 0},
646 /* Bits[7:0]=0x1e - CFG_PM_RXDLOZ_WAIT */
647 {GLOBAL_PM_CTRL, 0x800, 0xff, {0x1e}, 0, 0},
654 struct op_params usb2_power_up_params[] = {
656 * unit_base_reg, unit_offset, mask, USB2 data, wait_time,
660 {0x18440, 0x0 /*NA*/, 0xffffffff, {0x62}, 0, 0},
662 {0x18444, 0x0 /*NA*/, 0xffffffff, {0x62}, 0, 0},
664 {0x18448, 0x0 /*NA*/, 0xffffffff, {0x62}, 0, 0},
665 /* Phy offset 0x0 - PLL_CONTROL0 */
666 {0xc0000, 0x0 /*NA*/, 0xffffffff, {0x40605205}, 0, 0},
667 {0xc001c, 0x0 /*NA*/, 0xffffffff, {0x39f16ce}, 0, 0},
668 {0xc201c, 0x0 /*NA*/, 0xffffffff, {0x39f16ce}, 0, 0},
669 {0xc401c, 0x0 /*NA*/, 0xffffffff, {0x39f16ce}, 0, 0},
670 /* Phy offset 0x1 - PLL_CONTROL1 */
671 {0xc0004, 0x0 /*NA*/, 0x1, {0x1}, 0, 0},
672 /* Phy0 register 3 - TX Channel control 0 */
673 {0xc000c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0},
674 /* Phy0 register 3 - TX Channel control 0 */
675 {0xc200c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0},
676 /* Phy0 register 3 - TX Channel control 0 */
677 {0xc400c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0},
678 /* check PLLCAL_DONE is set and IMPCAL_DONE is set */
679 {0xc0008, 0x0 /*NA*/, 0x80800000, {0x80800000}, 1, 1000},
680 /* check REG_SQCAL_DONE is set */
681 {0xc0018, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000},
682 /* check PLL_READY is set */
683 {0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000}
690 /* QSGMII - power up seq */
691 struct op_params qsgmii_port_power_up_params[] = {
693 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
696 /* Connect the QSGMII to Gigabit Ethernet units */
697 {QSGMII_CONTROL_REG1, 0x0, 0x40000000, {0x40000000}, 0, 0},
699 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0xf0006, {0x80002}, 0, 0},
701 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000}, 0, 0},
703 {POWER_AND_PLL_CTRL_REG, 0x800, 0xff, {0xfc81}, 0, 0},
704 /* Ref clock source select */
705 {MISC_REG, 0x800, 0x4c0, {0x480}, 0, 0}
708 /* QSGMII - speed config seq */
709 struct op_params qsgmii_port_speed_config_params[] = {
711 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
715 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc00000, {0xcc00000}, 0, 0},
716 /* Phy Gen RX and TX */
717 {ISOLATE_REG, 0x800, 0xff, {0x33}, 0, 0},
719 {LOOPBACK_REG, 0x800, 0xe, {0x2}, 0, 0}
722 /* QSGMII - Select electrical param seq */
723 struct op_params qsgmii_port_electrical_config_params[] = {
725 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
728 /* Slew rate and emphasis */
729 {G1_SETTINGS_0_REG, 0x800, 0x8000, {0x0}, 0, 0}
732 /* QSGMII - TX config seq */
733 struct op_params qsgmii_port_tx_config_params1[] = {
735 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
738 {GLUE_REG, 0x800, 0x1800, {0x800}, 0, 0},
739 /* Sft Reset pulse */
740 {RESET_DFE_REG, 0x800, 0x401, {0x401}, 0, 0},
741 /* Sft Reset pulse */
742 {RESET_DFE_REG, 0x800, 0x401, {0x0}, 0, 0},
744 {LANE_ALIGN_REG0, 0x800, 0x1000, {0x1000}, 0, 0},
745 /* Power up PLL, RX and TX */
746 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x70000, {0x70000}, 0, 0},
747 /* Tx driver output idle */
748 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x80000, {0x80000}, 0, 0}
751 struct op_params qsgmii_port_tx_config_params2[] = {
753 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
756 /* Wait for PHY power up sequence to finish */
757 {COMMON_PHY_STATUS1_REG, 0x28, 0xc, {0xc}, 10, 1000},
758 /* Assert Rx Init and Tx driver output valid */
759 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40080000, {0x40000000}, 0, 0},
760 /* Wait for PHY power up sequence to finish */
761 {COMMON_PHY_STATUS1_REG, 0x28, 0x1, {0x1}, 1, 1000},
762 /* De-assert Rx Init */
763 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40000000, {0x0}, 0, 0}
766 /* SERDES_POWER_DOWN */
767 struct op_params serdes_power_down_params[] = {
768 {COMMON_PHY_CONFIGURATION1_REG, 0x28, (0xf << 11), {(0x3 << 11)},
770 {COMMON_PHY_CONFIGURATION1_REG, 0x28, (0x7 << 16), {0}, 0, 0}
774 * hws_ctrl_serdes_rev_get
776 * DESCRIPTION: Get the Serdes revision number
778 * INPUT: config_field - Field description enum
783 * 8bit Serdes revision number
785 u8 hws_ctrl_serdes_rev_get(void)
787 #ifdef CONFIG_ARMADA_38X
789 if (sys_env_device_rev_get() == MV_88F68XX_Z1_ID)
790 return MV_SERDES_REV_1_2;
793 /* for A39x-Z1, A38x-A0 */
794 return MV_SERDES_REV_2_1;
797 u32 hws_serdes_topology_verify(enum serdes_type serdes_type, u32 serdes_id,
798 enum serdes_mode serdes_mode)
801 u8 serd_max_num, unit_numb;
802 enum unit_id unit_id;
804 if (serdes_type > RXAUI) {
805 printf("%s: Warning: Wrong serdes type %s serdes#%d\n",
806 __func__, serdes_type_to_string[serdes_type], serdes_id);
810 unit_id = serdes_type_to_unit_info[serdes_type].serdes_unit_id;
811 unit_numb = serdes_type_to_unit_info[serdes_type].serdes_unit_num;
812 serd_max_num = sys_env_unit_max_num_get(unit_id);
814 /* if didn't exceed amount of required Serdes lanes for current type */
815 if (serdes_lane_in_use_count[unit_id][unit_numb] != 0) {
816 /* update amount of required Serdes lanes for current type */
817 serdes_lane_in_use_count[unit_id][unit_numb]--;
820 * If reached the exact amount of required Serdes lanes for
823 if (serdes_lane_in_use_count[unit_id][unit_numb] == 0) {
824 if (((serdes_type <= PEX3)) &&
825 ((serdes_mode == PEX_END_POINT_X4) ||
826 (serdes_mode == PEX_ROOT_COMPLEX_X4))) {
827 /* PCiex4 uses 2 SerDes */
828 serdes_unit_count[PEX_UNIT_ID] += 2;
830 serdes_unit_count[unit_id]++;
833 /* test SoC unit count limitation */
834 if (serdes_unit_count[unit_id] > serd_max_num) {
835 test_result = WRONG_NUMBER_OF_UNITS;
836 } else if (unit_numb >= serd_max_num) {
837 /* test SoC unit number limitation */
838 test_result = UNIT_NUMBER_VIOLATION;
842 test_result = SERDES_ALREADY_IN_USE;
843 if (test_result == SERDES_ALREADY_IN_USE) {
844 printf("%s: Error: serdes lane %d is configured to type %s: type already in use\n",
846 serdes_type_to_string[serdes_type]);
848 } else if (test_result == WRONG_NUMBER_OF_UNITS) {
849 printf("%s: Warning: serdes lane %d is set to type %s.\n",
851 serdes_type_to_string[serdes_type]);
852 printf("%s: Maximum supported lanes are already set to this type (limit = %d)\n",
853 __func__, serd_max_num);
855 } else if (test_result == UNIT_NUMBER_VIOLATION) {
856 printf("%s: Warning: serdes lane %d type is %s: current device support only %d units of this type.\n",
858 serdes_type_to_string[serdes_type],
867 void hws_serdes_xaui_topology_verify(void)
870 * If XAUI is in use - serdes_lane_in_use_count has to be = 0;
871 * if it is not in use hast be = 4
873 if ((serdes_lane_in_use_count[XAUI_UNIT_ID][0] != 0) &&
874 (serdes_lane_in_use_count[XAUI_UNIT_ID][0] != 4)) {
875 printf("%s: Warning: wrong number of lanes is set to XAUI - %d\n",
876 __func__, serdes_lane_in_use_count[XAUI_UNIT_ID][0]);
877 printf("%s: XAUI has to be defined on 4 lanes\n", __func__);
881 * If RXAUI is in use - serdes_lane_in_use_count has to be = 0;
882 * if it is not in use hast be = 2
884 if ((serdes_lane_in_use_count[RXAUI_UNIT_ID][0] != 0) &&
885 (serdes_lane_in_use_count[RXAUI_UNIT_ID][0] != 2)) {
886 printf("%s: Warning: wrong number of lanes is set to RXAUI - %d\n",
887 __func__, serdes_lane_in_use_count[RXAUI_UNIT_ID][0]);
888 printf("%s: RXAUI has to be defined on 2 lanes\n", __func__);
892 int hws_serdes_seq_db_init(void)
894 u8 serdes_rev = hws_ctrl_serdes_rev_get();
896 DEBUG_INIT_FULL_S("\n### serdes_seq38x_init ###\n");
898 if (serdes_rev == MV_SERDES_REV_NA) {
899 printf("hws_serdes_seq_db_init: serdes revision number is not supported\n");
900 return MV_NOT_SUPPORTED;
903 /* SATA_PORT_0_ONLY_POWER_UP_SEQ sequence init */
904 serdes_seq_db[SATA_PORT_0_ONLY_POWER_UP_SEQ].op_params_ptr =
905 sata_port0_power_up_params;
906 serdes_seq_db[SATA_PORT_0_ONLY_POWER_UP_SEQ].cfg_seq_size =
907 sizeof(sata_port0_power_up_params) / sizeof(struct op_params);
908 serdes_seq_db[SATA_PORT_0_ONLY_POWER_UP_SEQ].data_arr_idx = SATA;
910 /* SATA_PORT_1_ONLY_POWER_UP_SEQ sequence init */
911 serdes_seq_db[SATA_PORT_1_ONLY_POWER_UP_SEQ].op_params_ptr =
912 sata_port1_power_up_params;
913 serdes_seq_db[SATA_PORT_1_ONLY_POWER_UP_SEQ].cfg_seq_size =
914 sizeof(sata_port1_power_up_params) / sizeof(struct op_params);
915 serdes_seq_db[SATA_PORT_1_ONLY_POWER_UP_SEQ].data_arr_idx = SATA;
917 /* SATA_POWER_UP_SEQ sequence init */
918 serdes_seq_db[SATA_POWER_UP_SEQ].op_params_ptr =
919 sata_and_sgmii_power_up_params;
920 serdes_seq_db[SATA_POWER_UP_SEQ].cfg_seq_size =
921 sizeof(sata_and_sgmii_power_up_params) / sizeof(struct op_params);
922 serdes_seq_db[SATA_POWER_UP_SEQ].data_arr_idx = SATA;
924 /* SATA_1_5_SPEED_CONFIG_SEQ sequence init */
925 serdes_seq_db[SATA_1_5_SPEED_CONFIG_SEQ].op_params_ptr =
926 sata_and_sgmii_speed_config_params;
927 serdes_seq_db[SATA_1_5_SPEED_CONFIG_SEQ].cfg_seq_size =
928 sizeof(sata_and_sgmii_speed_config_params) /
929 sizeof(struct op_params);
930 serdes_seq_db[SATA_1_5_SPEED_CONFIG_SEQ].data_arr_idx = SATA;
932 /* SATA_3_SPEED_CONFIG_SEQ sequence init */
933 serdes_seq_db[SATA_3_SPEED_CONFIG_SEQ].op_params_ptr =
934 sata_and_sgmii_speed_config_params;
935 serdes_seq_db[SATA_3_SPEED_CONFIG_SEQ].cfg_seq_size =
936 sizeof(sata_and_sgmii_speed_config_params) /
937 sizeof(struct op_params);
938 serdes_seq_db[SATA_3_SPEED_CONFIG_SEQ].data_arr_idx = SATA;
940 /* SATA_6_SPEED_CONFIG_SEQ sequence init */
941 serdes_seq_db[SATA_6_SPEED_CONFIG_SEQ].op_params_ptr =
942 sata_and_sgmii_speed_config_params;
943 serdes_seq_db[SATA_6_SPEED_CONFIG_SEQ].cfg_seq_size =
944 sizeof(sata_and_sgmii_speed_config_params) /
945 sizeof(struct op_params);
946 serdes_seq_db[SATA_6_SPEED_CONFIG_SEQ].data_arr_idx = SATA;
948 /* SATA_ELECTRICAL_CONFIG_SEQ seq sequence init */
949 if (serdes_rev == MV_SERDES_REV_1_2) {
950 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
951 sata_electrical_config_serdes_rev1_params;
952 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
953 sizeof(sata_electrical_config_serdes_rev1_params) /
954 sizeof(struct op_params);
956 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
957 sata_electrical_config_serdes_rev2_params;
958 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
959 sizeof(sata_electrical_config_serdes_rev2_params) /
960 sizeof(struct op_params);
962 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].data_arr_idx = SATA;
964 /* SATA_TX_CONFIG_SEQ sequence init */
965 serdes_seq_db[SATA_TX_CONFIG_SEQ1].op_params_ptr =
966 sata_and_sgmii_tx_config_params1;
967 serdes_seq_db[SATA_TX_CONFIG_SEQ1].cfg_seq_size =
968 sizeof(sata_and_sgmii_tx_config_params1) / sizeof(struct op_params);
969 serdes_seq_db[SATA_TX_CONFIG_SEQ1].data_arr_idx = SATA;
971 /* SATA_PORT_0_ONLY_TX_CONFIG_SEQ sequence init */
972 serdes_seq_db[SATA_PORT_0_ONLY_TX_CONFIG_SEQ].op_params_ptr =
973 sata_port0_tx_config_params;
974 serdes_seq_db[SATA_PORT_0_ONLY_TX_CONFIG_SEQ].cfg_seq_size =
975 sizeof(sata_port0_tx_config_params) / sizeof(struct op_params);
976 serdes_seq_db[SATA_PORT_0_ONLY_TX_CONFIG_SEQ].data_arr_idx = SATA;
978 /* SATA_PORT_1_ONLY_TX_CONFIG_SEQ sequence init */
979 serdes_seq_db[SATA_PORT_1_ONLY_TX_CONFIG_SEQ].op_params_ptr =
980 sata_port1_tx_config_params;
981 serdes_seq_db[SATA_PORT_1_ONLY_TX_CONFIG_SEQ].cfg_seq_size =
982 sizeof(sata_port1_tx_config_params) / sizeof(struct op_params);
983 serdes_seq_db[SATA_PORT_1_ONLY_TX_CONFIG_SEQ].data_arr_idx = SATA;
985 /* SATA_TX_CONFIG_SEQ2 sequence init */
986 if (serdes_rev == MV_SERDES_REV_1_2) {
987 serdes_seq_db[SATA_TX_CONFIG_SEQ2].op_params_ptr =
988 sata_and_sgmii_tx_config_serdes_rev1_params2;
989 serdes_seq_db[SATA_TX_CONFIG_SEQ2].cfg_seq_size =
990 sizeof(sata_and_sgmii_tx_config_serdes_rev1_params2) /
991 sizeof(struct op_params);
993 serdes_seq_db[SATA_TX_CONFIG_SEQ2].op_params_ptr =
994 sata_and_sgmii_tx_config_serdes_rev2_params2;
995 serdes_seq_db[SATA_TX_CONFIG_SEQ2].cfg_seq_size =
996 sizeof(sata_and_sgmii_tx_config_serdes_rev2_params2) /
997 sizeof(struct op_params);
999 serdes_seq_db[SATA_TX_CONFIG_SEQ2].data_arr_idx = SATA;
1001 /* SGMII_POWER_UP_SEQ sequence init */
1002 serdes_seq_db[SGMII_POWER_UP_SEQ].op_params_ptr =
1003 sata_and_sgmii_power_up_params;
1004 serdes_seq_db[SGMII_POWER_UP_SEQ].cfg_seq_size =
1005 sizeof(sata_and_sgmii_power_up_params) / sizeof(struct op_params);
1006 serdes_seq_db[SGMII_POWER_UP_SEQ].data_arr_idx = SGMII;
1008 /* SGMII_1_25_SPEED_CONFIG_SEQ sequence init */
1009 serdes_seq_db[SGMII_1_25_SPEED_CONFIG_SEQ].op_params_ptr =
1010 sata_and_sgmii_speed_config_params;
1011 serdes_seq_db[SGMII_1_25_SPEED_CONFIG_SEQ].cfg_seq_size =
1012 sizeof(sata_and_sgmii_speed_config_params) /
1013 sizeof(struct op_params);
1014 serdes_seq_db[SGMII_1_25_SPEED_CONFIG_SEQ].data_arr_idx = SGMII;
1016 /* SGMII_3_125_SPEED_CONFIG_SEQ sequence init */
1017 serdes_seq_db[SGMII_3_125_SPEED_CONFIG_SEQ].op_params_ptr =
1018 sata_and_sgmii_speed_config_params;
1019 serdes_seq_db[SGMII_3_125_SPEED_CONFIG_SEQ].cfg_seq_size =
1020 sizeof(sata_and_sgmii_speed_config_params) /
1021 sizeof(struct op_params);
1022 serdes_seq_db[SGMII_3_125_SPEED_CONFIG_SEQ].data_arr_idx = SGMII_3_125;
1024 /* SGMII_ELECTRICAL_CONFIG_SEQ seq sequence init */
1025 if (serdes_rev == MV_SERDES_REV_1_2) {
1026 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
1027 sgmii_electrical_config_serdes_rev1_params;
1028 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
1029 sizeof(sgmii_electrical_config_serdes_rev1_params) /
1030 sizeof(struct op_params);
1032 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
1033 sgmii_electrical_config_serdes_rev2_params;
1034 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
1035 sizeof(sgmii_electrical_config_serdes_rev2_params) /
1036 sizeof(struct op_params);
1038 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].data_arr_idx = SGMII;
1040 /* SGMII_TX_CONFIG_SEQ sequence init */
1041 serdes_seq_db[SGMII_TX_CONFIG_SEQ1].op_params_ptr =
1042 sata_and_sgmii_tx_config_params1;
1043 serdes_seq_db[SGMII_TX_CONFIG_SEQ1].cfg_seq_size =
1044 sizeof(sata_and_sgmii_tx_config_params1) / sizeof(struct op_params);
1045 serdes_seq_db[SGMII_TX_CONFIG_SEQ1].data_arr_idx = SGMII;
1047 /* SGMII_TX_CONFIG_SEQ sequence init */
1048 if (serdes_rev == MV_SERDES_REV_1_2) {
1049 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].op_params_ptr =
1050 sata_and_sgmii_tx_config_serdes_rev1_params2;
1051 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].cfg_seq_size =
1052 sizeof(sata_and_sgmii_tx_config_serdes_rev1_params2) /
1053 sizeof(struct op_params);
1055 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].op_params_ptr =
1056 sata_and_sgmii_tx_config_serdes_rev2_params2;
1057 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].cfg_seq_size =
1058 sizeof(sata_and_sgmii_tx_config_serdes_rev2_params2) /
1059 sizeof(struct op_params);
1061 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].data_arr_idx = SGMII;
1063 /* PEX_POWER_UP_SEQ sequence init */
1064 if (serdes_rev == MV_SERDES_REV_1_2) {
1065 serdes_seq_db[PEX_POWER_UP_SEQ].op_params_ptr =
1066 pex_and_usb3_power_up_serdes_rev1_params;
1067 serdes_seq_db[PEX_POWER_UP_SEQ].cfg_seq_size =
1068 sizeof(pex_and_usb3_power_up_serdes_rev1_params) /
1069 sizeof(struct op_params);
1071 serdes_seq_db[PEX_POWER_UP_SEQ].op_params_ptr =
1072 pex_and_usb3_power_up_serdes_rev2_params;
1073 serdes_seq_db[PEX_POWER_UP_SEQ].cfg_seq_size =
1074 sizeof(pex_and_usb3_power_up_serdes_rev2_params) /
1075 sizeof(struct op_params);
1077 serdes_seq_db[PEX_POWER_UP_SEQ].data_arr_idx = PEX;
1079 /* PEX_2_5_SPEED_CONFIG_SEQ sequence init */
1080 serdes_seq_db[PEX_2_5_SPEED_CONFIG_SEQ].op_params_ptr =
1081 pex_and_usb3_speed_config_params;
1082 serdes_seq_db[PEX_2_5_SPEED_CONFIG_SEQ].cfg_seq_size =
1083 sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params);
1084 serdes_seq_db[PEX_2_5_SPEED_CONFIG_SEQ].data_arr_idx =
1085 PEXSERDES_SPEED_2_5_GBPS;
1087 /* PEX_5_SPEED_CONFIG_SEQ sequence init */
1088 serdes_seq_db[PEX_5_SPEED_CONFIG_SEQ].op_params_ptr =
1089 pex_and_usb3_speed_config_params;
1090 serdes_seq_db[PEX_5_SPEED_CONFIG_SEQ].cfg_seq_size =
1091 sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params);
1092 serdes_seq_db[PEX_5_SPEED_CONFIG_SEQ].data_arr_idx =
1093 PEXSERDES_SPEED_5_GBPS;
1095 /* PEX_ELECTRICAL_CONFIG_SEQ seq sequence init */
1096 if (serdes_rev == MV_SERDES_REV_1_2) {
1097 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
1098 pex_electrical_config_serdes_rev1_params;
1099 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
1100 sizeof(pex_electrical_config_serdes_rev1_params) /
1101 sizeof(struct op_params);
1103 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
1104 pex_electrical_config_serdes_rev2_params;
1105 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
1106 sizeof(pex_electrical_config_serdes_rev2_params) /
1107 sizeof(struct op_params);
1109 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].data_arr_idx = PEX;
1111 /* PEX_TX_CONFIG_SEQ1 sequence init */
1112 serdes_seq_db[PEX_TX_CONFIG_SEQ1].op_params_ptr =
1113 pex_and_usb3_tx_config_params1;
1114 serdes_seq_db[PEX_TX_CONFIG_SEQ1].cfg_seq_size =
1115 sizeof(pex_and_usb3_tx_config_params1) / sizeof(struct op_params);
1116 serdes_seq_db[PEX_TX_CONFIG_SEQ1].data_arr_idx = PEX;
1118 /* PEX_TX_CONFIG_SEQ2 sequence init */
1119 serdes_seq_db[PEX_TX_CONFIG_SEQ2].op_params_ptr =
1120 pex_and_usb3_tx_config_params2;
1121 serdes_seq_db[PEX_TX_CONFIG_SEQ2].cfg_seq_size =
1122 sizeof(pex_and_usb3_tx_config_params2) / sizeof(struct op_params);
1123 serdes_seq_db[PEX_TX_CONFIG_SEQ2].data_arr_idx = PEX;
1125 /* PEX_TX_CONFIG_SEQ3 sequence init */
1126 serdes_seq_db[PEX_TX_CONFIG_SEQ3].op_params_ptr =
1127 pex_and_usb3_tx_config_params3;
1128 serdes_seq_db[PEX_TX_CONFIG_SEQ3].cfg_seq_size =
1129 sizeof(pex_and_usb3_tx_config_params3) / sizeof(struct op_params);
1130 serdes_seq_db[PEX_TX_CONFIG_SEQ3].data_arr_idx = PEX;
1132 /* PEX_BY_4_CONFIG_SEQ sequence init */
1133 serdes_seq_db[PEX_BY_4_CONFIG_SEQ].op_params_ptr =
1134 pex_by4_config_params;
1135 serdes_seq_db[PEX_BY_4_CONFIG_SEQ].cfg_seq_size =
1136 sizeof(pex_by4_config_params) / sizeof(struct op_params);
1137 serdes_seq_db[PEX_BY_4_CONFIG_SEQ].data_arr_idx = PEX;
1139 /* PEX_CONFIG_REF_CLOCK_25MHZ_SEQ sequence init */
1140 serdes_seq_db[PEX_CONFIG_REF_CLOCK_25MHZ_SEQ].op_params_ptr =
1141 pex_config_ref_clock25_m_hz;
1142 serdes_seq_db[PEX_CONFIG_REF_CLOCK_25MHZ_SEQ].cfg_seq_size =
1143 sizeof(pex_config_ref_clock25_m_hz) / sizeof(struct op_params);
1144 serdes_seq_db[PEX_CONFIG_REF_CLOCK_25MHZ_SEQ].data_arr_idx = PEX;
1146 /* PEX_ELECTRICAL_CONFIG_REF_CLOCK_40MHZ_SEQ sequence init */
1147 serdes_seq_db[PEX_CONFIG_REF_CLOCK_40MHZ_SEQ].op_params_ptr =
1148 pex_config_ref_clock40_m_hz;
1149 serdes_seq_db[PEX_CONFIG_REF_CLOCK_40MHZ_SEQ].cfg_seq_size =
1150 sizeof(pex_config_ref_clock40_m_hz) / sizeof(struct op_params);
1151 serdes_seq_db[PEX_CONFIG_REF_CLOCK_40MHZ_SEQ].data_arr_idx = PEX;
1153 /* PEX_CONFIG_REF_CLOCK_100MHZ_SEQ sequence init */
1154 serdes_seq_db[PEX_CONFIG_REF_CLOCK_100MHZ_SEQ].op_params_ptr =
1155 pex_config_ref_clock100_m_hz;
1156 serdes_seq_db[PEX_CONFIG_REF_CLOCK_100MHZ_SEQ].cfg_seq_size =
1157 sizeof(pex_config_ref_clock100_m_hz) / sizeof(struct op_params);
1158 serdes_seq_db[PEX_CONFIG_REF_CLOCK_100MHZ_SEQ].data_arr_idx = PEX;
1160 /* USB3_POWER_UP_SEQ sequence init */
1161 if (serdes_rev == MV_SERDES_REV_1_2) {
1162 serdes_seq_db[USB3_POWER_UP_SEQ].op_params_ptr =
1163 pex_and_usb3_power_up_serdes_rev1_params;
1164 serdes_seq_db[USB3_POWER_UP_SEQ].cfg_seq_size =
1165 sizeof(pex_and_usb3_power_up_serdes_rev1_params) /
1166 sizeof(struct op_params);
1168 serdes_seq_db[USB3_POWER_UP_SEQ].op_params_ptr =
1169 pex_and_usb3_power_up_serdes_rev2_params;
1170 serdes_seq_db[USB3_POWER_UP_SEQ].cfg_seq_size =
1171 sizeof(pex_and_usb3_power_up_serdes_rev2_params) /
1172 sizeof(struct op_params);
1174 serdes_seq_db[USB3_POWER_UP_SEQ].data_arr_idx = USB3;
1176 /* USB3_HOST_SPEED_CONFIG_SEQ sequence init */
1177 serdes_seq_db[USB3_HOST_SPEED_CONFIG_SEQ].op_params_ptr =
1178 pex_and_usb3_speed_config_params;
1179 serdes_seq_db[USB3_HOST_SPEED_CONFIG_SEQ].cfg_seq_size =
1180 sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params);
1181 serdes_seq_db[USB3_HOST_SPEED_CONFIG_SEQ].data_arr_idx =
1182 USB3SERDES_SPEED_5_GBPS_HOST;
1184 /* USB3_DEVICE_SPEED_CONFIG_SEQ sequence init */
1185 serdes_seq_db[USB3_DEVICE_SPEED_CONFIG_SEQ].op_params_ptr =
1186 pex_and_usb3_speed_config_params;
1187 serdes_seq_db[USB3_DEVICE_SPEED_CONFIG_SEQ].cfg_seq_size =
1188 sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params);
1189 serdes_seq_db[USB3_DEVICE_SPEED_CONFIG_SEQ].data_arr_idx =
1190 USB3SERDES_SPEED_5_GBPS_DEVICE;
1192 /* USB3_ELECTRICAL_CONFIG_SEQ seq sequence init */
1193 if (serdes_rev == MV_SERDES_REV_1_2) {
1194 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
1195 usb3_electrical_config_serdes_rev1_params;
1196 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
1197 sizeof(usb3_electrical_config_serdes_rev1_params) /
1198 sizeof(struct op_params);
1200 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
1201 usb3_electrical_config_serdes_rev2_params;
1202 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
1203 sizeof(usb3_electrical_config_serdes_rev2_params) /
1204 sizeof(struct op_params);
1206 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].data_arr_idx = USB3;
1208 /* USB3_TX_CONFIG_SEQ sequence init */
1209 serdes_seq_db[USB3_TX_CONFIG_SEQ1].op_params_ptr =
1210 pex_and_usb3_tx_config_params1;
1211 serdes_seq_db[USB3_TX_CONFIG_SEQ1].cfg_seq_size =
1212 sizeof(pex_and_usb3_tx_config_params1) / sizeof(struct op_params);
1213 serdes_seq_db[USB3_TX_CONFIG_SEQ1].data_arr_idx = USB3;
1215 /* USB3_TX_CONFIG_SEQ sequence init */
1216 serdes_seq_db[USB3_TX_CONFIG_SEQ2].op_params_ptr =
1217 pex_and_usb3_tx_config_params2;
1218 serdes_seq_db[USB3_TX_CONFIG_SEQ2].cfg_seq_size =
1219 sizeof(pex_and_usb3_tx_config_params2) / sizeof(struct op_params);
1220 serdes_seq_db[USB3_TX_CONFIG_SEQ2].data_arr_idx = USB3;
1222 /* USB3_TX_CONFIG_SEQ sequence init */
1223 serdes_seq_db[USB3_TX_CONFIG_SEQ3].op_params_ptr =
1224 pex_and_usb3_tx_config_params3;
1225 serdes_seq_db[USB3_TX_CONFIG_SEQ3].cfg_seq_size =
1226 sizeof(pex_and_usb3_tx_config_params3) / sizeof(struct op_params);
1227 serdes_seq_db[USB3_TX_CONFIG_SEQ3].data_arr_idx = USB3;
1229 /* USB2_POWER_UP_SEQ sequence init */
1230 serdes_seq_db[USB2_POWER_UP_SEQ].op_params_ptr = usb2_power_up_params;
1231 serdes_seq_db[USB2_POWER_UP_SEQ].cfg_seq_size =
1232 sizeof(usb2_power_up_params) / sizeof(struct op_params);
1233 serdes_seq_db[USB2_POWER_UP_SEQ].data_arr_idx = 0;
1235 /* USB3_DEVICE_CONFIG_SEQ sequence init */
1236 serdes_seq_db[USB3_DEVICE_CONFIG_SEQ].op_params_ptr =
1237 usb3_device_config_params;
1238 serdes_seq_db[USB3_DEVICE_CONFIG_SEQ].cfg_seq_size =
1239 sizeof(usb3_device_config_params) / sizeof(struct op_params);
1240 serdes_seq_db[USB3_DEVICE_CONFIG_SEQ].data_arr_idx = 0; /* Not relevant */
1242 /* SERDES_POWER_DOWN_SEQ sequence init */
1243 serdes_seq_db[SERDES_POWER_DOWN_SEQ].op_params_ptr =
1244 serdes_power_down_params;
1245 serdes_seq_db[SERDES_POWER_DOWN_SEQ].cfg_seq_size =
1246 sizeof(serdes_power_down_params) /
1247 sizeof(struct op_params);
1248 serdes_seq_db[SERDES_POWER_DOWN_SEQ].data_arr_idx = FIRST_CELL;
1250 if (serdes_rev == MV_SERDES_REV_2_1) {
1251 /* QSGMII_POWER_UP_SEQ sequence init */
1252 serdes_seq_db[QSGMII_POWER_UP_SEQ].op_params_ptr =
1253 qsgmii_port_power_up_params;
1254 serdes_seq_db[QSGMII_POWER_UP_SEQ].cfg_seq_size =
1255 sizeof(qsgmii_port_power_up_params) /
1256 sizeof(struct op_params);
1257 serdes_seq_db[QSGMII_POWER_UP_SEQ].data_arr_idx =
1260 /* QSGMII_5_SPEED_CONFIG_SEQ sequence init */
1261 serdes_seq_db[QSGMII_5_SPEED_CONFIG_SEQ].op_params_ptr =
1262 qsgmii_port_speed_config_params;
1263 serdes_seq_db[QSGMII_5_SPEED_CONFIG_SEQ].cfg_seq_size =
1264 sizeof(qsgmii_port_speed_config_params) /
1265 sizeof(struct op_params);
1266 serdes_seq_db[QSGMII_5_SPEED_CONFIG_SEQ].data_arr_idx =
1269 /* QSGMII_ELECTRICAL_CONFIG_SEQ seq sequence init */
1270 serdes_seq_db[QSGMII_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
1271 qsgmii_port_electrical_config_params;
1272 serdes_seq_db[QSGMII_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
1273 sizeof(qsgmii_port_electrical_config_params) /
1274 sizeof(struct op_params);
1275 serdes_seq_db[QSGMII_ELECTRICAL_CONFIG_SEQ].data_arr_idx =
1278 /* QSGMII_TX_CONFIG_SEQ sequence init */
1279 serdes_seq_db[QSGMII_TX_CONFIG_SEQ1].op_params_ptr =
1280 qsgmii_port_tx_config_params1;
1281 serdes_seq_db[QSGMII_TX_CONFIG_SEQ1].cfg_seq_size =
1282 sizeof(qsgmii_port_tx_config_params1) /
1283 sizeof(struct op_params);
1284 serdes_seq_db[QSGMII_TX_CONFIG_SEQ1].data_arr_idx =
1287 /* QSGMII_TX_CONFIG_SEQ sequence init */
1288 serdes_seq_db[QSGMII_TX_CONFIG_SEQ2].op_params_ptr =
1289 qsgmii_port_tx_config_params2;
1290 serdes_seq_db[QSGMII_TX_CONFIG_SEQ2].cfg_seq_size =
1291 sizeof(qsgmii_port_tx_config_params2) /
1292 sizeof(struct op_params);
1293 serdes_seq_db[QSGMII_TX_CONFIG_SEQ2].data_arr_idx =
1300 enum serdes_seq serdes_type_and_speed_to_speed_seq(enum serdes_type serdes_type,
1301 enum serdes_speed baud_rate)
1303 enum serdes_seq seq_id = SERDES_LAST_SEQ;
1305 DEBUG_INIT_FULL_S("\n### serdes_type_and_speed_to_speed_seq ###\n");
1306 switch (serdes_type) {
1311 if (baud_rate == SERDES_SPEED_2_5_GBPS)
1312 seq_id = PEX_2_5_SPEED_CONFIG_SEQ;
1313 else if (baud_rate == SERDES_SPEED_5_GBPS)
1314 seq_id = PEX_5_SPEED_CONFIG_SEQ;
1318 if (baud_rate == SERDES_SPEED_5_GBPS)
1319 seq_id = USB3_HOST_SPEED_CONFIG_SEQ;
1322 if (baud_rate == SERDES_SPEED_5_GBPS)
1323 seq_id = USB3_DEVICE_SPEED_CONFIG_SEQ;
1329 if (baud_rate == SERDES_SPEED_1_5_GBPS)
1330 seq_id = SATA_1_5_SPEED_CONFIG_SEQ;
1331 else if (baud_rate == SERDES_SPEED_3_GBPS)
1332 seq_id = SATA_3_SPEED_CONFIG_SEQ;
1333 else if (baud_rate == SERDES_SPEED_6_GBPS)
1334 seq_id = SATA_6_SPEED_CONFIG_SEQ;
1339 #ifdef CONFIG_ARMADA_39X
1342 if (baud_rate == SERDES_SPEED_1_25_GBPS)
1343 seq_id = SGMII_1_25_SPEED_CONFIG_SEQ;
1344 else if (baud_rate == SERDES_SPEED_3_125_GBPS)
1345 seq_id = SGMII_3_125_SPEED_CONFIG_SEQ;
1348 seq_id = QSGMII_5_SPEED_CONFIG_SEQ;
1350 #ifdef CONFIG_ARMADA_39X
1352 seq_id = XAUI_3_125_SPEED_CONFIG_SEQ;
1355 seq_id = RXAUI_6_25_SPEED_CONFIG_SEQ;
1359 return SERDES_LAST_SEQ;
1365 void print_topology_details(struct serdes_map *serdes_map_array)
1369 DEBUG_INIT_S("board SerDes lanes topology details:\n");
1371 DEBUG_INIT_S(" | Lane # | Speed | Type |\n");
1372 DEBUG_INIT_S(" --------------------------------\n");
1373 for (lane_num = 0; lane_num < hws_serdes_get_max_lane(); lane_num++) {
1374 if (serdes_map_array[lane_num].serdes_type == DEFAULT_SERDES)
1376 DEBUG_INIT_S(" | ");
1377 DEBUG_INIT_D(hws_get_physical_serdes_num(lane_num), 1);
1378 DEBUG_INIT_S(" | ");
1379 DEBUG_INIT_D(serdes_map_array[lane_num].serdes_speed, 2);
1380 DEBUG_INIT_S(" | ");
1381 DEBUG_INIT_S((char *)
1382 serdes_type_to_string[serdes_map_array[lane_num].
1384 DEBUG_INIT_S("\t|\n");
1386 DEBUG_INIT_S(" --------------------------------\n");
1389 int hws_pre_serdes_init_config(void)
1394 * Configure Core PLL
1397 * set PLL parameters
1398 * bits[2:0] =0x3 (Core-PLL Kdiv)
1399 * bits[20:12]=0x9f (Core-PLL Ndiv)
1400 * bits[24:21]=0x7(Core-PLL VCO Band)
1401 * bits[28:25]=0x1(Core-PLL Rlf)
1402 * bits[31:29]=0x2(Core-PLL charge-pump adjust)
1404 reg_write(CORE_PLL_PARAMETERS_REG, 0x42e9f003);
1406 /* Enable PLL Configuration */
1407 data = reg_read(CORE_PLL_CONFIG_REG);
1408 data = SET_BIT(data, 9);
1409 reg_write(CORE_PLL_CONFIG_REG, data);
1414 int serdes_phy_config(void)
1416 DEBUG_INIT_FULL_S("\n### ctrl_high_speed_serdes_phy_config ###\n");
1418 DEBUG_INIT_S("High speed PHY - Version: ");
1419 DEBUG_INIT_S(SERDES_VERION);
1422 /* Init serdes sequences DB */
1423 if (hws_serdes_seq_init() != MV_OK) {
1424 printf("hws_ctrl_high_speed_serdes_phy_config: Error: Serdes initialization fail\n");
1428 /* Board topology load */
1430 ("ctrl_high_speed_serdes_phy_config: Loading board topology..\n");
1431 CHECK_STATUS(hws_board_topology_load(serdes_configuration_map));
1433 /* print topology */
1434 print_topology_details(serdes_configuration_map);
1435 CHECK_STATUS(hws_pre_serdes_init_config());
1437 /* Power-Up sequence */
1439 ("ctrl_high_speed_serdes_phy_config: Starting serdes power up sequence\n");
1441 CHECK_STATUS(hws_power_up_serdes_lanes(serdes_configuration_map));
1444 ("\n### ctrl_high_speed_serdes_phy_config ended successfully ###\n");
1446 DEBUG_INIT_S(ENDED_OK);
1451 int serdes_polarity_config(u32 serdes_num, int is_rx)
1455 u8 bit_off = (is_rx) ? 11 : 10;
1457 reg_addr = SERDES_REGS_LANE_BASE_OFFSET(serdes_num) + SYNC_PATTERN_REG;
1458 data = reg_read(reg_addr);
1459 data = SET_BIT(data, bit_off);
1460 reg_write(reg_addr, data);
1465 int hws_power_up_serdes_lanes(struct serdes_map *serdes_config_map)
1467 u32 serdes_id, serdes_lane_num;
1468 enum ref_clock ref_clock;
1469 enum serdes_type serdes_type;
1470 enum serdes_speed serdes_speed;
1471 enum serdes_mode serdes_mode;
1472 int serdes_rx_polarity_swap;
1473 int serdes_tx_polarity_swap;
1474 int is_pex_enabled = 0;
1478 * Flag which indicates that one of the Serdes is of PEX.
1479 * In this case, PEX unit will be initialized after Serdes power-up
1482 DEBUG_INIT_FULL_S("\n### hws_power_up_serdes_lanes ###\n");
1484 /* COMMON PHYS SELECTORS register configuration */
1486 ("hws_power_up_serdes_lanes: Updating COMMON PHYS SELECTORS reg\n");
1487 CHECK_STATUS(hws_update_serdes_phy_selectors(serdes_configuration_map));
1489 /* per Serdes Power Up */
1490 for (serdes_id = 0; serdes_id < hws_serdes_get_max_lane();
1493 ("calling serdes_power_up_ctrl: serdes lane number ");
1494 DEBUG_INIT_FULL_D_10(serdes_lane_num, 1);
1495 DEBUG_INIT_FULL_S("\n");
1497 serdes_lane_num = hws_get_physical_serdes_num(serdes_id);
1498 serdes_type = serdes_config_map[serdes_id].serdes_type;
1499 serdes_speed = serdes_config_map[serdes_id].serdes_speed;
1500 serdes_mode = serdes_config_map[serdes_id].serdes_mode;
1501 serdes_rx_polarity_swap = serdes_config_map[serdes_id].swap_rx;
1502 serdes_tx_polarity_swap = serdes_config_map[serdes_id].swap_tx;
1504 /* serdes lane is not in use */
1505 if (serdes_type == DEFAULT_SERDES)
1507 else if (serdes_type <= PEX3) /* PEX type */
1510 ref_clock = hws_serdes_get_ref_clock_val(serdes_type);
1511 if (ref_clock == REF_CLOCK_UNSUPPORTED) {
1513 ("hws_power_up_serdes_lanes: unsupported ref clock\n");
1514 return MV_NOT_SUPPORTED;
1516 CHECK_STATUS(serdes_power_up_ctrl(serdes_lane_num,
1520 serdes_mode, ref_clock));
1522 /* RX Polarity config */
1523 if (serdes_rx_polarity_swap)
1524 CHECK_STATUS(serdes_polarity_config
1525 (serdes_lane_num, 1));
1527 /* TX Polarity config */
1528 if (serdes_tx_polarity_swap)
1529 CHECK_STATUS(serdes_polarity_config
1530 (serdes_lane_num, 0));
1533 if (is_pex_enabled) {
1534 /* Set PEX_TX_CONFIG_SEQ sequence for PEXx4 mode.
1535 After finish the Power_up sequence for all lanes,
1536 the lanes should be released from reset state. */
1537 CHECK_STATUS(hws_pex_tx_config_seq(serdes_config_map));
1539 /* PEX configuration */
1540 CHECK_STATUS(hws_pex_config(serdes_config_map));
1543 /* USB2 configuration */
1544 DEBUG_INIT_FULL_S("hws_power_up_serdes_lanes: init USB2 Phys\n");
1545 CHECK_STATUS(mv_seq_exec(0 /* not relevant */ , USB2_POWER_UP_SEQ));
1548 ("### hws_power_up_serdes_lanes ended successfully ###\n");
1553 int ctrl_high_speed_serdes_phy_config(void)
1555 return hws_ctrl_high_speed_serdes_phy_config();
1558 static int serdes_pex_usb3_pipe_delay_w_a(u32 serdes_num, u8 serdes_type)
1562 /* WA for A380 Z1 relevant for lanes 3,4,5 only */
1563 if (serdes_num >= 3) {
1564 reg_data = reg_read(GENERAL_PURPOSE_RESERVED0_REG);
1565 /* set delay on pipe -
1566 * When lane 3 is connected to a MAC of Pex -> set bit 7 to 1.
1567 * When lane 3 is connected to a MAC of USB3 -> set bit 7 to 0.
1568 * When lane 4 is connected to a MAC of Pex -> set bit 8 to 1.
1569 * When lane 4 is connected to a MAC of USB3 -> set bit 8 to 0.
1570 * When lane 5 is connected to a MAC of Pex -> set bit 8 to 1.
1571 * When lane 5 is connected to a MAC of USB3 -> set bit 8 to 0.
1573 if (serdes_type == PEX)
1574 reg_data |= 1 << (7 + (serdes_num - 3));
1575 if (serdes_type == USB3) {
1577 reg_data &= ~(1 << (7 + (serdes_num - 3)));
1579 reg_write(GENERAL_PURPOSE_RESERVED0_REG, reg_data);
1586 * hws_serdes_pex_ref_clock_satr_get -
1588 * DESCRIPTION: Get the reference clock value from DEVICE_SAMPLE_AT_RESET1_REG
1590 * bit[2] for PEX#0, bit[3] for PEX#1, bit[30] for PEX#2, bit[31]
1592 * If bit=0 --> REF_CLOCK_100MHz
1593 * If bit=1 && DEVICE_SAMPLE_AT_RESET2_REG bit[0]=0
1594 * --> REF_CLOCK_25MHz
1595 * If bit=1 && DEVICE_SAMPLE_AT_RESET2_REG bit[0]=1
1596 * --> REF_CLOCK_40MHz
1598 * INPUT: serdes_type - Type of Serdes
1600 * OUTPUT: pex_satr - Return the REF_CLOCK value:
1601 * REF_CLOCK_25MHz, REF_CLOCK_40MHz or REF_CLOCK_100MHz
1603 * RETURNS: MV_OK - for success
1604 * MV_BAD_PARAM - for fail
1606 int hws_serdes_pex_ref_clock_satr_get(enum serdes_type serdes_type, u32 *pex_satr)
1608 u32 data, reg_satr1;
1610 reg_satr1 = reg_read(DEVICE_SAMPLE_AT_RESET1_REG);
1612 switch (serdes_type) {
1614 data = REF_CLK_SELECTOR_VAL_PEX0(reg_satr1);
1617 data = REF_CLK_SELECTOR_VAL_PEX1(reg_satr1);
1620 data = REF_CLK_SELECTOR_VAL_PEX2(reg_satr1);
1623 data = REF_CLK_SELECTOR_VAL_PEX3(reg_satr1);
1626 printf("%s: Error: SerDes type %d is not supported\n",
1627 __func__, serdes_type);
1628 return MV_BAD_PARAM;
1636 u32 hws_serdes_get_ref_clock_val(enum serdes_type serdes_type)
1639 enum ref_clock ref_clock;
1641 DEBUG_INIT_FULL_S("\n### hws_serdes_get_ref_clock_val ###\n");
1643 if (serdes_type >= LAST_SERDES_TYPE)
1644 return REF_CLOCK_UNSUPPORTED;
1646 /* read ref clock from S@R */
1647 ref_clock = hws_serdes_silicon_ref_clock_get();
1649 if (serdes_type > PEX3) {
1650 /* for all Serdes types but PCIe */
1654 /* for PCIe, need also to check PCIe S@R */
1655 CHECK_STATUS(hws_serdes_pex_ref_clock_satr_get
1656 (serdes_type, &pex_satr));
1658 if (pex_satr == 0) {
1659 return REF_CLOCK_100MHZ;
1660 } else if (pex_satr == 1) {
1661 /* value of 1 means we can use ref clock from SoC (as other Serdes types) */
1665 ("%s: Error: REF_CLK_SELECTOR_VAL for SerDes type %d is wrong\n",
1666 __func__, serdes_type);
1667 return REF_CLOCK_UNSUPPORTED;
1671 int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up,
1672 enum serdes_type serdes_type,
1673 enum serdes_speed baud_rate,
1674 enum serdes_mode serdes_mode, enum ref_clock ref_clock)
1676 u32 sata_idx, pex_idx, sata_port;
1677 enum serdes_seq speed_seq_id;
1681 DEBUG_INIT_FULL_S("\n### serdes_power_up_ctrl ###\n");
1683 if (serdes_power_up == 1) { /* Serdes power up */
1685 ("serdes_power_up_ctrl: executing power up.. ");
1686 DEBUG_INIT_FULL_C("serdes num = ", serdes_num, 2);
1687 DEBUG_INIT_FULL_C("serdes type = ", serdes_type, 2);
1689 DEBUG_INIT_FULL_S("Going access 1");
1691 /* Getting the Speed Select sequence id */
1693 serdes_type_and_speed_to_speed_seq(serdes_type,
1695 if (speed_seq_id == SERDES_LAST_SEQ) {
1697 ("serdes_power_up_ctrl: serdes type %d and speed %d are not supported together\n",
1698 serdes_type, baud_rate);
1700 return MV_BAD_PARAM;
1703 /* Executing power up, ref clock set, speed config and TX config */
1704 switch (serdes_type) {
1709 if (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2) {
1710 CHECK_STATUS(serdes_pex_usb3_pipe_delay_w_a
1714 is_pex_by1 = (serdes_mode == PEX_ROOT_COMPLEX_X1) ||
1715 (serdes_mode == PEX_END_POINT_X1);
1716 pex_idx = serdes_type - PEX0;
1718 if ((is_pex_by1 == 1) || (serdes_type == PEX0)) {
1719 /* For PEX by 4, init only the PEX 0 */
1720 reg_data = reg_read(SOC_CONTROL_REG1);
1721 if (is_pex_by1 == 1)
1724 reg_data &= ~0x4000;
1725 reg_write(SOC_CONTROL_REG1, reg_data);
1728 reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
1731 if (is_pex_by1 == 1)
1735 reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
1739 reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
1743 reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
1747 reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
1751 reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x70),
1755 CHECK_STATUS(mv_seq_exec(serdes_num, PEX_POWER_UP_SEQ));
1756 if (is_pex_by1 == 0) {
1758 * for PEX by 4 - use the PEX index as the
1761 serdes_seq_db[PEX_BY_4_CONFIG_SEQ].
1762 data_arr_idx = pex_idx;
1763 CHECK_STATUS(mv_seq_exec
1764 (serdes_num, PEX_BY_4_CONFIG_SEQ));
1767 CHECK_STATUS(hws_ref_clock_set
1768 (serdes_num, serdes_type, ref_clock));
1769 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
1770 CHECK_STATUS(mv_seq_exec
1771 (serdes_num, PEX_ELECTRICAL_CONFIG_SEQ));
1773 if (is_pex_by1 == 1) {
1774 CHECK_STATUS(mv_seq_exec
1775 (serdes_num, PEX_TX_CONFIG_SEQ2));
1776 CHECK_STATUS(mv_seq_exec
1777 (serdes_num, PEX_TX_CONFIG_SEQ3));
1778 CHECK_STATUS(mv_seq_exec
1779 (serdes_num, PEX_TX_CONFIG_SEQ1));
1787 if (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2) {
1788 CHECK_STATUS(serdes_pex_usb3_pipe_delay_w_a
1789 (serdes_num, USB3));
1791 CHECK_STATUS(mv_seq_exec
1792 (serdes_num, USB3_POWER_UP_SEQ));
1793 CHECK_STATUS(hws_ref_clock_set
1794 (serdes_num, serdes_type, ref_clock));
1795 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
1796 if (serdes_type == USB3_DEVICE) {
1797 CHECK_STATUS(mv_seq_exec
1799 USB3_DEVICE_CONFIG_SEQ));
1801 CHECK_STATUS(mv_seq_exec
1802 (serdes_num, USB3_ELECTRICAL_CONFIG_SEQ));
1803 CHECK_STATUS(mv_seq_exec
1804 (serdes_num, USB3_TX_CONFIG_SEQ1));
1805 CHECK_STATUS(mv_seq_exec
1806 (serdes_num, USB3_TX_CONFIG_SEQ2));
1807 CHECK_STATUS(mv_seq_exec
1808 (serdes_num, USB3_TX_CONFIG_SEQ3));
1816 sata_idx = ((serdes_type == SATA0) ||
1817 (serdes_type == SATA1)) ? 0 : 1;
1818 sata_port = ((serdes_type == SATA0) ||
1819 (serdes_type == SATA2)) ? 0 : 1;
1821 CHECK_STATUS(mv_seq_exec
1822 (sata_idx, (sata_port == 0) ?
1823 SATA_PORT_0_ONLY_POWER_UP_SEQ :
1824 SATA_PORT_1_ONLY_POWER_UP_SEQ));
1825 CHECK_STATUS(mv_seq_exec
1826 (serdes_num, SATA_POWER_UP_SEQ));
1827 CHECK_STATUS(hws_ref_clock_set
1828 (serdes_num, serdes_type, ref_clock));
1829 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
1830 CHECK_STATUS(mv_seq_exec
1831 (serdes_num, SATA_ELECTRICAL_CONFIG_SEQ));
1832 CHECK_STATUS(mv_seq_exec
1833 (serdes_num, SATA_TX_CONFIG_SEQ1));
1834 CHECK_STATUS(mv_seq_exec
1835 (sata_idx, (sata_port == 0) ?
1836 SATA_PORT_0_ONLY_TX_CONFIG_SEQ :
1837 SATA_PORT_1_ONLY_TX_CONFIG_SEQ));
1838 CHECK_STATUS(mv_seq_exec
1839 (serdes_num, SATA_TX_CONFIG_SEQ2));
1846 CHECK_STATUS(mv_seq_exec
1847 (serdes_num, SGMII_POWER_UP_SEQ));
1848 CHECK_STATUS(hws_ref_clock_set
1849 (serdes_num, serdes_type, ref_clock));
1850 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
1851 CHECK_STATUS(mv_seq_exec
1852 (serdes_num, SGMII_ELECTRICAL_CONFIG_SEQ));
1853 CHECK_STATUS(mv_seq_exec
1854 (serdes_num, SGMII_TX_CONFIG_SEQ1));
1855 CHECK_STATUS(mv_seq_exec
1856 (serdes_num, SGMII_TX_CONFIG_SEQ2));
1858 /* GBE configuration */
1859 reg_data = reg_read(GBE_CONFIGURATION_REG);
1860 /* write the SGMII index */
1861 reg_data |= 0x1 << (serdes_type - SGMII0);
1862 reg_write(GBE_CONFIGURATION_REG, reg_data);
1866 if (hws_ctrl_serdes_rev_get() < MV_SERDES_REV_2_1)
1867 return MV_NOT_SUPPORTED;
1869 CHECK_STATUS(mv_seq_exec
1870 (serdes_num, QSGMII_POWER_UP_SEQ));
1871 CHECK_STATUS(hws_ref_clock_set
1872 (serdes_num, serdes_type, ref_clock));
1873 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
1874 CHECK_STATUS(mv_seq_exec
1876 QSGMII_ELECTRICAL_CONFIG_SEQ));
1877 CHECK_STATUS(mv_seq_exec
1878 (serdes_num, QSGMII_TX_CONFIG_SEQ1));
1879 CHECK_STATUS(mv_seq_exec
1880 (serdes_num, QSGMII_TX_CONFIG_SEQ2));
1885 CHECK_STATUS(serdes_power_up_ctrl_ext
1886 (serdes_num, serdes_power_up, serdes_type,
1887 baud_rate, serdes_mode, ref_clock));
1891 ("serdes_power_up_ctrl: bad serdes_type parameter\n");
1892 return MV_BAD_PARAM;
1894 } else { /* Serdes power down */
1895 DEBUG_INIT_FULL_S("serdes_power_up: executing power down.. ");
1896 DEBUG_INIT_FULL_C("serdes num = ", serdes_num, 1);
1898 CHECK_STATUS(mv_seq_exec(serdes_num, SERDES_POWER_DOWN_SEQ));
1902 "serdes_power_up_ctrl ended successfully for serdes ",
1908 int hws_update_serdes_phy_selectors(struct serdes_map *serdes_config_map)
1910 u32 lane_data, idx, serdes_lane_hw_num, reg_data = 0;
1911 enum serdes_type serdes_type;
1912 enum serdes_mode serdes_mode;
1915 int updated_topology_print = 0;
1917 DEBUG_INIT_FULL_S("\n### hws_update_serdes_phy_selectors ###\n");
1919 ("Updating the COMMON PHYS SELECTORS register with the serdes types\n");
1921 if (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2)
1927 * Updating bits 0-17 in the COMMON PHYS SELECTORS register
1928 * according to the serdes types
1930 for (idx = 0; idx < hws_serdes_get_max_lane();
1932 serdes_type = serdes_config_map[idx].serdes_type;
1933 serdes_mode = serdes_config_map[idx].serdes_mode;
1934 serdes_lane_hw_num = hws_get_physical_serdes_num(idx);
1937 hws_serdes_get_phy_selector_val(serdes_lane_hw_num,
1940 if (serdes_type == DEFAULT_SERDES)
1943 if (hws_serdes_topology_verify
1944 (serdes_type, idx, serdes_mode) != MV_OK) {
1945 serdes_config_map[idx].serdes_type =
1947 printf("%s: SerDes lane #%d is disabled\n", __func__,
1948 serdes_lane_hw_num);
1949 updated_topology_print = 1;
1954 * Checking if the board topology configuration includes
1955 * PEXx4 - for the next step
1957 if ((serdes_mode == PEX_END_POINT_X4) ||
1958 (serdes_mode == PEX_ROOT_COMPLEX_X4)) {
1959 /* update lane data to the 3 next SERDES lanes */
1961 common_phys_selectors_pex_by4_lanes
1962 [serdes_lane_hw_num];
1963 if (serdes_type == PEX0)
1967 if (lane_data == NA) {
1969 ("%s: Warning: SerDes lane #%d and type %d are not supported together\n",
1970 __func__, serdes_lane_hw_num, serdes_mode);
1971 serdes_config_map[idx].serdes_type =
1973 printf("%s: SerDes lane #%d is disabled\n", __func__,
1974 serdes_lane_hw_num);
1979 * Updating the data that will be written to
1980 * COMMON_PHYS_SELECTORS_REG
1982 reg_data |= (lane_data <<
1983 (select_bit_off * serdes_lane_hw_num));
1987 * Check that number of used lanes for XAUI and RXAUI
1988 * (if used) is right
1990 hws_serdes_xaui_topology_verify();
1992 /* Print topology */
1993 if (updated_topology_print)
1994 print_topology_details(serdes_config_map);
1997 * Updating the PEXx4 Enable bit in the COMMON PHYS SELECTORS
1998 * register for PEXx4 mode
2000 reg_data |= (is_pex_x4 == 1) ? (0x1 << PEX_X4_ENABLE_OFFS) : 0;
2002 /* Updating the COMMON PHYS SELECTORS register */
2003 reg_write(COMMON_PHYS_SELECTORS_REG, reg_data);
2008 int hws_ref_clock_set(u32 serdes_num, enum serdes_type serdes_type,
2009 enum ref_clock ref_clock)
2011 u32 data1 = 0, data2 = 0, data3 = 0, reg_data;
2013 DEBUG_INIT_FULL_S("\n### hws_ref_clock_set ###\n");
2015 if (hws_is_serdes_active(serdes_num) != 1) {
2016 printf("%s: SerDes lane #%d is not Active\n", __func__,
2018 return MV_BAD_PARAM;
2021 switch (serdes_type) {
2026 switch (ref_clock) {
2027 case REF_CLOCK_25MHZ:
2028 CHECK_STATUS(mv_seq_exec
2030 PEX_CONFIG_REF_CLOCK_25MHZ_SEQ));
2032 case REF_CLOCK_100MHZ:
2033 CHECK_STATUS(mv_seq_exec
2035 PEX_CONFIG_REF_CLOCK_100MHZ_SEQ));
2037 #ifdef CONFIG_ARMADA_39X
2038 case REF_CLOCK_40MHZ:
2039 CHECK_STATUS(mv_seq_exec
2041 PEX_CONFIG_REF_CLOCK_40MHZ_SEQ));
2046 ("%s: Error: ref_clock %d for SerDes lane #%d, type %d is not supported\n",
2047 __func__, ref_clock, serdes_num, serdes_type);
2048 return MV_BAD_PARAM;
2053 if (ref_clock == REF_CLOCK_25MHZ) {
2054 data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_2;
2055 data2 = GLOBAL_PM_CTRL_REG_25MHZ_VAL;
2056 data3 = LANE_CFG4_REG_25MHZ_VAL;
2057 } else if (ref_clock == REF_CLOCK_40MHZ) {
2058 data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL;
2059 data2 = GLOBAL_PM_CTRL_REG_40MHZ_VAL;
2060 data3 = LANE_CFG4_REG_40MHZ_VAL;
2063 ("hws_ref_clock_set: ref clock is not valid for serdes type %d\n",
2065 return MV_BAD_PARAM;
2076 if (ref_clock == REF_CLOCK_25MHZ) {
2077 data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1;
2078 } else if (ref_clock == REF_CLOCK_40MHZ) {
2079 data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL;
2082 ("hws_ref_clock_set: ref clock is not valid for serdes type %d\n",
2084 return MV_BAD_PARAM;
2087 #ifdef CONFIG_ARMADA_39X
2091 if (ref_clock == REF_CLOCK_25MHZ) {
2092 data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1;
2093 } else if (ref_clock == REF_CLOCK_40MHZ) {
2094 data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL;
2097 ("hws_ref_clock_set: ref clock is not valid for serdes type %d\n",
2099 return MV_BAD_PARAM;
2104 DEBUG_INIT_S("hws_ref_clock_set: not supported serdes type\n");
2105 return MV_BAD_PARAM;
2109 * Write the ref_clock to relevant SELECT_REF_CLOCK_REG bits and
2112 reg_data = reg_read(POWER_AND_PLL_CTRL_REG +
2113 SERDES_REGS_LANE_BASE_OFFSET(serdes_num));
2114 reg_data &= POWER_AND_PLL_CTRL_REG_MASK;
2116 reg_write(POWER_AND_PLL_CTRL_REG +
2117 SERDES_REGS_LANE_BASE_OFFSET(serdes_num), reg_data);
2119 if ((serdes_type == USB3_HOST0) || (serdes_type == USB3_HOST1) ||
2120 (serdes_type == USB3_DEVICE)) {
2121 reg_data = reg_read(GLOBAL_PM_CTRL +
2122 SERDES_REGS_LANE_BASE_OFFSET(serdes_num));
2123 reg_data &= GLOBAL_PM_CTRL_REG_MASK;
2125 reg_write(GLOBAL_PM_CTRL +
2126 SERDES_REGS_LANE_BASE_OFFSET(serdes_num), reg_data);
2128 reg_data = reg_read(LANE_CFG4_REG +
2129 SERDES_REGS_LANE_BASE_OFFSET(serdes_num));
2130 reg_data &= LANE_CFG4_REG_MASK;
2132 reg_write(LANE_CFG4_REG +
2133 SERDES_REGS_LANE_BASE_OFFSET(serdes_num), reg_data);
2140 * hws_pex_tx_config_seq -
2142 * DESCRIPTION: Set PEX_TX_CONFIG_SEQ sequence init for PEXx4 mode
2143 * INPUT: serdes_map - The board topology map
2145 * RETURNS: MV_OK - for success
2146 * MV_BAD_PARAM - for fail
2148 int hws_pex_tx_config_seq(struct serdes_map *serdes_map)
2150 enum serdes_mode serdes_mode;
2151 u32 serdes_lane_id, serdes_lane_hw_num;
2153 DEBUG_INIT_FULL_S("\n### hws_pex_tx_config_seq ###\n");
2156 * For PEXx4: the pex_and_usb3_tx_config_params1/2/3
2157 * configurations should run by setting each sequence for
2161 /* relese pipe soft reset for all lanes */
2162 for (serdes_lane_id = 0; serdes_lane_id < hws_serdes_get_max_lane();
2164 serdes_mode = serdes_map[serdes_lane_id].serdes_mode;
2165 serdes_lane_hw_num =
2166 hws_get_physical_serdes_num(serdes_lane_id);
2168 if ((serdes_mode == PEX_ROOT_COMPLEX_X4) ||
2169 (serdes_mode == PEX_END_POINT_X4)) {
2170 CHECK_STATUS(mv_seq_exec
2171 (serdes_lane_hw_num, PEX_TX_CONFIG_SEQ1));
2175 /* set phy soft reset for all lanes */
2176 for (serdes_lane_id = 0; serdes_lane_id < hws_serdes_get_max_lane();
2178 serdes_mode = serdes_map[serdes_lane_id].serdes_mode;
2179 serdes_lane_hw_num =
2180 hws_get_physical_serdes_num(serdes_lane_id);
2181 if ((serdes_mode == PEX_ROOT_COMPLEX_X4) ||
2182 (serdes_mode == PEX_END_POINT_X4)) {
2183 CHECK_STATUS(mv_seq_exec
2184 (serdes_lane_hw_num, PEX_TX_CONFIG_SEQ2));
2188 /* set phy soft reset for all lanes */
2189 for (serdes_lane_id = 0; serdes_lane_id < hws_serdes_get_max_lane();
2191 serdes_mode = serdes_map[serdes_lane_id].serdes_mode;
2192 serdes_lane_hw_num =
2193 hws_get_physical_serdes_num(serdes_lane_id);
2194 if ((serdes_mode == PEX_ROOT_COMPLEX_X4) ||
2195 (serdes_mode == PEX_END_POINT_X4)) {
2196 CHECK_STATUS(mv_seq_exec
2197 (serdes_lane_hw_num, PEX_TX_CONFIG_SEQ3));