1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Marvell International Ltd. and its affiliates
9 #include <asm/arch/cpu.h>
10 #include <asm/arch/soc.h>
11 #include <linux/delay.h>
13 #include "high_speed_env_spec.h"
14 #include "sys_env_lib.h"
17 #if defined(CONFIG_ARMADA_38X)
18 #elif defined(CONFIG_ARMADA_39X)
20 #error "No device is defined"
25 * serdes_seq_db - holds all serdes sequences, their size and the
26 * relevant index in the data array initialized in serdes_seq_init
28 struct cfg_seq serdes_seq_db[SERDES_LAST_SEQ];
30 #define SERDES_VERSION "2.0"
31 #define ENDED_OK "High speed PHY - Ended Successfully\n"
33 #define LINK_WAIT_CNTR 100
34 #define LINK_WAIT_SLEEP 100
36 #define MAX_UNIT_NUMB 4
37 #define TOPOLOGY_TEST_OK 0
38 #define WRONG_NUMBER_OF_UNITS 1
39 #define SERDES_ALREADY_IN_USE 2
40 #define UNIT_NUMBER_VIOLATION 3
43 * serdes_lane_in_use_count contains the exact amount of serdes lanes
46 u8 serdes_lane_in_use_count[MAX_UNITS_ID][MAX_UNIT_NUMB] = {
48 { 1, 1, 1, 1 }, /* PEX */
49 { 1, 1, 1, 1 }, /* ETH_GIG */
50 { 1, 1, 0, 0 }, /* USB3H */
51 { 1, 1, 1, 0 }, /* USB3D */
52 { 1, 1, 1, 1 }, /* SATA */
53 { 1, 0, 0, 0 }, /* QSGMII */
54 { 4, 0, 0, 0 }, /* XAUI */
55 { 2, 0, 0, 0 } /* RXAUI */
59 * serdes_unit_count count unit number.
60 * (i.e a single XAUI is counted as 1 unit)
62 u8 serdes_unit_count[MAX_UNITS_ID] = { 0 };
64 /* Selector mapping for A380-A0 and A390-Z1 */
65 u8 selectors_serdes_rev2_map[LAST_SERDES_TYPE][MAX_SERDES_LANES] = {
67 { 0x1, 0x1, NA, NA, NA, NA, NA }, /* PEX0 */
68 { NA, NA, 0x1, NA, 0x1, NA, 0x1 }, /* PEX1 */
69 { NA, NA, NA, NA, 0x7, 0x1, NA }, /* PEX2 */
70 { NA, NA, NA, 0x1, NA, NA, NA }, /* PEX3 */
71 { 0x2, 0x3, NA, NA, NA, NA, NA }, /* SATA0 */
72 { NA, NA, 0x3, NA, NA, NA, NA }, /* SATA1 */
73 { NA, NA, NA, NA, 0x6, 0x2, NA }, /* SATA2 */
74 { NA, NA, NA, 0x3, NA, NA, NA }, /* SATA3 */
75 { 0x3, 0x4, NA, NA, NA, NA, NA }, /* SGMII0 */
76 { NA, 0x5, 0x4, NA, 0x3, NA, NA }, /* SGMII1 */
77 { NA, NA, NA, 0x4, NA, 0x3, NA }, /* SGMII2 */
78 { NA, 0x7, NA, NA, NA, NA, NA }, /* QSGMII */
79 { NA, 0x6, NA, NA, 0x4, NA, NA }, /* USB3_HOST0 */
80 { NA, NA, NA, 0x5, NA, 0x4, NA }, /* USB3_HOST1 */
81 { NA, NA, NA, 0x6, 0x5, 0x5, NA }, /* USB3_DEVICE */
82 #ifdef CONFIG_ARMADA_39X
83 { NA, NA, 0x5, NA, 0x8, NA, 0x2 }, /* SGMII3 */
84 { NA, NA, NA, 0x8, 0x9, 0x8, 0x4 }, /* XAUI */
85 { NA, NA, NA, NA, NA, 0x8, 0x4 }, /* RXAUI */
87 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, NA } /* DEFAULT_SERDES */
90 /* Selector mapping for PEX by 4 confiuration */
91 u8 common_phys_selectors_pex_by4_lanes[] = { 0x1, 0x2, 0x2, 0x2 };
93 static const char *const serdes_type_to_string[] = {
116 struct serdes_unit_data {
121 static struct serdes_unit_data serdes_type_to_unit_info[] = {
130 {ETH_GIG_UNIT_ID, 0,},
131 {ETH_GIG_UNIT_ID, 1,},
132 {ETH_GIG_UNIT_ID, 2,},
133 {QSGMII_UNIT_ID, 0,},
137 {ETH_GIG_UNIT_ID, 3,},
148 struct op_params sata_port0_power_up_params[] = {
150 * unit_base_reg, unit_offset, mask, SATA data, wait_time,
153 /* Access to reg 0x48(OOB param 1) */
154 {SATA_VENDOR_PORT_0_REG_ADDR, 0x38000, 0xffffffff, {0x48,}, 0, 0},
155 /* OOB Com_wake and Com_reset spacing upper limit data */
156 {SATA_VENDOR_PORT_0_REG_DATA, 0x38000, 0xf03f, {0x6018,}, 0, 0},
157 /* Access to reg 0xa(PHY Control) */
158 {SATA_VENDOR_PORT_0_REG_ADDR, 0x38000, 0xffffffff, {0xa,}, 0, 0},
159 /* Rx clk and Tx clk select non-inverted mode */
160 {SATA_VENDOR_PORT_0_REG_DATA, 0x38000, 0x3000, {0x0,}, 0, 0},
161 /* Power Down Sata addr */
162 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0,}, 0, 0},
163 /* Power Down Sata Port 0 */
164 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffff00ff, {0xc40040,}, 0, 0},
167 struct op_params sata_port1_power_up_params[] = {
169 * unit_base_reg, unit_offset, mask, SATA data, wait_time,
172 /* Access to reg 0x48(OOB param 1) */
173 {SATA_VENDOR_PORT_1_REG_ADDR, 0x38000, 0xffffffff, {0x48,}, 0, 0},
174 /* OOB Com_wake and Com_reset spacing upper limit data */
175 {SATA_VENDOR_PORT_1_REG_DATA, 0x38000, 0xf03f, {0x6018,}, 0, 0},
176 /* Access to reg 0xa(PHY Control) */
177 {SATA_VENDOR_PORT_1_REG_ADDR, 0x38000, 0xffffffff, {0xa,}, 0, 0},
178 /* Rx clk and Tx clk select non-inverted mode */
179 {SATA_VENDOR_PORT_1_REG_DATA, 0x38000, 0x3000, {0x0,}, 0, 0},
180 /* Power Down Sata addr */
181 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0,}, 0, 0},
182 /* Power Down Sata Port 1 */
183 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffff00, {0xc44000,}, 0, 0},
186 /* SATA and SGMII - power up seq */
187 struct op_params sata_and_sgmii_power_up_params[] = {
189 * unit_base_reg, unit_offset, mask, SATA data, SGMII data,
190 * wait_time, num_of_loops
193 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x90006, {0x80002, 0x80002},
196 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000, 0x6000}, 0, 0},
198 {POWER_AND_PLL_CTRL_REG, 0x800, 0x0e0, {0x0, 0x80}, 0, 0},
199 /* Ref clock source select */
200 {MISC_REG, 0x800, 0x440, {0x440, 0x400}, 0, 0}
203 /* SATA and SGMII - speed config seq */
204 struct op_params sata_and_sgmii_speed_config_params[] = {
206 * unit_base_reg, unit_offset, mask, SATA data,
207 * SGMII (1.25G), SGMII (3.125G), wait_time, num_of_loops
210 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc00000,
211 {0x8800000, 0x19800000, 0x22000000}, 0, 0},
212 /* Select Baud Rate for SATA only */
213 {INTERFACE_REG, 0x800, 0xc00, {0x800, NO_DATA, NO_DATA}, 0, 0},
214 /* Phy Gen RX and TX */
215 {ISOLATE_REG, 0x800, 0xff, {NO_DATA, 0x66, 0x66}, 0, 0},
217 {LOOPBACK_REG, 0x800, 0xe, {0x4, 0x2, 0x2}, 0, 0}
220 /* SATA and SGMII - TX config seq */
221 struct op_params sata_and_sgmii_tx_config_params1[] = {
223 * unitunit_base_reg, unit_offset, mask, SATA data, SGMII data,
224 * wait_time, num_of_loops
226 {GLUE_REG, 0x800, 0x1800, {NO_DATA, 0x800}, 0, 0},
227 /* Sft Reset pulse */
228 {RESET_DFE_REG, 0x800, 0x401, {0x401, 0x401}, 0, 0},
229 /* Sft Reset pulse */
230 {RESET_DFE_REG, 0x800, 0x401, {0x0, 0x0}, 0, 0},
231 /* Power up PLL, RX and TX */
232 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0xf0000, {0x70000, 0x70000},
236 struct op_params sata_port0_tx_config_params[] = {
238 * unit_base_reg, unit_offset, mask, SATA data, wait_time,
241 /* Power Down Sata addr */
242 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0}, 0, 0},
243 /* Power Down Sata Port 0 */
244 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffff00ff, {0xc40000}, 0, 0},
245 /* Regret bit addr */
246 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x4}, 0, 0},
247 /* Regret bit data */
248 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffffff, {0x80}, 0, 0}
251 struct op_params sata_port1_tx_config_params[] = {
253 * unit_base_reg, unit_offset, mask, SATA data, wait_time,
256 /* Power Down Sata addr */
257 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x0}, 0, 0},
258 /* Power Down Sata Port 1 */
259 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffff00, {0xc40000}, 0, 0},
260 /* Regret bit addr */
261 {SATA_CTRL_REG_IND_ADDR, 0x38000, 0xffffffff, {0x4}, 0, 0},
262 /* Regret bit data */
263 {SATA_CTRL_REG_IND_DATA, 0x38000, 0xffffffff, {0x80}, 0, 0}
266 struct op_params sata_and_sgmii_tx_config_serdes_rev1_params2[] = {
268 * unit_base_reg, unit_offset, mask, SATA data, SGMII data,
269 * wait_time, num_of_loops
271 /* Wait for PHY power up sequence to finish */
272 {COMMON_PHY_STATUS1_REG, 0x28, 0xc, {0xc, 0xc}, 10, 1000},
273 /* Wait for PHY power up sequence to finish */
274 {COMMON_PHY_STATUS1_REG, 0x28, 0x1, {0x1, 0x1}, 1, 1000}
277 struct op_params sata_and_sgmii_tx_config_serdes_rev2_params2[] = {
279 * unit_base_reg, unit_offset, mask, SATA data, SGMII data,
280 * wait_time, num_of_loops
282 /* Wait for PHY power up sequence to finish */
283 {COMMON_PHY_STATUS1_REG, 0x28, 0xc, {0xc, 0xc}, 10, 1000},
284 /* Assert Rx Init for SGMII */
285 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40000000, {NA, 0x40000000},
287 /* Assert Rx Init for SATA */
288 {ISOLATE_REG, 0x800, 0x400, {0x400, NA}, 0, 0},
289 /* Wait for PHY power up sequence to finish */
290 {COMMON_PHY_STATUS1_REG, 0x28, 0x1, {0x1, 0x1}, 1, 1000},
291 /* De-assert Rx Init for SGMII */
292 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40000000, {NA, 0x0}, 0, 0},
293 /* De-assert Rx Init for SATA */
294 {ISOLATE_REG, 0x800, 0x400, {0x0, NA}, 0, 0},
295 /* os_ph_offset_force (align 90) */
296 {RX_REG3, 0x800, 0xff, {0xde, NO_DATA}, 0, 0},
297 /* Set os_ph_valid */
298 {RX_REG3, 0x800, 0x100, {0x100, NO_DATA}, 0, 0},
299 /* Unset os_ph_valid */
300 {RX_REG3, 0x800, 0x100, {0x0, NO_DATA}, 0, 0},
303 struct op_params sata_electrical_config_serdes_rev1_params[] = {
305 * unit_base_reg, unit_offset, mask, SATA data, wait_time,
308 /* enable SSC and DFE update enable */
309 {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x400008, {0x400000,}, 0, 0},
310 /* tximpcal_th and rximpcal_th */
311 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x4000,}, 0, 0},
312 /* SQ_THRESH and FFE Setting */
313 {SQUELCH_FFE_SETTING_REG, 0x800, 0xfff, {0x6cf,}, 0, 0},
314 /* G1_TX SLEW, EMPH1 and AMP */
315 {G1_SETTINGS_0_REG, 0x800, 0xffff, {0x8a32,}, 0, 0},
316 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
317 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9,}, 0, 0},
318 /* G2_TX SLEW, EMPH1 and AMP */
319 {G2_SETTINGS_0_REG, 0x800, 0xffff, {0x8b5c,}, 0, 0},
320 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
321 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2,}, 0, 0},
322 /* G3_TX SLEW, EMPH1 and AMP */
323 {G3_SETTINGS_0_REG, 0x800, 0xffff, {0xe6e,}, 0, 0},
324 /* G3_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
325 {G3_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2,}, 0, 0},
326 /* Cal rxclkalign90 ext enable and Cal os ph ext */
327 {CAL_REG6, 0x800, 0xff00, {0xdd00,}, 0, 0},
328 /* Dtl Clamping disable and Dtl clamping Sel(6000ppm) */
329 {RX_REG2, 0x800, 0xf0, {0x70,}, 0, 0},
332 struct op_params sata_electrical_config_serdes_rev2_params[] = {
334 * unit_base_reg, unit_offset, mask, SATA data, wait_time,
337 /* SQ_THRESH and FFE Setting */
338 {SQUELCH_FFE_SETTING_REG, 0x800, 0xf00, {0x600}, 0, 0},
339 /* enable SSC and DFE update enable */
340 {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x400008, {0x400000}, 0, 0},
341 /* G1_TX SLEW, EMPH1 and AMP */
342 {G1_SETTINGS_0_REG, 0x800, 0xffff, {0x8a32}, 0, 0},
343 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
344 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
345 /* G2_TX SLEW, EMPH1 and AMP */
346 {G2_SETTINGS_0_REG, 0x800, 0xffff, {0x8b5c}, 0, 0},
347 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
348 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2}, 0, 0},
349 /* G3_TX SLEW, EMPH1 and AMP */
350 {G3_SETTINGS_0_REG, 0x800, 0xffff, {0xe6e}, 0, 0},
352 * G3_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI & DFE_En Gen3,
353 * DC wander calibration dis
355 {G3_SETTINGS_1_REG, 0x800, 0x47ff, {0x7d2}, 0, 0},
356 /* Bit[12]=0x0 idle_sync_en */
357 {PCIE_REG0, 0x800, 0x1000, {0x0}, 0, 0},
358 /* Dtl Clamping disable and Dtl clamping Sel(6000ppm) */
359 {RX_REG2, 0x800, 0xf0, {0x70,}, 0, 0},
360 /* tximpcal_th and rximpcal_th */
361 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0},
362 /* DFE_STEP_FINE_FX[3:0] =0xa */
363 {DFE_REG0, 0x800, 0xa00f, {0x800a}, 0, 0},
364 /* DFE_EN and Dis Update control from pin disable */
365 {DFE_REG3, 0x800, 0xc000, {0x0}, 0, 0},
366 /* FFE Force FFE_REs and cap settings for Gen1 */
367 {G1_SETTINGS_3_REG, 0x800, 0xff, {0xcf}, 0, 0},
368 /* FFE Force FFE_REs and cap settings for Gen2 */
369 {G2_SETTINGS_3_REG, 0x800, 0xff, {0xbf}, 0, 0},
370 /* FE Force FFE_REs=4 and cap settings for Gen3n */
371 {G3_SETTINGS_3_REG, 0x800, 0xff, {0xcf}, 0, 0},
372 /* Set DFE Gen 3 Resolution to 3 */
373 {G3_SETTINGS_4_REG, 0x800, 0x300, {0x300}, 0, 0},
376 struct op_params sgmii_electrical_config_serdes_rev1_params[] = {
378 * unit_base_reg, unit_offset, mask, SGMII (1.25G), SGMII (3.125G),
379 * wait_time, num_of_loops
381 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
382 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9, 0x3c9}, 0, 0},
383 /* SQ_THRESH and FFE Setting */
384 {SQUELCH_FFE_SETTING_REG, 0x800, 0xfff, {0x8f, 0xbf}, 0, 0},
385 /* tximpcal_th and rximpcal_th */
386 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x4000, 0x4000}, 0, 0},
389 struct op_params sgmii_electrical_config_serdes_rev2_params[] = {
391 * unit_base_reg, unit_offset, mask, SGMII (1.25G), SGMII (3.125G),
392 * wait_time, num_of_loops
394 /* Set Slew_rate, Emph and Amp */
395 {G1_SETTINGS_0_REG, 0x800, 0xffff, {0x8fa, 0x8fa}, 0, 0},
396 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
397 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9, 0x3c9}, 0, 0},
399 {RX_REG2, 0x800, 0x4, {0x0, 0x0}, 0, 0},
400 /* G1 FFE Setting Force, RES and CAP */
401 {G1_SETTINGS_3_REG, 0x800, 0xff, {0x8f, 0xbf}, 0, 0},
402 /* tximpcal_th and rximpcal_th */
403 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000, 0x3000}, 0, 0},
410 /* PEX and USB3 - power up seq for Serdes Rev 1.2 */
411 struct op_params pex_and_usb3_power_up_serdes_rev1_params[] = {
413 * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
414 * wait_time, num_of_loops
416 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc7f806,
417 {0x4471804, 0x4479804}, 0, 0},
418 {COMMON_PHY_CONFIGURATION2_REG, 0x28, 0x5c, {0x58, 0x58}, 0, 0},
419 {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x3, {0x1, 0x1}, 0, 0},
420 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000, 0xe000}, 0, 0},
421 {GLOBAL_CLK_CTRL, 0x800, 0xd, {0x5, 0x1}, 0, 0},
422 /* Ref clock source select */
423 {MISC_REG, 0x800, 0x4c0, {0x80, 0x4c0}, 0, 0}
426 /* PEX and USB3 - power up seq for Serdes Rev 2.1 */
427 struct op_params pex_and_usb3_power_up_serdes_rev2_params[] = {
429 * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
430 * wait_time, num_of_loops
432 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc7f806,
433 {0x4471804, 0x4479804}, 0, 0},
434 {COMMON_PHY_CONFIGURATION2_REG, 0x28, 0x5c, {0x58, 0x58}, 0, 0},
435 {COMMON_PHY_CONFIGURATION4_REG, 0x28, 0x3, {0x1, 0x1}, 0, 0},
436 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000, 0xe000}, 0, 0},
437 {GLOBAL_CLK_CTRL, 0x800, 0xd, {0x5, 0x1}, 0, 0},
438 {GLOBAL_MISC_CTRL, 0x800, 0xc0, {0x0, NO_DATA}, 0, 0},
439 /* Ref clock source select */
440 {MISC_REG, 0x800, 0x4c0, {0x80, 0x4c0}, 0, 0}
443 /* PEX and USB3 - speed config seq */
444 struct op_params pex_and_usb3_speed_config_params[] = {
446 * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
447 * wait_time, num_of_loops
449 /* Maximal PHY Generation Setting */
450 {INTERFACE_REG, 0x800, 0xc00, {0x400, 0x400, 0x400, 0x400, 0x400},
454 struct op_params usb3_electrical_config_serdes_rev1_params[] = {
455 /* Spread Spectrum Clock Enable */
456 {LANE_CFG4_REG, 0x800, 0x80, {0x80}, 0, 0},
457 /* G2_TX_SSC_AMP[6:0]=4.5k_p_pM and TX emphasis mode=m_v */
458 {G2_SETTINGS_2_REG, 0x800, 0xfe40, {0x4440}, 0, 0},
459 /* tximpcal_th and rximpcal_th */
460 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x4000}, 0, 0},
461 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
462 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2}, 0, 0},
463 /* FFE Setting Force, RES and CAP */
464 {SQUELCH_FFE_SETTING_REG, 0x800, 0xff, {0xef}, 0, 0},
465 /* Dtl Clamping disable and Dtl-clamping-Sel(6000ppm) */
466 {RX_REG2, 0x800, 0xf0, {0x70}, 0, 0},
467 /* cal_rxclkalign90_ext_en and cal_os_ph_ext */
468 {CAL_REG6, 0x800, 0xff00, {0xd500}, 0, 0},
469 /* vco_cal_vth_sel */
470 {REF_REG0, 0x800, 0x38, {0x20}, 0, 0},
473 struct op_params usb3_electrical_config_serdes_rev2_params[] = {
474 /* Spread Spectrum Clock Enable */
475 {LANE_CFG4_REG, 0x800, 0x80, {0x80}, 0, 0},
476 /* G2_TX_SSC_AMP[6:0]=4.5k_p_pM and TX emphasis mode=m_v */
477 {G2_SETTINGS_2_REG, 0x800, 0xfe40, {0x4440}, 0, 0},
478 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
479 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3d2}, 0, 0},
480 /* Dtl Clamping disable and Dtl-clamping-Sel(6000ppm) */
481 {RX_REG2, 0x800, 0xf0, {0x70}, 0, 0},
482 /* vco_cal_vth_sel */
483 {REF_REG0, 0x800, 0x38, {0x20}, 0, 0},
484 /* Spread Spectrum Clock Enable */
485 {LANE_CFG5_REG, 0x800, 0x4, {0x4}, 0, 0},
488 /* PEX and USB3 - TX config seq */
491 * For PEXx1: the pex_and_usb3_tx_config_params1/2/3 configurations should run
492 * one by one on the lane.
493 * For PEXx4: the pex_and_usb3_tx_config_params1/2/3 configurations should run
494 * by setting each sequence for all 4 lanes.
496 struct op_params pex_and_usb3_tx_config_params1[] = {
498 * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
499 * wait_time, num_of_loops
501 {GLOBAL_CLK_CTRL, 0x800, 0x1, {0x0, 0x0}, 0, 0},
503 {0x0, 0x0, 0x0, {0x0, 0x0}, 10, 0},
504 /* os_ph_offset_force (align 90) */
505 {RX_REG3, 0x800, 0xff, {0xdc, NO_DATA}, 0, 0},
506 /* Set os_ph_valid */
507 {RX_REG3, 0x800, 0x100, {0x100, NO_DATA}, 0, 0},
508 /* Unset os_ph_valid */
509 {RX_REG3, 0x800, 0x100, {0x0, NO_DATA}, 0, 0},
512 struct op_params pex_and_usb3_tx_config_params2[] = {
514 * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
515 * wait_time, num_of_loops
517 /* Sft Reset pulse */
518 {RESET_DFE_REG, 0x800, 0x401, {0x401, 0x401}, 0, 0},
521 struct op_params pex_and_usb3_tx_config_params3[] = {
523 * unit_base_reg, unit_offset, mask, PEX data, USB3 data,
524 * wait_time, num_of_loops
526 /* Sft Reset pulse */
527 {RESET_DFE_REG, 0x800, 0x401, {0x0, 0x0}, 0, 0},
529 {0x0, 0x0, 0x0, {0x0, 0x0}, 10, 0}
532 /* PEX by 4 config seq */
533 struct op_params pex_by4_config_params[] = {
534 /* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */
535 {GLOBAL_CLK_SRC_HI, 0x800, 0x7, {0x5, 0x0, 0x0, 0x2}, 0, 0},
536 /* Lane Alignment enable */
537 {LANE_ALIGN_REG0, 0x800, 0x1000, {0x0, 0x0, 0x0, 0x0}, 0, 0},
538 /* Max PLL phy config */
539 {CALIBRATION_CTRL_REG, 0x800, 0x1000, {0x1000, 0x1000, 0x1000, 0x1000},
541 /* Max PLL pipe config */
542 {LANE_CFG1_REG, 0x800, 0x600, {0x600, 0x600, 0x600, 0x600}, 0, 0},
545 /* USB3 device donfig seq */
546 struct op_params usb3_device_config_params[] = {
547 /* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */
548 {LANE_CFG4_REG, 0x800, 0x200, {0x200}, 0, 0}
551 /* PEX - electrical configuration seq Rev 1.2 */
552 struct op_params pex_electrical_config_serdes_rev1_params[] = {
554 * unit_base_reg, unit_offset, mask, PEX data, wait_time,
557 /* G1_TX_SLEW_CTRL_EN and G1_TX_SLEW_RATE */
558 {G1_SETTINGS_0_REG, 0x800, 0xf000, {0xb000}, 0, 0},
559 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
560 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
561 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
562 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
564 {LANE_CFG4_REG, 0x800, 0x8, {0x8}, 0, 0},
565 /* FFE Setting Force, RES and CAP */
566 {SQUELCH_FFE_SETTING_REG, 0x800, 0xff, {0xaf}, 0, 0},
567 /* tximpcal_th and rximpcal_th */
568 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0},
569 /* cal_rxclkalign90_ext_en and cal_os_ph_ext */
570 {CAL_REG6, 0x800, 0xff00, {0xdc00}, 0, 0},
573 /* PEX - electrical configuration seq Rev 2.1 */
574 struct op_params pex_electrical_config_serdes_rev2_params[] = {
576 * unit_base_reg, unit_offset, mask, PEX data, wait_time,
579 /* G1_TX_SLEW_CTRL_EN and G1_TX_SLEW_RATE */
580 {G1_SETTINGS_0_REG, 0x800, 0xf000, {0xb000}, 0, 0},
581 /* G1_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
582 {G1_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
583 /* G1 FFE Setting Force, RES and CAP */
584 {G1_SETTINGS_3_REG, 0x800, 0xff, {0xcf}, 0, 0},
585 /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
586 {G2_SETTINGS_1_REG, 0x800, 0x3ff, {0x3c9}, 0, 0},
587 /* G2 FFE Setting Force, RES and CAP */
588 {G2_SETTINGS_3_REG, 0x800, 0xff, {0xaf}, 0, 0},
589 /* G2 DFE resolution value */
590 {G2_SETTINGS_4_REG, 0x800, 0x300, {0x300}, 0, 0},
591 /* DFE resolution force */
592 {DFE_REG0, 0x800, 0x8000, {0x8000}, 0, 0},
593 /* Tx amplitude for Tx Margin 0 */
594 {PCIE_REG1, 0x800, 0xf80, {0xd00}, 0, 0},
595 /* Tx_Emph value for -3.5d_b and -6d_b */
596 {PCIE_REG3, 0x800, 0xff00, {0xaf00}, 0, 0},
598 {LANE_CFG4_REG, 0x800, 0x8, {0x8}, 0, 0},
599 /* tximpcal_th and rximpcal_th */
600 {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0},
601 /* Force receiver detected */
602 {LANE_CFG0_REG, 0x800, 0x8000, {0x8000}, 0, 0},
605 /* PEX - configuration seq for REF_CLOCK_25MHz */
606 struct op_params pex_config_ref_clock25_m_hz[] = {
608 * unit_base_reg, unit_offset, mask, PEX data, wait_time,
611 /* Bits[4:0]=0x2 - REF_FREF_SEL */
612 {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x2}, 0, 0},
613 /* Bit[10]=0x1 - REFCLK_SEL */
614 {MISC_REG, 0x800, 0x400, {0x400}, 0, 0},
615 /* Bits[7:0]=0x7 - CFG_PM_RXDLOZ_WAIT */
616 {GLOBAL_PM_CTRL, 0x800, 0xff, {0x7}, 0, 0},
619 /* PEX - configuration seq for REF_CLOCK_40MHz */
620 struct op_params pex_config_ref_clock40_m_hz[] = {
622 * unit_base_reg, unit_offset, mask, PEX data, wait_time,
625 /* Bits[4:0]=0x3 - REF_FREF_SEL */
626 {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x3}, 0, 0},
627 /* Bits[10]=0x1 - REFCLK_SEL */
628 {MISC_REG, 0x800, 0x400, {0x400}, 0, 0},
629 /* Bits[7:0]=0xc - CFG_PM_RXDLOZ_WAIT */
630 {GLOBAL_PM_CTRL, 0x800, 0xff, {0xc}, 0, 0},
633 /* PEX - configuration seq for REF_CLOCK_100MHz */
634 struct op_params pex_config_ref_clock100_m_hz[] = {
636 * unit_base_reg, unit_offset, mask, PEX data, wait_time,
639 /* Bits[4:0]=0x0 - REF_FREF_SEL */
640 {POWER_AND_PLL_CTRL_REG, 0x800, 0x1f, {0x0}, 0, 0},
641 /* Bit[10]=0x0 - REFCLK_SEL */
642 {MISC_REG, 0x800, 0x400, {0x0}, 0, 0},
643 /* Bits[7:0]=0x1e - CFG_PM_RXDLOZ_WAIT */
644 {GLOBAL_PM_CTRL, 0x800, 0xff, {0x1e}, 0, 0},
651 struct op_params usb2_power_up_params[] = {
653 * unit_base_reg, unit_offset, mask, USB2 data, wait_time,
657 {0x18440, 0x0 /*NA*/, 0xffffffff, {0x62}, 0, 0},
659 {0x18444, 0x0 /*NA*/, 0xffffffff, {0x62}, 0, 0},
661 {0x18448, 0x0 /*NA*/, 0xffffffff, {0x62}, 0, 0},
662 /* Phy offset 0x0 - PLL_CONTROL0 */
663 {0xc0000, 0x0 /*NA*/, 0xffffffff, {0x40605205}, 0, 0},
664 {0xc001c, 0x0 /*NA*/, 0xffffffff, {0x39f16ce}, 0, 0},
665 {0xc201c, 0x0 /*NA*/, 0xffffffff, {0x39f16ce}, 0, 0},
666 {0xc401c, 0x0 /*NA*/, 0xffffffff, {0x39f16ce}, 0, 0},
667 /* Phy offset 0x1 - PLL_CONTROL1 */
668 {0xc0004, 0x0 /*NA*/, 0x1, {0x1}, 0, 0},
669 /* Phy0 register 3 - TX Channel control 0 */
670 {0xc000c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0},
671 /* Phy0 register 3 - TX Channel control 0 */
672 {0xc200c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0},
673 /* Phy0 register 3 - TX Channel control 0 */
674 {0xc400c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0},
675 /* Decrease the amplitude of the low speed eye to meet the spec */
676 {0xc000c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0},
677 {0xc200c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0},
678 {0xc400c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0},
679 /* Change the High speed impedance threshold */
680 {0xc0008, 0x0 /*NA*/, 0x700, {CONFIG_ARMADA_38X_HS_IMPEDANCE_THRESH << 8}, 0, 0},
681 {0xc2008, 0x0 /*NA*/, 0x700, {CONFIG_ARMADA_38X_HS_IMPEDANCE_THRESH << 8}, 0, 0},
682 {0xc4008, 0x0 /*NA*/, 0x700, {CONFIG_ARMADA_38X_HS_IMPEDANCE_THRESH << 8}, 0, 0},
683 /* Change the squelch level of the receiver to meet the receiver electrical measurements (squelch and receiver sensitivity tests) */
684 {0xc0014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0},
685 {0xc2014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0},
686 {0xc4014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0},
687 /* Check PLLCAL_DONE is set and IMPCAL_DONE is set */
688 {0xc0008, 0x0 /*NA*/, 0x80800000, {0x80800000}, 1, 1000},
689 /* Check REG_SQCAL_DONE is set */
690 {0xc0018, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000},
691 /* Check PLL_READY is set */
692 {0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000},
693 /* Start calibrate of high seed impedance */
694 {0xc0008, 0x0 /*NA*/, 0x2000, {0x2000}, 0, 0},
695 {0x0, 0x0 /*NA*/, 0x0, {0x0}, 10, 0},
696 /* De-assert the calibration signal */
697 {0xc0008, 0x0 /*NA*/, 0x2000, {0x0}, 0, 0},
704 /* QSGMII - power up seq */
705 struct op_params qsgmii_port_power_up_params[] = {
707 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
710 /* Connect the QSGMII to Gigabit Ethernet units */
711 {QSGMII_CONTROL_REG1, 0x0, 0x40000000, {0x40000000}, 0, 0},
713 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0xf0006, {0x80002}, 0, 0},
715 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x7800, {0x6000}, 0, 0},
717 {POWER_AND_PLL_CTRL_REG, 0x800, 0xff, {0xfc81}, 0, 0},
718 /* Ref clock source select */
719 {MISC_REG, 0x800, 0x4c0, {0x480}, 0, 0}
722 /* QSGMII - speed config seq */
723 struct op_params qsgmii_port_speed_config_params[] = {
725 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
729 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x3fc00000, {0xcc00000}, 0, 0},
730 /* Phy Gen RX and TX */
731 {ISOLATE_REG, 0x800, 0xff, {0x33}, 0, 0},
733 {LOOPBACK_REG, 0x800, 0xe, {0x2}, 0, 0}
736 /* QSGMII - Select electrical param seq */
737 struct op_params qsgmii_port_electrical_config_params[] = {
739 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
742 /* Slew rate and emphasis */
743 {G1_SETTINGS_0_REG, 0x800, 0x8000, {0x0}, 0, 0}
746 /* QSGMII - TX config seq */
747 struct op_params qsgmii_port_tx_config_params1[] = {
749 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
752 {GLUE_REG, 0x800, 0x1800, {0x800}, 0, 0},
753 /* Sft Reset pulse */
754 {RESET_DFE_REG, 0x800, 0x401, {0x401}, 0, 0},
755 /* Sft Reset pulse */
756 {RESET_DFE_REG, 0x800, 0x401, {0x0}, 0, 0},
758 {LANE_ALIGN_REG0, 0x800, 0x1000, {0x1000}, 0, 0},
759 /* Power up PLL, RX and TX */
760 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x70000, {0x70000}, 0, 0},
761 /* Tx driver output idle */
762 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x80000, {0x80000}, 0, 0}
765 struct op_params qsgmii_port_tx_config_params2[] = {
767 * unit_base_reg, unit_offset, mask, QSGMII data, wait_time,
770 /* Wait for PHY power up sequence to finish */
771 {COMMON_PHY_STATUS1_REG, 0x28, 0xc, {0xc}, 10, 1000},
772 /* Assert Rx Init and Tx driver output valid */
773 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40080000, {0x40000000}, 0, 0},
774 /* Wait for PHY power up sequence to finish */
775 {COMMON_PHY_STATUS1_REG, 0x28, 0x1, {0x1}, 1, 1000},
776 /* De-assert Rx Init */
777 {COMMON_PHY_CONFIGURATION1_REG, 0x28, 0x40000000, {0x0}, 0, 0}
780 /* SERDES_POWER_DOWN */
781 struct op_params serdes_power_down_params[] = {
782 {COMMON_PHY_CONFIGURATION1_REG, 0x28, (0xf << 11), {(0x3 << 11)},
784 {COMMON_PHY_CONFIGURATION1_REG, 0x28, (0x7 << 16), {0}, 0, 0}
788 * hws_ctrl_serdes_rev_get
790 * DESCRIPTION: Get the Serdes revision number
792 * INPUT: config_field - Field description enum
797 * 8bit Serdes revision number
799 u8 hws_ctrl_serdes_rev_get(void)
801 #ifdef CONFIG_ARMADA_38X
803 if (sys_env_device_rev_get() == MV_88F68XX_Z1_ID)
804 return MV_SERDES_REV_1_2;
807 /* for A39x-Z1, A38x-A0 */
808 return MV_SERDES_REV_2_1;
811 u32 hws_serdes_topology_verify(enum serdes_type serdes_type, u32 serdes_id,
812 enum serdes_mode serdes_mode)
815 u8 serd_max_num, unit_numb;
816 enum unit_id unit_id;
818 if (serdes_type > RXAUI) {
819 printf("%s: Warning: Wrong serdes type %s serdes#%d\n",
820 __func__, serdes_type_to_string[serdes_type], serdes_id);
824 unit_id = serdes_type_to_unit_info[serdes_type].serdes_unit_id;
825 unit_numb = serdes_type_to_unit_info[serdes_type].serdes_unit_num;
826 serd_max_num = sys_env_unit_max_num_get(unit_id);
828 /* if didn't exceed amount of required Serdes lanes for current type */
829 if (serdes_lane_in_use_count[unit_id][unit_numb] != 0) {
830 /* update amount of required Serdes lanes for current type */
831 serdes_lane_in_use_count[unit_id][unit_numb]--;
834 * If reached the exact amount of required Serdes lanes for
837 if (serdes_lane_in_use_count[unit_id][unit_numb] == 0) {
838 if (((serdes_type <= PEX3)) &&
839 ((serdes_mode == PEX_END_POINT_X4) ||
840 (serdes_mode == PEX_ROOT_COMPLEX_X4))) {
841 /* PCiex4 uses 2 SerDes */
842 serdes_unit_count[PEX_UNIT_ID] += 2;
844 serdes_unit_count[unit_id]++;
847 /* test SoC unit count limitation */
848 if (serdes_unit_count[unit_id] > serd_max_num) {
849 test_result = WRONG_NUMBER_OF_UNITS;
850 } else if (unit_numb >= serd_max_num) {
851 /* test SoC unit number limitation */
852 test_result = UNIT_NUMBER_VIOLATION;
856 test_result = SERDES_ALREADY_IN_USE;
859 if (test_result == SERDES_ALREADY_IN_USE) {
860 printf("%s: Error: serdes lane %d is configured to type %s: type already in use\n",
862 serdes_type_to_string[serdes_type]);
864 } else if (test_result == WRONG_NUMBER_OF_UNITS) {
865 printf("%s: Warning: serdes lane %d is set to type %s.\n",
867 serdes_type_to_string[serdes_type]);
868 printf("%s: Maximum supported lanes are already set to this type (limit = %d)\n",
869 __func__, serd_max_num);
871 } else if (test_result == UNIT_NUMBER_VIOLATION) {
872 printf("%s: Warning: serdes lane %d type is %s: current device support only %d units of this type.\n",
874 serdes_type_to_string[serdes_type],
882 void hws_serdes_xaui_topology_verify(void)
885 * If XAUI is in use - serdes_lane_in_use_count has to be = 0;
886 * if it is not in use hast be = 4
888 if ((serdes_lane_in_use_count[XAUI_UNIT_ID][0] != 0) &&
889 (serdes_lane_in_use_count[XAUI_UNIT_ID][0] != 4)) {
890 printf("%s: Warning: wrong number of lanes is set to XAUI - %d\n",
891 __func__, serdes_lane_in_use_count[XAUI_UNIT_ID][0]);
892 printf("%s: XAUI has to be defined on 4 lanes\n", __func__);
896 * If RXAUI is in use - serdes_lane_in_use_count has to be = 0;
897 * if it is not in use hast be = 2
899 if ((serdes_lane_in_use_count[RXAUI_UNIT_ID][0] != 0) &&
900 (serdes_lane_in_use_count[RXAUI_UNIT_ID][0] != 2)) {
901 printf("%s: Warning: wrong number of lanes is set to RXAUI - %d\n",
902 __func__, serdes_lane_in_use_count[RXAUI_UNIT_ID][0]);
903 printf("%s: RXAUI has to be defined on 2 lanes\n", __func__);
907 int hws_serdes_seq_db_init(void)
909 u8 serdes_rev = hws_ctrl_serdes_rev_get();
911 DEBUG_INIT_FULL_S("\n### serdes_seq38x_init ###\n");
913 if (serdes_rev == MV_SERDES_REV_NA) {
914 printf("hws_serdes_seq_db_init: serdes revision number is not supported\n");
915 return MV_NOT_SUPPORTED;
918 /* SATA_PORT_0_ONLY_POWER_UP_SEQ sequence init */
919 serdes_seq_db[SATA_PORT_0_ONLY_POWER_UP_SEQ].op_params_ptr =
920 sata_port0_power_up_params;
921 serdes_seq_db[SATA_PORT_0_ONLY_POWER_UP_SEQ].cfg_seq_size =
922 sizeof(sata_port0_power_up_params) / sizeof(struct op_params);
923 serdes_seq_db[SATA_PORT_0_ONLY_POWER_UP_SEQ].data_arr_idx = SATA;
925 /* SATA_PORT_1_ONLY_POWER_UP_SEQ sequence init */
926 serdes_seq_db[SATA_PORT_1_ONLY_POWER_UP_SEQ].op_params_ptr =
927 sata_port1_power_up_params;
928 serdes_seq_db[SATA_PORT_1_ONLY_POWER_UP_SEQ].cfg_seq_size =
929 sizeof(sata_port1_power_up_params) / sizeof(struct op_params);
930 serdes_seq_db[SATA_PORT_1_ONLY_POWER_UP_SEQ].data_arr_idx = SATA;
932 /* SATA_POWER_UP_SEQ sequence init */
933 serdes_seq_db[SATA_POWER_UP_SEQ].op_params_ptr =
934 sata_and_sgmii_power_up_params;
935 serdes_seq_db[SATA_POWER_UP_SEQ].cfg_seq_size =
936 sizeof(sata_and_sgmii_power_up_params) / sizeof(struct op_params);
937 serdes_seq_db[SATA_POWER_UP_SEQ].data_arr_idx = SATA;
939 /* SATA_1_5_SPEED_CONFIG_SEQ sequence init */
940 serdes_seq_db[SATA_1_5_SPEED_CONFIG_SEQ].op_params_ptr =
941 sata_and_sgmii_speed_config_params;
942 serdes_seq_db[SATA_1_5_SPEED_CONFIG_SEQ].cfg_seq_size =
943 sizeof(sata_and_sgmii_speed_config_params) /
944 sizeof(struct op_params);
945 serdes_seq_db[SATA_1_5_SPEED_CONFIG_SEQ].data_arr_idx = SATA;
947 /* SATA_3_SPEED_CONFIG_SEQ sequence init */
948 serdes_seq_db[SATA_3_SPEED_CONFIG_SEQ].op_params_ptr =
949 sata_and_sgmii_speed_config_params;
950 serdes_seq_db[SATA_3_SPEED_CONFIG_SEQ].cfg_seq_size =
951 sizeof(sata_and_sgmii_speed_config_params) /
952 sizeof(struct op_params);
953 serdes_seq_db[SATA_3_SPEED_CONFIG_SEQ].data_arr_idx = SATA;
955 /* SATA_6_SPEED_CONFIG_SEQ sequence init */
956 serdes_seq_db[SATA_6_SPEED_CONFIG_SEQ].op_params_ptr =
957 sata_and_sgmii_speed_config_params;
958 serdes_seq_db[SATA_6_SPEED_CONFIG_SEQ].cfg_seq_size =
959 sizeof(sata_and_sgmii_speed_config_params) /
960 sizeof(struct op_params);
961 serdes_seq_db[SATA_6_SPEED_CONFIG_SEQ].data_arr_idx = SATA;
963 /* SATA_ELECTRICAL_CONFIG_SEQ seq sequence init */
964 if (serdes_rev == MV_SERDES_REV_1_2) {
965 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
966 sata_electrical_config_serdes_rev1_params;
967 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
968 sizeof(sata_electrical_config_serdes_rev1_params) /
969 sizeof(struct op_params);
971 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
972 sata_electrical_config_serdes_rev2_params;
973 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
974 sizeof(sata_electrical_config_serdes_rev2_params) /
975 sizeof(struct op_params);
977 serdes_seq_db[SATA_ELECTRICAL_CONFIG_SEQ].data_arr_idx = SATA;
979 /* SATA_TX_CONFIG_SEQ sequence init */
980 serdes_seq_db[SATA_TX_CONFIG_SEQ1].op_params_ptr =
981 sata_and_sgmii_tx_config_params1;
982 serdes_seq_db[SATA_TX_CONFIG_SEQ1].cfg_seq_size =
983 sizeof(sata_and_sgmii_tx_config_params1) / sizeof(struct op_params);
984 serdes_seq_db[SATA_TX_CONFIG_SEQ1].data_arr_idx = SATA;
986 /* SATA_PORT_0_ONLY_TX_CONFIG_SEQ sequence init */
987 serdes_seq_db[SATA_PORT_0_ONLY_TX_CONFIG_SEQ].op_params_ptr =
988 sata_port0_tx_config_params;
989 serdes_seq_db[SATA_PORT_0_ONLY_TX_CONFIG_SEQ].cfg_seq_size =
990 sizeof(sata_port0_tx_config_params) / sizeof(struct op_params);
991 serdes_seq_db[SATA_PORT_0_ONLY_TX_CONFIG_SEQ].data_arr_idx = SATA;
993 /* SATA_PORT_1_ONLY_TX_CONFIG_SEQ sequence init */
994 serdes_seq_db[SATA_PORT_1_ONLY_TX_CONFIG_SEQ].op_params_ptr =
995 sata_port1_tx_config_params;
996 serdes_seq_db[SATA_PORT_1_ONLY_TX_CONFIG_SEQ].cfg_seq_size =
997 sizeof(sata_port1_tx_config_params) / sizeof(struct op_params);
998 serdes_seq_db[SATA_PORT_1_ONLY_TX_CONFIG_SEQ].data_arr_idx = SATA;
1000 /* SATA_TX_CONFIG_SEQ2 sequence init */
1001 if (serdes_rev == MV_SERDES_REV_1_2) {
1002 serdes_seq_db[SATA_TX_CONFIG_SEQ2].op_params_ptr =
1003 sata_and_sgmii_tx_config_serdes_rev1_params2;
1004 serdes_seq_db[SATA_TX_CONFIG_SEQ2].cfg_seq_size =
1005 sizeof(sata_and_sgmii_tx_config_serdes_rev1_params2) /
1006 sizeof(struct op_params);
1008 serdes_seq_db[SATA_TX_CONFIG_SEQ2].op_params_ptr =
1009 sata_and_sgmii_tx_config_serdes_rev2_params2;
1010 serdes_seq_db[SATA_TX_CONFIG_SEQ2].cfg_seq_size =
1011 sizeof(sata_and_sgmii_tx_config_serdes_rev2_params2) /
1012 sizeof(struct op_params);
1014 serdes_seq_db[SATA_TX_CONFIG_SEQ2].data_arr_idx = SATA;
1016 /* SGMII_POWER_UP_SEQ sequence init */
1017 serdes_seq_db[SGMII_POWER_UP_SEQ].op_params_ptr =
1018 sata_and_sgmii_power_up_params;
1019 serdes_seq_db[SGMII_POWER_UP_SEQ].cfg_seq_size =
1020 sizeof(sata_and_sgmii_power_up_params) / sizeof(struct op_params);
1021 serdes_seq_db[SGMII_POWER_UP_SEQ].data_arr_idx = SGMII;
1023 /* SGMII_1_25_SPEED_CONFIG_SEQ sequence init */
1024 serdes_seq_db[SGMII_1_25_SPEED_CONFIG_SEQ].op_params_ptr =
1025 sata_and_sgmii_speed_config_params;
1026 serdes_seq_db[SGMII_1_25_SPEED_CONFIG_SEQ].cfg_seq_size =
1027 sizeof(sata_and_sgmii_speed_config_params) /
1028 sizeof(struct op_params);
1029 serdes_seq_db[SGMII_1_25_SPEED_CONFIG_SEQ].data_arr_idx = SGMII;
1031 /* SGMII_3_125_SPEED_CONFIG_SEQ sequence init */
1032 serdes_seq_db[SGMII_3_125_SPEED_CONFIG_SEQ].op_params_ptr =
1033 sata_and_sgmii_speed_config_params;
1034 serdes_seq_db[SGMII_3_125_SPEED_CONFIG_SEQ].cfg_seq_size =
1035 sizeof(sata_and_sgmii_speed_config_params) /
1036 sizeof(struct op_params);
1037 serdes_seq_db[SGMII_3_125_SPEED_CONFIG_SEQ].data_arr_idx = SGMII_3_125;
1039 /* SGMII_ELECTRICAL_CONFIG_SEQ seq sequence init */
1040 if (serdes_rev == MV_SERDES_REV_1_2) {
1041 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
1042 sgmii_electrical_config_serdes_rev1_params;
1043 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
1044 sizeof(sgmii_electrical_config_serdes_rev1_params) /
1045 sizeof(struct op_params);
1047 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
1048 sgmii_electrical_config_serdes_rev2_params;
1049 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
1050 sizeof(sgmii_electrical_config_serdes_rev2_params) /
1051 sizeof(struct op_params);
1053 serdes_seq_db[SGMII_ELECTRICAL_CONFIG_SEQ].data_arr_idx = SGMII;
1055 /* SGMII_TX_CONFIG_SEQ sequence init */
1056 serdes_seq_db[SGMII_TX_CONFIG_SEQ1].op_params_ptr =
1057 sata_and_sgmii_tx_config_params1;
1058 serdes_seq_db[SGMII_TX_CONFIG_SEQ1].cfg_seq_size =
1059 sizeof(sata_and_sgmii_tx_config_params1) / sizeof(struct op_params);
1060 serdes_seq_db[SGMII_TX_CONFIG_SEQ1].data_arr_idx = SGMII;
1062 /* SGMII_TX_CONFIG_SEQ sequence init */
1063 if (serdes_rev == MV_SERDES_REV_1_2) {
1064 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].op_params_ptr =
1065 sata_and_sgmii_tx_config_serdes_rev1_params2;
1066 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].cfg_seq_size =
1067 sizeof(sata_and_sgmii_tx_config_serdes_rev1_params2) /
1068 sizeof(struct op_params);
1070 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].op_params_ptr =
1071 sata_and_sgmii_tx_config_serdes_rev2_params2;
1072 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].cfg_seq_size =
1073 sizeof(sata_and_sgmii_tx_config_serdes_rev2_params2) /
1074 sizeof(struct op_params);
1076 serdes_seq_db[SGMII_TX_CONFIG_SEQ2].data_arr_idx = SGMII;
1078 /* PEX_POWER_UP_SEQ sequence init */
1079 if (serdes_rev == MV_SERDES_REV_1_2) {
1080 serdes_seq_db[PEX_POWER_UP_SEQ].op_params_ptr =
1081 pex_and_usb3_power_up_serdes_rev1_params;
1082 serdes_seq_db[PEX_POWER_UP_SEQ].cfg_seq_size =
1083 sizeof(pex_and_usb3_power_up_serdes_rev1_params) /
1084 sizeof(struct op_params);
1086 serdes_seq_db[PEX_POWER_UP_SEQ].op_params_ptr =
1087 pex_and_usb3_power_up_serdes_rev2_params;
1088 serdes_seq_db[PEX_POWER_UP_SEQ].cfg_seq_size =
1089 sizeof(pex_and_usb3_power_up_serdes_rev2_params) /
1090 sizeof(struct op_params);
1092 serdes_seq_db[PEX_POWER_UP_SEQ].data_arr_idx = PEX;
1094 /* PEX_2_5_SPEED_CONFIG_SEQ sequence init */
1095 serdes_seq_db[PEX_2_5_SPEED_CONFIG_SEQ].op_params_ptr =
1096 pex_and_usb3_speed_config_params;
1097 serdes_seq_db[PEX_2_5_SPEED_CONFIG_SEQ].cfg_seq_size =
1098 sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params);
1099 serdes_seq_db[PEX_2_5_SPEED_CONFIG_SEQ].data_arr_idx =
1100 PEXSERDES_SPEED_2_5_GBPS;
1102 /* PEX_5_SPEED_CONFIG_SEQ sequence init */
1103 serdes_seq_db[PEX_5_SPEED_CONFIG_SEQ].op_params_ptr =
1104 pex_and_usb3_speed_config_params;
1105 serdes_seq_db[PEX_5_SPEED_CONFIG_SEQ].cfg_seq_size =
1106 sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params);
1107 serdes_seq_db[PEX_5_SPEED_CONFIG_SEQ].data_arr_idx =
1108 PEXSERDES_SPEED_5_GBPS;
1110 /* PEX_ELECTRICAL_CONFIG_SEQ seq sequence init */
1111 if (serdes_rev == MV_SERDES_REV_1_2) {
1112 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
1113 pex_electrical_config_serdes_rev1_params;
1114 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
1115 sizeof(pex_electrical_config_serdes_rev1_params) /
1116 sizeof(struct op_params);
1118 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
1119 pex_electrical_config_serdes_rev2_params;
1120 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
1121 sizeof(pex_electrical_config_serdes_rev2_params) /
1122 sizeof(struct op_params);
1124 serdes_seq_db[PEX_ELECTRICAL_CONFIG_SEQ].data_arr_idx = PEX;
1126 /* PEX_TX_CONFIG_SEQ1 sequence init */
1127 serdes_seq_db[PEX_TX_CONFIG_SEQ1].op_params_ptr =
1128 pex_and_usb3_tx_config_params1;
1129 serdes_seq_db[PEX_TX_CONFIG_SEQ1].cfg_seq_size =
1130 sizeof(pex_and_usb3_tx_config_params1) / sizeof(struct op_params);
1131 serdes_seq_db[PEX_TX_CONFIG_SEQ1].data_arr_idx = PEX;
1133 /* PEX_TX_CONFIG_SEQ2 sequence init */
1134 serdes_seq_db[PEX_TX_CONFIG_SEQ2].op_params_ptr =
1135 pex_and_usb3_tx_config_params2;
1136 serdes_seq_db[PEX_TX_CONFIG_SEQ2].cfg_seq_size =
1137 sizeof(pex_and_usb3_tx_config_params2) / sizeof(struct op_params);
1138 serdes_seq_db[PEX_TX_CONFIG_SEQ2].data_arr_idx = PEX;
1140 /* PEX_TX_CONFIG_SEQ3 sequence init */
1141 serdes_seq_db[PEX_TX_CONFIG_SEQ3].op_params_ptr =
1142 pex_and_usb3_tx_config_params3;
1143 serdes_seq_db[PEX_TX_CONFIG_SEQ3].cfg_seq_size =
1144 sizeof(pex_and_usb3_tx_config_params3) / sizeof(struct op_params);
1145 serdes_seq_db[PEX_TX_CONFIG_SEQ3].data_arr_idx = PEX;
1147 /* PEX_BY_4_CONFIG_SEQ sequence init */
1148 serdes_seq_db[PEX_BY_4_CONFIG_SEQ].op_params_ptr =
1149 pex_by4_config_params;
1150 serdes_seq_db[PEX_BY_4_CONFIG_SEQ].cfg_seq_size =
1151 sizeof(pex_by4_config_params) / sizeof(struct op_params);
1152 serdes_seq_db[PEX_BY_4_CONFIG_SEQ].data_arr_idx = PEX;
1154 /* PEX_CONFIG_REF_CLOCK_25MHZ_SEQ sequence init */
1155 serdes_seq_db[PEX_CONFIG_REF_CLOCK_25MHZ_SEQ].op_params_ptr =
1156 pex_config_ref_clock25_m_hz;
1157 serdes_seq_db[PEX_CONFIG_REF_CLOCK_25MHZ_SEQ].cfg_seq_size =
1158 sizeof(pex_config_ref_clock25_m_hz) / sizeof(struct op_params);
1159 serdes_seq_db[PEX_CONFIG_REF_CLOCK_25MHZ_SEQ].data_arr_idx = PEX;
1161 /* PEX_ELECTRICAL_CONFIG_REF_CLOCK_40MHZ_SEQ sequence init */
1162 serdes_seq_db[PEX_CONFIG_REF_CLOCK_40MHZ_SEQ].op_params_ptr =
1163 pex_config_ref_clock40_m_hz;
1164 serdes_seq_db[PEX_CONFIG_REF_CLOCK_40MHZ_SEQ].cfg_seq_size =
1165 sizeof(pex_config_ref_clock40_m_hz) / sizeof(struct op_params);
1166 serdes_seq_db[PEX_CONFIG_REF_CLOCK_40MHZ_SEQ].data_arr_idx = PEX;
1168 /* PEX_CONFIG_REF_CLOCK_100MHZ_SEQ sequence init */
1169 serdes_seq_db[PEX_CONFIG_REF_CLOCK_100MHZ_SEQ].op_params_ptr =
1170 pex_config_ref_clock100_m_hz;
1171 serdes_seq_db[PEX_CONFIG_REF_CLOCK_100MHZ_SEQ].cfg_seq_size =
1172 sizeof(pex_config_ref_clock100_m_hz) / sizeof(struct op_params);
1173 serdes_seq_db[PEX_CONFIG_REF_CLOCK_100MHZ_SEQ].data_arr_idx = PEX;
1175 /* USB3_POWER_UP_SEQ sequence init */
1176 if (serdes_rev == MV_SERDES_REV_1_2) {
1177 serdes_seq_db[USB3_POWER_UP_SEQ].op_params_ptr =
1178 pex_and_usb3_power_up_serdes_rev1_params;
1179 serdes_seq_db[USB3_POWER_UP_SEQ].cfg_seq_size =
1180 sizeof(pex_and_usb3_power_up_serdes_rev1_params) /
1181 sizeof(struct op_params);
1183 serdes_seq_db[USB3_POWER_UP_SEQ].op_params_ptr =
1184 pex_and_usb3_power_up_serdes_rev2_params;
1185 serdes_seq_db[USB3_POWER_UP_SEQ].cfg_seq_size =
1186 sizeof(pex_and_usb3_power_up_serdes_rev2_params) /
1187 sizeof(struct op_params);
1189 serdes_seq_db[USB3_POWER_UP_SEQ].data_arr_idx = USB3;
1191 /* USB3_HOST_SPEED_CONFIG_SEQ sequence init */
1192 serdes_seq_db[USB3_HOST_SPEED_CONFIG_SEQ].op_params_ptr =
1193 pex_and_usb3_speed_config_params;
1194 serdes_seq_db[USB3_HOST_SPEED_CONFIG_SEQ].cfg_seq_size =
1195 sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params);
1196 serdes_seq_db[USB3_HOST_SPEED_CONFIG_SEQ].data_arr_idx =
1197 USB3SERDES_SPEED_5_GBPS_HOST;
1199 /* USB3_DEVICE_SPEED_CONFIG_SEQ sequence init */
1200 serdes_seq_db[USB3_DEVICE_SPEED_CONFIG_SEQ].op_params_ptr =
1201 pex_and_usb3_speed_config_params;
1202 serdes_seq_db[USB3_DEVICE_SPEED_CONFIG_SEQ].cfg_seq_size =
1203 sizeof(pex_and_usb3_speed_config_params) / sizeof(struct op_params);
1204 serdes_seq_db[USB3_DEVICE_SPEED_CONFIG_SEQ].data_arr_idx =
1205 USB3SERDES_SPEED_5_GBPS_DEVICE;
1207 /* USB3_ELECTRICAL_CONFIG_SEQ seq sequence init */
1208 if (serdes_rev == MV_SERDES_REV_1_2) {
1209 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
1210 usb3_electrical_config_serdes_rev1_params;
1211 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
1212 sizeof(usb3_electrical_config_serdes_rev1_params) /
1213 sizeof(struct op_params);
1215 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
1216 usb3_electrical_config_serdes_rev2_params;
1217 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
1218 sizeof(usb3_electrical_config_serdes_rev2_params) /
1219 sizeof(struct op_params);
1221 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].data_arr_idx = USB3;
1223 /* USB3_TX_CONFIG_SEQ sequence init */
1224 serdes_seq_db[USB3_TX_CONFIG_SEQ1].op_params_ptr =
1225 pex_and_usb3_tx_config_params1;
1226 serdes_seq_db[USB3_TX_CONFIG_SEQ1].cfg_seq_size =
1227 sizeof(pex_and_usb3_tx_config_params1) / sizeof(struct op_params);
1228 serdes_seq_db[USB3_TX_CONFIG_SEQ1].data_arr_idx = USB3;
1230 /* USB3_TX_CONFIG_SEQ sequence init */
1231 serdes_seq_db[USB3_TX_CONFIG_SEQ2].op_params_ptr =
1232 pex_and_usb3_tx_config_params2;
1233 serdes_seq_db[USB3_TX_CONFIG_SEQ2].cfg_seq_size =
1234 sizeof(pex_and_usb3_tx_config_params2) / sizeof(struct op_params);
1235 serdes_seq_db[USB3_TX_CONFIG_SEQ2].data_arr_idx = USB3;
1237 /* USB3_TX_CONFIG_SEQ sequence init */
1238 serdes_seq_db[USB3_TX_CONFIG_SEQ3].op_params_ptr =
1239 pex_and_usb3_tx_config_params3;
1240 serdes_seq_db[USB3_TX_CONFIG_SEQ3].cfg_seq_size =
1241 sizeof(pex_and_usb3_tx_config_params3) / sizeof(struct op_params);
1242 serdes_seq_db[USB3_TX_CONFIG_SEQ3].data_arr_idx = USB3;
1244 /* USB2_POWER_UP_SEQ sequence init */
1245 serdes_seq_db[USB2_POWER_UP_SEQ].op_params_ptr = usb2_power_up_params;
1246 serdes_seq_db[USB2_POWER_UP_SEQ].cfg_seq_size =
1247 sizeof(usb2_power_up_params) / sizeof(struct op_params);
1248 serdes_seq_db[USB2_POWER_UP_SEQ].data_arr_idx = 0;
1250 /* USB3_DEVICE_CONFIG_SEQ sequence init */
1251 serdes_seq_db[USB3_DEVICE_CONFIG_SEQ].op_params_ptr =
1252 usb3_device_config_params;
1253 serdes_seq_db[USB3_DEVICE_CONFIG_SEQ].cfg_seq_size =
1254 sizeof(usb3_device_config_params) / sizeof(struct op_params);
1255 serdes_seq_db[USB3_DEVICE_CONFIG_SEQ].data_arr_idx = 0; /* Not relevant */
1257 /* SERDES_POWER_DOWN_SEQ sequence init */
1258 serdes_seq_db[SERDES_POWER_DOWN_SEQ].op_params_ptr =
1259 serdes_power_down_params;
1260 serdes_seq_db[SERDES_POWER_DOWN_SEQ].cfg_seq_size =
1261 sizeof(serdes_power_down_params) /
1262 sizeof(struct op_params);
1263 serdes_seq_db[SERDES_POWER_DOWN_SEQ].data_arr_idx = FIRST_CELL;
1265 if (serdes_rev == MV_SERDES_REV_2_1) {
1266 /* QSGMII_POWER_UP_SEQ sequence init */
1267 serdes_seq_db[QSGMII_POWER_UP_SEQ].op_params_ptr =
1268 qsgmii_port_power_up_params;
1269 serdes_seq_db[QSGMII_POWER_UP_SEQ].cfg_seq_size =
1270 sizeof(qsgmii_port_power_up_params) /
1271 sizeof(struct op_params);
1272 serdes_seq_db[QSGMII_POWER_UP_SEQ].data_arr_idx =
1275 /* QSGMII_5_SPEED_CONFIG_SEQ sequence init */
1276 serdes_seq_db[QSGMII_5_SPEED_CONFIG_SEQ].op_params_ptr =
1277 qsgmii_port_speed_config_params;
1278 serdes_seq_db[QSGMII_5_SPEED_CONFIG_SEQ].cfg_seq_size =
1279 sizeof(qsgmii_port_speed_config_params) /
1280 sizeof(struct op_params);
1281 serdes_seq_db[QSGMII_5_SPEED_CONFIG_SEQ].data_arr_idx =
1284 /* QSGMII_ELECTRICAL_CONFIG_SEQ seq sequence init */
1285 serdes_seq_db[QSGMII_ELECTRICAL_CONFIG_SEQ].op_params_ptr =
1286 qsgmii_port_electrical_config_params;
1287 serdes_seq_db[QSGMII_ELECTRICAL_CONFIG_SEQ].cfg_seq_size =
1288 sizeof(qsgmii_port_electrical_config_params) /
1289 sizeof(struct op_params);
1290 serdes_seq_db[QSGMII_ELECTRICAL_CONFIG_SEQ].data_arr_idx =
1293 /* QSGMII_TX_CONFIG_SEQ sequence init */
1294 serdes_seq_db[QSGMII_TX_CONFIG_SEQ1].op_params_ptr =
1295 qsgmii_port_tx_config_params1;
1296 serdes_seq_db[QSGMII_TX_CONFIG_SEQ1].cfg_seq_size =
1297 sizeof(qsgmii_port_tx_config_params1) /
1298 sizeof(struct op_params);
1299 serdes_seq_db[QSGMII_TX_CONFIG_SEQ1].data_arr_idx =
1302 /* QSGMII_TX_CONFIG_SEQ sequence init */
1303 serdes_seq_db[QSGMII_TX_CONFIG_SEQ2].op_params_ptr =
1304 qsgmii_port_tx_config_params2;
1305 serdes_seq_db[QSGMII_TX_CONFIG_SEQ2].cfg_seq_size =
1306 sizeof(qsgmii_port_tx_config_params2) /
1307 sizeof(struct op_params);
1308 serdes_seq_db[QSGMII_TX_CONFIG_SEQ2].data_arr_idx =
1315 enum serdes_seq serdes_type_and_speed_to_speed_seq(enum serdes_type serdes_type,
1316 enum serdes_speed baud_rate)
1318 enum serdes_seq seq_id = SERDES_LAST_SEQ;
1320 DEBUG_INIT_FULL_S("\n### serdes_type_and_speed_to_speed_seq ###\n");
1321 switch (serdes_type) {
1326 if (baud_rate == SERDES_SPEED_2_5_GBPS)
1327 seq_id = PEX_2_5_SPEED_CONFIG_SEQ;
1328 else if (baud_rate == SERDES_SPEED_5_GBPS)
1329 seq_id = PEX_5_SPEED_CONFIG_SEQ;
1333 if (baud_rate == SERDES_SPEED_5_GBPS)
1334 seq_id = USB3_HOST_SPEED_CONFIG_SEQ;
1337 if (baud_rate == SERDES_SPEED_5_GBPS)
1338 seq_id = USB3_DEVICE_SPEED_CONFIG_SEQ;
1344 if (baud_rate == SERDES_SPEED_1_5_GBPS)
1345 seq_id = SATA_1_5_SPEED_CONFIG_SEQ;
1346 else if (baud_rate == SERDES_SPEED_3_GBPS)
1347 seq_id = SATA_3_SPEED_CONFIG_SEQ;
1348 else if (baud_rate == SERDES_SPEED_6_GBPS)
1349 seq_id = SATA_6_SPEED_CONFIG_SEQ;
1354 #ifdef CONFIG_ARMADA_39X
1357 if (baud_rate == SERDES_SPEED_1_25_GBPS)
1358 seq_id = SGMII_1_25_SPEED_CONFIG_SEQ;
1359 else if (baud_rate == SERDES_SPEED_3_125_GBPS)
1360 seq_id = SGMII_3_125_SPEED_CONFIG_SEQ;
1363 seq_id = QSGMII_5_SPEED_CONFIG_SEQ;
1365 #ifdef CONFIG_ARMADA_39X
1367 seq_id = XAUI_3_125_SPEED_CONFIG_SEQ;
1370 seq_id = RXAUI_6_25_SPEED_CONFIG_SEQ;
1374 return SERDES_LAST_SEQ;
1380 static void print_topology_details(const struct serdes_map *serdes_map,
1385 DEBUG_INIT_S("board SerDes lanes topology details:\n");
1387 DEBUG_INIT_S(" | Lane # | Speed | Type |\n");
1388 DEBUG_INIT_S(" --------------------------------\n");
1389 for (lane_num = 0; lane_num < count; lane_num++) {
1390 if (serdes_map[lane_num].serdes_type == DEFAULT_SERDES)
1392 DEBUG_INIT_S(" | ");
1393 DEBUG_INIT_D(hws_get_physical_serdes_num(lane_num), 1);
1394 DEBUG_INIT_S(" | ");
1395 DEBUG_INIT_D(serdes_map[lane_num].serdes_speed, 2);
1396 DEBUG_INIT_S(" | ");
1397 DEBUG_INIT_S((char *)
1398 serdes_type_to_string[serdes_map[lane_num].
1400 DEBUG_INIT_S("\t|\n");
1402 DEBUG_INIT_S(" --------------------------------\n");
1405 int hws_pre_serdes_init_config(void)
1410 * Configure Core PLL
1413 * set PLL parameters
1414 * bits[2:0] =0x3 (Core-PLL Kdiv)
1415 * bits[20:12]=0x9f (Core-PLL Ndiv)
1416 * bits[24:21]=0x7(Core-PLL VCO Band)
1417 * bits[28:25]=0x1(Core-PLL Rlf)
1418 * bits[31:29]=0x2(Core-PLL charge-pump adjust)
1420 reg_write(CORE_PLL_PARAMETERS_REG, 0x42e9f003);
1422 /* Enable PLL Configuration */
1423 data = reg_read(CORE_PLL_CONFIG_REG);
1424 data = SET_BIT(data, 9);
1425 reg_write(CORE_PLL_CONFIG_REG, data);
1430 int serdes_phy_config(void)
1432 struct serdes_map *serdes_map;
1435 DEBUG_INIT_FULL_S("\n### ctrl_high_speed_serdes_phy_config ###\n");
1437 DEBUG_INIT_S("High speed PHY - Version: ");
1438 DEBUG_INIT_S(SERDES_VERSION);
1441 /* Init serdes sequences DB */
1442 if (hws_serdes_seq_init() != MV_OK) {
1443 printf("hws_ctrl_high_speed_serdes_phy_config: Error: Serdes initialization fail\n");
1447 /* Board topology load */
1449 ("ctrl_high_speed_serdes_phy_config: Loading board topology..\n");
1450 CHECK_STATUS(hws_board_topology_load(&serdes_map, &serdes_count));
1451 if (serdes_count > hws_serdes_get_max_lane()) {
1452 printf("Error: too many serdes lanes specified by board\n");
1456 /* print topology */
1457 print_topology_details(serdes_map, serdes_count);
1458 CHECK_STATUS(hws_pre_serdes_init_config());
1460 /* Power-Up sequence */
1462 ("ctrl_high_speed_serdes_phy_config: Starting serdes power up sequence\n");
1464 CHECK_STATUS(hws_power_up_serdes_lanes(serdes_map, serdes_count));
1467 ("\n### ctrl_high_speed_serdes_phy_config ended successfully ###\n");
1469 DEBUG_INIT_S(ENDED_OK);
1474 int serdes_polarity_config(u32 serdes_num, int is_rx)
1478 u8 bit_off = (is_rx) ? 11 : 10;
1480 reg_addr = SERDES_REGS_LANE_BASE_OFFSET(serdes_num) + SYNC_PATTERN_REG;
1481 data = reg_read(reg_addr);
1482 data = SET_BIT(data, bit_off);
1483 reg_write(reg_addr, data);
1488 int hws_power_up_serdes_lanes(struct serdes_map *serdes_map, u8 count)
1490 u32 serdes_id, serdes_lane_num;
1491 enum ref_clock ref_clock;
1492 enum serdes_type serdes_type;
1493 enum serdes_speed serdes_speed;
1494 enum serdes_mode serdes_mode;
1495 int serdes_rx_polarity_swap;
1496 int serdes_tx_polarity_swap;
1497 int is_pex_enabled = 0;
1501 * Flag which indicates that one of the Serdes is of PEX.
1502 * In this case, PEX unit will be initialized after Serdes power-up
1505 DEBUG_INIT_FULL_S("\n### hws_power_up_serdes_lanes ###\n");
1507 /* COMMON PHYS SELECTORS register configuration */
1509 ("hws_power_up_serdes_lanes: Updating COMMON PHYS SELECTORS reg\n");
1510 CHECK_STATUS(hws_update_serdes_phy_selectors(serdes_map, count));
1512 /* per Serdes Power Up */
1513 for (serdes_id = 0; serdes_id < count; serdes_id++) {
1515 ("calling serdes_power_up_ctrl: serdes lane number ");
1516 DEBUG_INIT_FULL_D_10(serdes_lane_num, 1);
1517 DEBUG_INIT_FULL_S("\n");
1519 serdes_lane_num = hws_get_physical_serdes_num(serdes_id);
1520 serdes_type = serdes_map[serdes_id].serdes_type;
1521 serdes_speed = serdes_map[serdes_id].serdes_speed;
1522 serdes_mode = serdes_map[serdes_id].serdes_mode;
1523 serdes_rx_polarity_swap = serdes_map[serdes_id].swap_rx;
1524 serdes_tx_polarity_swap = serdes_map[serdes_id].swap_tx;
1526 /* serdes lane is not in use */
1527 if (serdes_type == DEFAULT_SERDES)
1529 else if (serdes_type <= PEX3) /* PEX type */
1532 ref_clock = hws_serdes_get_ref_clock_val(serdes_type);
1533 if (ref_clock == REF_CLOCK_UNSUPPORTED) {
1535 ("hws_power_up_serdes_lanes: unsupported ref clock\n");
1536 return MV_NOT_SUPPORTED;
1538 CHECK_STATUS(serdes_power_up_ctrl(serdes_lane_num,
1542 serdes_mode, ref_clock));
1544 /* RX Polarity config */
1545 if (serdes_rx_polarity_swap)
1546 CHECK_STATUS(serdes_polarity_config
1547 (serdes_lane_num, 1));
1549 /* TX Polarity config */
1550 if (serdes_tx_polarity_swap)
1551 CHECK_STATUS(serdes_polarity_config
1552 (serdes_lane_num, 0));
1555 if (is_pex_enabled) {
1556 /* Set PEX_TX_CONFIG_SEQ sequence for PEXx4 mode.
1557 After finish the Power_up sequence for all lanes,
1558 the lanes should be released from reset state. */
1559 CHECK_STATUS(hws_pex_tx_config_seq(serdes_map, count));
1561 /* PEX configuration */
1562 CHECK_STATUS(hws_pex_config(serdes_map, count));
1565 /* USB2 configuration */
1566 DEBUG_INIT_FULL_S("hws_power_up_serdes_lanes: init USB2 Phys\n");
1567 CHECK_STATUS(mv_seq_exec(0 /* not relevant */ , USB2_POWER_UP_SEQ));
1570 ("### hws_power_up_serdes_lanes ended successfully ###\n");
1575 int ctrl_high_speed_serdes_phy_config(void)
1577 return hws_ctrl_high_speed_serdes_phy_config();
1580 static int serdes_pex_usb3_pipe_delay_w_a(u32 serdes_num, u8 serdes_type)
1584 /* WA for A380 Z1 relevant for lanes 3,4,5 only */
1585 if (serdes_num >= 3) {
1586 reg_data = reg_read(GENERAL_PURPOSE_RESERVED0_REG);
1587 /* set delay on pipe -
1588 * When lane 3 is connected to a MAC of Pex -> set bit 7 to 1.
1589 * When lane 3 is connected to a MAC of USB3 -> set bit 7 to 0.
1590 * When lane 4 is connected to a MAC of Pex -> set bit 8 to 1.
1591 * When lane 4 is connected to a MAC of USB3 -> set bit 8 to 0.
1592 * When lane 5 is connected to a MAC of Pex -> set bit 8 to 1.
1593 * When lane 5 is connected to a MAC of USB3 -> set bit 8 to 0.
1595 if (serdes_type == PEX)
1596 reg_data |= 1 << (7 + (serdes_num - 3));
1597 if (serdes_type == USB3) {
1599 reg_data &= ~(1 << (7 + (serdes_num - 3)));
1601 reg_write(GENERAL_PURPOSE_RESERVED0_REG, reg_data);
1608 * hws_serdes_pex_ref_clock_satr_get -
1610 * DESCRIPTION: Get the reference clock value from DEVICE_SAMPLE_AT_RESET1_REG
1612 * bit[2] for PEX#0, bit[3] for PEX#1, bit[30] for PEX#2, bit[31]
1614 * If bit=0 --> REF_CLOCK_100MHz
1615 * If bit=1 && DEVICE_SAMPLE_AT_RESET2_REG bit[0]=0
1616 * --> REF_CLOCK_25MHz
1617 * If bit=1 && DEVICE_SAMPLE_AT_RESET2_REG bit[0]=1
1618 * --> REF_CLOCK_40MHz
1620 * INPUT: serdes_type - Type of Serdes
1622 * OUTPUT: pex_satr - Return the REF_CLOCK value:
1623 * REF_CLOCK_25MHz, REF_CLOCK_40MHz or REF_CLOCK_100MHz
1625 * RETURNS: MV_OK - for success
1626 * MV_BAD_PARAM - for fail
1628 int hws_serdes_pex_ref_clock_satr_get(enum serdes_type serdes_type, u32 *pex_satr)
1630 u32 data, reg_satr1;
1632 reg_satr1 = reg_read(DEVICE_SAMPLE_AT_RESET1_REG);
1634 switch (serdes_type) {
1636 data = REF_CLK_SELECTOR_VAL_PEX0(reg_satr1);
1639 data = REF_CLK_SELECTOR_VAL_PEX1(reg_satr1);
1642 data = REF_CLK_SELECTOR_VAL_PEX2(reg_satr1);
1645 data = REF_CLK_SELECTOR_VAL_PEX3(reg_satr1);
1648 printf("%s: Error: SerDes type %d is not supported\n",
1649 __func__, serdes_type);
1650 return MV_BAD_PARAM;
1658 u32 hws_serdes_get_ref_clock_val(enum serdes_type serdes_type)
1661 enum ref_clock ref_clock;
1663 DEBUG_INIT_FULL_S("\n### hws_serdes_get_ref_clock_val ###\n");
1665 if (serdes_type >= LAST_SERDES_TYPE)
1666 return REF_CLOCK_UNSUPPORTED;
1668 /* read ref clock from S@R */
1669 ref_clock = hws_serdes_silicon_ref_clock_get();
1671 if (serdes_type > PEX3) {
1672 /* for all Serdes types but PCIe */
1676 /* for PCIe, need also to check PCIe S@R */
1677 CHECK_STATUS(hws_serdes_pex_ref_clock_satr_get
1678 (serdes_type, &pex_satr));
1680 if (pex_satr == 0) {
1681 return REF_CLOCK_100MHZ;
1682 } else if (pex_satr == 1) {
1683 /* value of 1 means we can use ref clock from SoC (as other Serdes types) */
1687 ("%s: Error: REF_CLK_SELECTOR_VAL for SerDes type %d is wrong\n",
1688 __func__, serdes_type);
1689 return REF_CLOCK_UNSUPPORTED;
1693 int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up,
1694 enum serdes_type serdes_type,
1695 enum serdes_speed baud_rate,
1696 enum serdes_mode serdes_mode, enum ref_clock ref_clock)
1698 u32 sata_idx, pex_idx, sata_port;
1699 enum serdes_seq speed_seq_id;
1703 DEBUG_INIT_FULL_S("\n### serdes_power_up_ctrl ###\n");
1705 if (serdes_power_up == 1) { /* Serdes power up */
1707 ("serdes_power_up_ctrl: executing power up.. ");
1708 DEBUG_INIT_FULL_C("serdes num = ", serdes_num, 2);
1709 DEBUG_INIT_FULL_C("serdes type = ", serdes_type, 2);
1711 DEBUG_INIT_FULL_S("Going access 1");
1713 /* Getting the Speed Select sequence id */
1715 serdes_type_and_speed_to_speed_seq(serdes_type,
1717 if (speed_seq_id == SERDES_LAST_SEQ) {
1719 ("serdes_power_up_ctrl: serdes type %d and speed %d are not supported together\n",
1720 serdes_type, baud_rate);
1722 return MV_BAD_PARAM;
1725 /* Executing power up, ref clock set, speed config and TX config */
1726 switch (serdes_type) {
1731 if (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2) {
1732 CHECK_STATUS(serdes_pex_usb3_pipe_delay_w_a
1736 is_pex_by1 = (serdes_mode == PEX_ROOT_COMPLEX_X1) ||
1737 (serdes_mode == PEX_END_POINT_X1);
1738 pex_idx = serdes_type - PEX0;
1740 if ((is_pex_by1 == 1) || (serdes_type == PEX0)) {
1741 /* For PEX by 4, init only the PEX 0 */
1742 reg_data = reg_read(SOC_CONTROL_REG1);
1743 if (is_pex_by1 == 1)
1746 reg_data &= ~0x4000;
1747 reg_write(SOC_CONTROL_REG1, reg_data);
1750 reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
1753 if (is_pex_by1 == 1)
1757 reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
1761 reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
1765 reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c),
1769 reg_read(((PEX_IF_REGS_BASE(pex_idx)) +
1773 reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x70),
1777 CHECK_STATUS(mv_seq_exec(serdes_num, PEX_POWER_UP_SEQ));
1778 if (is_pex_by1 == 0) {
1780 * for PEX by 4 - use the PEX index as the
1783 serdes_seq_db[PEX_BY_4_CONFIG_SEQ].
1784 data_arr_idx = pex_idx;
1785 CHECK_STATUS(mv_seq_exec
1786 (serdes_num, PEX_BY_4_CONFIG_SEQ));
1789 CHECK_STATUS(hws_ref_clock_set
1790 (serdes_num, serdes_type, ref_clock));
1791 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
1792 CHECK_STATUS(mv_seq_exec
1793 (serdes_num, PEX_ELECTRICAL_CONFIG_SEQ));
1795 if (is_pex_by1 == 1) {
1796 CHECK_STATUS(mv_seq_exec
1797 (serdes_num, PEX_TX_CONFIG_SEQ2));
1798 CHECK_STATUS(mv_seq_exec
1799 (serdes_num, PEX_TX_CONFIG_SEQ3));
1800 CHECK_STATUS(mv_seq_exec
1801 (serdes_num, PEX_TX_CONFIG_SEQ1));
1809 if (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2) {
1810 CHECK_STATUS(serdes_pex_usb3_pipe_delay_w_a
1811 (serdes_num, USB3));
1813 CHECK_STATUS(mv_seq_exec
1814 (serdes_num, USB3_POWER_UP_SEQ));
1815 CHECK_STATUS(hws_ref_clock_set
1816 (serdes_num, serdes_type, ref_clock));
1817 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
1818 if (serdes_type == USB3_DEVICE) {
1819 CHECK_STATUS(mv_seq_exec
1821 USB3_DEVICE_CONFIG_SEQ));
1823 CHECK_STATUS(mv_seq_exec
1824 (serdes_num, USB3_ELECTRICAL_CONFIG_SEQ));
1825 CHECK_STATUS(mv_seq_exec
1826 (serdes_num, USB3_TX_CONFIG_SEQ1));
1827 CHECK_STATUS(mv_seq_exec
1828 (serdes_num, USB3_TX_CONFIG_SEQ2));
1829 CHECK_STATUS(mv_seq_exec
1830 (serdes_num, USB3_TX_CONFIG_SEQ3));
1838 sata_idx = ((serdes_type == SATA0) ||
1839 (serdes_type == SATA1)) ? 0 : 1;
1840 sata_port = ((serdes_type == SATA0) ||
1841 (serdes_type == SATA2)) ? 0 : 1;
1843 CHECK_STATUS(mv_seq_exec
1844 (sata_idx, (sata_port == 0) ?
1845 SATA_PORT_0_ONLY_POWER_UP_SEQ :
1846 SATA_PORT_1_ONLY_POWER_UP_SEQ));
1847 CHECK_STATUS(mv_seq_exec
1848 (serdes_num, SATA_POWER_UP_SEQ));
1849 CHECK_STATUS(hws_ref_clock_set
1850 (serdes_num, serdes_type, ref_clock));
1851 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
1852 CHECK_STATUS(mv_seq_exec
1853 (serdes_num, SATA_ELECTRICAL_CONFIG_SEQ));
1854 CHECK_STATUS(mv_seq_exec
1855 (serdes_num, SATA_TX_CONFIG_SEQ1));
1856 CHECK_STATUS(mv_seq_exec
1857 (sata_idx, (sata_port == 0) ?
1858 SATA_PORT_0_ONLY_TX_CONFIG_SEQ :
1859 SATA_PORT_1_ONLY_TX_CONFIG_SEQ));
1860 CHECK_STATUS(mv_seq_exec
1861 (serdes_num, SATA_TX_CONFIG_SEQ2));
1868 CHECK_STATUS(mv_seq_exec
1869 (serdes_num, SGMII_POWER_UP_SEQ));
1870 CHECK_STATUS(hws_ref_clock_set
1871 (serdes_num, serdes_type, ref_clock));
1872 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
1873 CHECK_STATUS(mv_seq_exec
1874 (serdes_num, SGMII_ELECTRICAL_CONFIG_SEQ));
1875 CHECK_STATUS(mv_seq_exec
1876 (serdes_num, SGMII_TX_CONFIG_SEQ1));
1877 CHECK_STATUS(mv_seq_exec
1878 (serdes_num, SGMII_TX_CONFIG_SEQ2));
1880 /* GBE configuration */
1881 reg_data = reg_read(GBE_CONFIGURATION_REG);
1882 /* write the SGMII index */
1883 reg_data |= 0x1 << (serdes_type - SGMII0);
1884 reg_write(GBE_CONFIGURATION_REG, reg_data);
1888 if (hws_ctrl_serdes_rev_get() < MV_SERDES_REV_2_1)
1889 return MV_NOT_SUPPORTED;
1891 CHECK_STATUS(mv_seq_exec
1892 (serdes_num, QSGMII_POWER_UP_SEQ));
1893 CHECK_STATUS(hws_ref_clock_set
1894 (serdes_num, serdes_type, ref_clock));
1895 CHECK_STATUS(mv_seq_exec(serdes_num, speed_seq_id));
1896 CHECK_STATUS(mv_seq_exec
1898 QSGMII_ELECTRICAL_CONFIG_SEQ));
1899 CHECK_STATUS(mv_seq_exec
1900 (serdes_num, QSGMII_TX_CONFIG_SEQ1));
1901 CHECK_STATUS(mv_seq_exec
1902 (serdes_num, QSGMII_TX_CONFIG_SEQ2));
1907 CHECK_STATUS(serdes_power_up_ctrl_ext
1908 (serdes_num, serdes_power_up, serdes_type,
1909 baud_rate, serdes_mode, ref_clock));
1913 ("serdes_power_up_ctrl: bad serdes_type parameter\n");
1914 return MV_BAD_PARAM;
1916 } else { /* Serdes power down */
1917 DEBUG_INIT_FULL_S("serdes_power_up: executing power down.. ");
1918 DEBUG_INIT_FULL_C("serdes num = ", serdes_num, 1);
1920 CHECK_STATUS(mv_seq_exec(serdes_num, SERDES_POWER_DOWN_SEQ));
1924 "serdes_power_up_ctrl ended successfully for serdes ",
1930 int hws_update_serdes_phy_selectors(struct serdes_map *serdes_map, u8 count)
1932 u32 lane_data, idx, serdes_lane_hw_num, reg_data = 0;
1933 enum serdes_type serdes_type;
1934 enum serdes_mode serdes_mode;
1937 int updated_topology_print = 0;
1939 DEBUG_INIT_FULL_S("\n### hws_update_serdes_phy_selectors ###\n");
1941 ("Updating the COMMON PHYS SELECTORS register with the serdes types\n");
1943 if (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2)
1949 * Updating bits 0-17 in the COMMON PHYS SELECTORS register
1950 * according to the serdes types
1952 for (idx = 0; idx < count; idx++) {
1953 serdes_type = serdes_map[idx].serdes_type;
1954 serdes_mode = serdes_map[idx].serdes_mode;
1955 serdes_lane_hw_num = hws_get_physical_serdes_num(idx);
1958 hws_serdes_get_phy_selector_val(serdes_lane_hw_num,
1961 if (serdes_type == DEFAULT_SERDES)
1964 if (hws_serdes_topology_verify
1965 (serdes_type, idx, serdes_mode) != MV_OK) {
1966 serdes_map[idx].serdes_type =
1968 printf("%s: SerDes lane #%d is disabled\n", __func__,
1969 serdes_lane_hw_num);
1970 updated_topology_print = 1;
1975 * Checking if the board topology configuration includes
1976 * PEXx4 - for the next step
1978 if ((serdes_mode == PEX_END_POINT_X4) ||
1979 (serdes_mode == PEX_ROOT_COMPLEX_X4)) {
1980 /* update lane data to the 3 next SERDES lanes */
1982 common_phys_selectors_pex_by4_lanes
1983 [serdes_lane_hw_num];
1984 if (serdes_type == PEX0)
1988 if (lane_data == NA) {
1990 ("%s: Warning: SerDes lane #%d and type %d are not supported together\n",
1991 __func__, serdes_lane_hw_num, serdes_mode);
1992 serdes_map[idx].serdes_type = DEFAULT_SERDES;
1993 printf("%s: SerDes lane #%d is disabled\n", __func__,
1994 serdes_lane_hw_num);
1999 * Updating the data that will be written to
2000 * COMMON_PHYS_SELECTORS_REG
2002 reg_data |= (lane_data <<
2003 (select_bit_off * serdes_lane_hw_num));
2007 * Check that number of used lanes for XAUI and RXAUI
2008 * (if used) is right
2010 hws_serdes_xaui_topology_verify();
2012 /* Print topology */
2013 if (updated_topology_print)
2014 print_topology_details(serdes_map, count);
2017 * Updating the PEXx4 Enable bit in the COMMON PHYS SELECTORS
2018 * register for PEXx4 mode
2020 reg_data |= (is_pex_x4 == 1) ? (0x1 << PEX_X4_ENABLE_OFFS) : 0;
2022 /* Updating the COMMON PHYS SELECTORS register */
2023 reg_write(COMMON_PHYS_SELECTORS_REG, reg_data);
2028 int hws_ref_clock_set(u32 serdes_num, enum serdes_type serdes_type,
2029 enum ref_clock ref_clock)
2031 u32 data1 = 0, data2 = 0, data3 = 0, reg_data;
2033 DEBUG_INIT_FULL_S("\n### hws_ref_clock_set ###\n");
2035 if (hws_is_serdes_active(serdes_num) != 1) {
2036 printf("%s: SerDes lane #%d is not Active\n", __func__,
2038 return MV_BAD_PARAM;
2041 switch (serdes_type) {
2046 switch (ref_clock) {
2047 case REF_CLOCK_25MHZ:
2048 CHECK_STATUS(mv_seq_exec
2050 PEX_CONFIG_REF_CLOCK_25MHZ_SEQ));
2052 case REF_CLOCK_100MHZ:
2053 CHECK_STATUS(mv_seq_exec
2055 PEX_CONFIG_REF_CLOCK_100MHZ_SEQ));
2057 #ifdef CONFIG_ARMADA_39X
2058 case REF_CLOCK_40MHZ:
2059 CHECK_STATUS(mv_seq_exec
2061 PEX_CONFIG_REF_CLOCK_40MHZ_SEQ));
2066 ("%s: Error: ref_clock %d for SerDes lane #%d, type %d is not supported\n",
2067 __func__, ref_clock, serdes_num, serdes_type);
2068 return MV_BAD_PARAM;
2073 if (ref_clock == REF_CLOCK_25MHZ) {
2074 data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_2;
2075 data2 = GLOBAL_PM_CTRL_REG_25MHZ_VAL;
2076 data3 = LANE_CFG4_REG_25MHZ_VAL;
2077 } else if (ref_clock == REF_CLOCK_40MHZ) {
2078 data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL;
2079 data2 = GLOBAL_PM_CTRL_REG_40MHZ_VAL;
2080 data3 = LANE_CFG4_REG_40MHZ_VAL;
2083 ("hws_ref_clock_set: ref clock is not valid for serdes type %d\n",
2085 return MV_BAD_PARAM;
2096 if (ref_clock == REF_CLOCK_25MHZ) {
2097 data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1;
2098 } else if (ref_clock == REF_CLOCK_40MHZ) {
2099 data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL;
2102 ("hws_ref_clock_set: ref clock is not valid for serdes type %d\n",
2104 return MV_BAD_PARAM;
2107 #ifdef CONFIG_ARMADA_39X
2111 if (ref_clock == REF_CLOCK_25MHZ) {
2112 data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1;
2113 } else if (ref_clock == REF_CLOCK_40MHZ) {
2114 data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL;
2117 ("hws_ref_clock_set: ref clock is not valid for serdes type %d\n",
2119 return MV_BAD_PARAM;
2124 DEBUG_INIT_S("hws_ref_clock_set: not supported serdes type\n");
2125 return MV_BAD_PARAM;
2129 * Write the ref_clock to relevant SELECT_REF_CLOCK_REG bits and
2132 reg_data = reg_read(POWER_AND_PLL_CTRL_REG +
2133 SERDES_REGS_LANE_BASE_OFFSET(serdes_num));
2134 reg_data &= POWER_AND_PLL_CTRL_REG_MASK;
2136 reg_write(POWER_AND_PLL_CTRL_REG +
2137 SERDES_REGS_LANE_BASE_OFFSET(serdes_num), reg_data);
2139 if ((serdes_type == USB3_HOST0) || (serdes_type == USB3_HOST1) ||
2140 (serdes_type == USB3_DEVICE)) {
2141 reg_data = reg_read(GLOBAL_PM_CTRL +
2142 SERDES_REGS_LANE_BASE_OFFSET(serdes_num));
2143 reg_data &= GLOBAL_PM_CTRL_REG_MASK;
2145 reg_write(GLOBAL_PM_CTRL +
2146 SERDES_REGS_LANE_BASE_OFFSET(serdes_num), reg_data);
2148 reg_data = reg_read(LANE_CFG4_REG +
2149 SERDES_REGS_LANE_BASE_OFFSET(serdes_num));
2150 reg_data &= LANE_CFG4_REG_MASK;
2152 reg_write(LANE_CFG4_REG +
2153 SERDES_REGS_LANE_BASE_OFFSET(serdes_num), reg_data);
2160 * hws_pex_tx_config_seq -
2162 * DESCRIPTION: Set PEX_TX_CONFIG_SEQ sequence init for PEXx4 mode
2163 * INPUT: serdes_map - The board topology map
2165 * RETURNS: MV_OK - for success
2166 * MV_BAD_PARAM - for fail
2168 int hws_pex_tx_config_seq(const struct serdes_map *serdes_map, u8 count)
2170 enum serdes_mode serdes_mode;
2171 u32 serdes_lane_id, serdes_lane_hw_num;
2173 DEBUG_INIT_FULL_S("\n### hws_pex_tx_config_seq ###\n");
2176 * For PEXx4: the pex_and_usb3_tx_config_params1/2/3
2177 * configurations should run by setting each sequence for
2181 /* relese pipe soft reset for all lanes */
2182 for (serdes_lane_id = 0; serdes_lane_id < count; serdes_lane_id++) {
2183 serdes_mode = serdes_map[serdes_lane_id].serdes_mode;
2184 serdes_lane_hw_num =
2185 hws_get_physical_serdes_num(serdes_lane_id);
2187 if ((serdes_mode == PEX_ROOT_COMPLEX_X4) ||
2188 (serdes_mode == PEX_END_POINT_X4)) {
2189 CHECK_STATUS(mv_seq_exec
2190 (serdes_lane_hw_num, PEX_TX_CONFIG_SEQ1));
2194 /* set phy soft reset for all lanes */
2195 for (serdes_lane_id = 0; serdes_lane_id < count; serdes_lane_id++) {
2196 serdes_mode = serdes_map[serdes_lane_id].serdes_mode;
2197 serdes_lane_hw_num =
2198 hws_get_physical_serdes_num(serdes_lane_id);
2199 if ((serdes_mode == PEX_ROOT_COMPLEX_X4) ||
2200 (serdes_mode == PEX_END_POINT_X4)) {
2201 CHECK_STATUS(mv_seq_exec
2202 (serdes_lane_hw_num, PEX_TX_CONFIG_SEQ2));
2206 /* set phy soft reset for all lanes */
2207 for (serdes_lane_id = 0; serdes_lane_id < count; serdes_lane_id++) {
2208 serdes_mode = serdes_map[serdes_lane_id].serdes_mode;
2209 serdes_lane_hw_num =
2210 hws_get_physical_serdes_num(serdes_lane_id);
2211 if ((serdes_mode == PEX_ROOT_COMPLEX_X4) ||
2212 (serdes_mode == PEX_END_POINT_X4)) {
2213 CHECK_STATUS(mv_seq_exec
2214 (serdes_lane_hw_num, PEX_TX_CONFIG_SEQ3));