1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) Marvell International Ltd. and its affiliates
10 #include "high_speed_env_spec.h"
12 /* Direct access to PEX0 Root Port's PCIe Capability structure */
13 #define PEX0_RP_PCIE_CFG_OFFSET (0x00080000 + 0x60)
15 /* SOC_CONTROL_REG1 fields */
16 #define PCIE0_ENABLE_OFFS 0
17 #define PCIE0_ENABLE_MASK (0x1 << PCIE0_ENABLE_OFFS)
18 #define PCIE1_ENABLE_OFFS 1
19 #define PCIE1_ENABLE_MASK (0x1 << PCIE1_ENABLE_OFFS)
20 #define PCIE2_ENABLE_OFFS 2
21 #define PCIE2_ENABLE_MASK (0x1 << PCIE2_ENABLE_OFFS)
22 #define PCIE3_ENABLE_OFFS 3
23 #define PCIE4_ENABLE_MASK (0x1 << PCIE3_ENABLE_OFFS)
25 int hws_pex_config(const struct serdes_map *serdes_map, u8 count);
26 void board_pex_config(void);