arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Marvell International Ltd. and its affiliates
   4  */
   5
   6 #include <common.h>
   7 #include <spl.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/cpu.h>
  10 #include <asm/arch/soc.h>
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13
  14 #include "ctrl_pex.h"
  15 #include "sys_env_lib.h"
  16
  17 int hws_pex_config(const struct serdes_map *serdes_map, u8 count)
  18 {
  19         enum serdes_type serdes_type;
  20         u32 idx, tmp;
  21
  22         DEBUG_INIT_FULL_S("\n### hws_pex_config ###\n");
  23
  24         tmp = reg_read(SOC_CONTROL_REG1);
  25         tmp &= ~0x03;
  26
  27         for (idx = 0; idx < count; idx++) {
  28                 serdes_type = serdes_map[idx].serdes_type;
  29                 if ((serdes_type != PEX0) &&
  30                     ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
  31                      (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
  32                         /* for PEX by4 - relevant for the first port only */
  33                         continue;
  34                 }
  35
  36                 switch (serdes_type) {
  37                 case PEX0:
  38                         tmp |= 0x1 << PCIE0_ENABLE_OFFS;
  39                         break;
  40                 case PEX1:
  41                         tmp |= 0x1 << PCIE1_ENABLE_OFFS;
  42                         break;
  43                 case PEX2:
  44                         tmp |= 0x1 << PCIE2_ENABLE_OFFS;
  45                         break;
  46                 case PEX3:
  47                         tmp |= 0x1 << PCIE3_ENABLE_OFFS;
  48                         break;
  49                 default:
  50                         break;
  51                 }
  52         }
  53
  54         reg_write(SOC_CONTROL_REG1, tmp);
  55
  56         return MV_OK;
  57 }