1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
10 #include <linux/mbus.h>
12 #include <asm/pl310.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
17 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
18 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
20 static struct mbus_win windows[] = {
22 { MBUS_SPI_BASE, MBUS_SPI_SIZE,
23 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
26 { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
27 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
29 #ifdef CONFIG_ARMADA_MSYS
31 { MBUS_DFX_BASE, MBUS_DFX_SIZE, CPU_TARGET_DFX, 0 },
35 void lowlevel_init(void)
38 * Dummy implementation, we only need LOWLEVEL_INIT
39 * on Armada to configure CP15 in start.S / cpu_init_cp15()
43 void reset_cpu(unsigned long ignored)
45 struct mvebu_system_registers *reg =
46 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
48 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask);
49 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst);
54 int mvebu_soc_family(void)
56 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
65 return MVEBU_SOC_A375;
70 return MVEBU_SOC_A38X;
75 return MVEBU_SOC_MSYS;
78 return MVEBU_SOC_UNKNOWN;
81 #if defined(CONFIG_DISPLAY_CPUINFO)
83 #if defined(CONFIG_ARMADA_375)
84 /* SAR frequency values for Armada 375 */
85 static const struct sar_freq_modes sar_freq_tab[] = {
86 { 0, 0x0, 266, 133, 266 },
87 { 1, 0x0, 333, 167, 167 },
88 { 2, 0x0, 333, 167, 222 },
89 { 3, 0x0, 333, 167, 333 },
90 { 4, 0x0, 400, 200, 200 },
91 { 5, 0x0, 400, 200, 267 },
92 { 6, 0x0, 400, 200, 400 },
93 { 7, 0x0, 500, 250, 250 },
94 { 8, 0x0, 500, 250, 334 },
95 { 9, 0x0, 500, 250, 500 },
96 { 10, 0x0, 533, 267, 267 },
97 { 11, 0x0, 533, 267, 356 },
98 { 12, 0x0, 533, 267, 533 },
99 { 13, 0x0, 600, 300, 300 },
100 { 14, 0x0, 600, 300, 400 },
101 { 15, 0x0, 600, 300, 600 },
102 { 16, 0x0, 666, 333, 333 },
103 { 17, 0x0, 666, 333, 444 },
104 { 18, 0x0, 666, 333, 666 },
105 { 19, 0x0, 800, 400, 267 },
106 { 20, 0x0, 800, 400, 400 },
107 { 21, 0x0, 800, 400, 534 },
108 { 22, 0x0, 900, 450, 300 },
109 { 23, 0x0, 900, 450, 450 },
110 { 24, 0x0, 900, 450, 600 },
111 { 25, 0x0, 1000, 500, 500 },
112 { 26, 0x0, 1000, 500, 667 },
113 { 27, 0x0, 1000, 333, 500 },
114 { 28, 0x0, 400, 400, 400 },
115 { 29, 0x0, 1100, 550, 550 },
116 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
118 #elif defined(CONFIG_ARMADA_38X)
119 /* SAR frequency values for Armada 38x */
120 static const struct sar_freq_modes sar_freq_tab[] = {
121 { 0x0, 0x0, 666, 333, 333 },
122 { 0x2, 0x0, 800, 400, 400 },
123 { 0x4, 0x0, 1066, 533, 533 },
124 { 0x6, 0x0, 1200, 600, 600 },
125 { 0x8, 0x0, 1332, 666, 666 },
126 { 0xc, 0x0, 1600, 800, 800 },
127 { 0x10, 0x0, 1866, 933, 933 },
128 { 0x13, 0x0, 2000, 1000, 933 },
129 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
131 #elif defined(CONFIG_ARMADA_MSYS)
132 static const struct sar_freq_modes sar_freq_tab[] = {
133 { 0x0, 0x0, 400, 400, 400 },
134 { 0x2, 0x0, 667, 333, 667 },
135 { 0x3, 0x0, 800, 400, 800 },
136 { 0x5, 0x0, 800, 400, 800 },
137 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
140 /* SAR frequency values for Armada XP */
141 static const struct sar_freq_modes sar_freq_tab[] = {
142 { 0xa, 0x5, 800, 400, 400 },
143 { 0x1, 0x5, 1066, 533, 533 },
144 { 0x2, 0x5, 1200, 600, 600 },
145 { 0x2, 0x9, 1200, 600, 400 },
146 { 0x3, 0x5, 1333, 667, 667 },
147 { 0x4, 0x5, 1500, 750, 750 },
148 { 0x4, 0x9, 1500, 750, 500 },
149 { 0xb, 0x9, 1600, 800, 533 },
150 { 0xb, 0xa, 1600, 800, 640 },
151 { 0xb, 0x5, 1600, 800, 800 },
152 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
156 void get_sar_freq(struct sar_freq_modes *sar_freq)
162 #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS)
163 val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
165 val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
167 freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
168 #if defined(SAR2_CPU_FREQ_MASK)
170 * Shift CPU0 clock frequency select bit from SAR2 register
171 * into correct position
173 freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
174 >> SAR2_CPU_FREQ_OFFS) << 3;
176 for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
177 if (sar_freq_tab[i].val == freq) {
178 #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS)
179 *sar_freq = sar_freq_tab[i];
185 ffc = (val & SAR_FFC_FREQ_MASK) >>
187 for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
188 if (sar_freq_tab[k].ffc == ffc) {
189 *sar_freq = sar_freq_tab[k];
198 /* SAR value not found, return 0 for frequencies */
199 *sar_freq = sar_freq_tab[i - 1];
202 int print_cpuinfo(void)
204 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
205 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
206 struct sar_freq_modes sar_freq;
232 case SOC_98DX3236_ID:
235 case SOC_98DX3336_ID:
238 case SOC_98DX4251_ID:
246 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
255 printf("?? (%x)", revid);
260 if (mvebu_soc_family() == MVEBU_SOC_A375) {
262 case MV_88F67XX_A0_ID:
266 printf("?? (%x)", revid);
271 if (mvebu_soc_family() == MVEBU_SOC_A38X) {
273 case MV_88F68XX_Z1_ID:
276 case MV_88F68XX_A0_ID:
279 case MV_88F68XX_B0_ID:
283 printf("?? (%x)", revid);
288 if (mvebu_soc_family() == MVEBU_SOC_MSYS) {
297 printf("?? (%x)", revid);
302 get_sar_freq(&sar_freq);
303 printf(" at %d MHz\n", sar_freq.p_clk);
307 #endif /* CONFIG_DISPLAY_CPUINFO */
310 * This function initialize Controller DRAM Fastpath windows.
311 * It takes the CS size information from the 0x1500 scratch registers
312 * and sets the correct windows sizes and base addresses accordingly.
314 * These values are set in the scratch registers by the Marvell
315 * DDR3 training code, which is executed by the SPL before the
316 * main payload (U-Boot) is executed.
318 static void update_sdram_window_sizes(void)
324 for (i = 0; i < SDRAM_MAX_CS; i++) {
325 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
327 size |= ~(SDRAM_ADDR_MASK);
329 /* Set Base Address */
330 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
331 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
334 * Check if out of max window size and resize
337 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
338 ~(SDRAM_ADDR_MASK)) | 1;
339 temp |= (size & SDRAM_ADDR_MASK);
340 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
342 base += ((u64)size + 1);
345 * Disable window if not used, otherwise this
346 * leads to overlapping enabled windows with
347 * pretty strange results
349 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
354 void mmu_disable(void)
357 "mrc p15, 0, r0, c1, c0, 0\n"
359 "mcr p15, 0, r0, c1, c0, 0\n");
362 #ifdef CONFIG_ARCH_CPU_INIT
363 static void set_cbar(u32 addr)
365 asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
368 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
369 #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
370 #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \
371 (((addr) & 0xF) << 6))
372 #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \
373 (((reg) & 0xF) << 2))
375 static void setup_usb_phys(void)
383 /* Setup PLL frequency */
384 /* USB REF frequency = 25 MHz */
385 clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
387 /* Power up PLL and PHY channel */
388 setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));
390 /* Assert VCOCAL_START */
391 setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));
396 * USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
399 for (dev = 0; dev < 3; dev++) {
400 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));
402 /* Assert REG_RCAL_START in channel REG 1 */
403 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
405 clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
410 * This function is not called from the SPL U-Boot version
412 int arch_cpu_init(void)
414 struct pl310_regs *const pl310 =
415 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
418 * Only with disabled MMU its possible to switch the base
419 * register address on Armada 38x. Without this the SDRAM
420 * located at >= 0x4000.0000 is also not accessible, as its
421 * still locked to cache.
425 /* Linux expects the internal registers to be at 0xf1000000 */
426 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
427 set_cbar(SOC_REGS_PHY_BASE + 0xC000);
430 * From this stage on, the SoC detection is working. As we have
431 * configured the internal register base to the value used
432 * in the macros / defines in the U-Boot header (soc.h).
435 if (mvebu_soc_family() == MVEBU_SOC_A38X) {
437 * To fully release / unlock this area from cache, we need
438 * to flush all caches and disable the L2 cache.
442 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
446 * We need to call mvebu_mbus_probe() before calling
447 * update_sdram_window_sizes() as it disables all previously
448 * configured mbus windows and then configures them as
449 * required for U-Boot. Calling update_sdram_window_sizes()
450 * without this configuration will not work, as the internal
451 * registers can't be accessed reliably because of potenial
453 * After updating the SDRAM access windows we need to call
454 * mvebu_mbus_probe() again, as this now correctly configures
455 * the SDRAM areas that are later used by the MVEBU drivers
460 * First disable all windows
462 mvebu_mbus_probe(NULL, 0);
464 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
466 * Now the SDRAM access windows can be reconfigured using
467 * the information in the SDRAM scratch pad registers
469 update_sdram_window_sizes();
473 * Finally the mbus windows can be configured with the
474 * updated SDRAM sizes
476 mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
478 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
479 /* Enable GBE0, GBE1, LCD and NFC PUP */
480 clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
481 GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
482 NAND_PUP_EN | SPI_PUP_EN);
484 /* Configure USB PLL and PHYs on AXP */
488 /* Enable NAND and NAND arbiter */
489 clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);
491 /* Disable MBUS error propagation */
492 clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
496 #endif /* CONFIG_ARCH_CPU_INIT */
498 u32 mvebu_get_nand_clock(void)
502 if (mvebu_soc_family() == MVEBU_SOC_A38X)
503 reg = MVEBU_DFX_DIV_CLK_CTRL(1);
504 else if (mvebu_soc_family() == MVEBU_SOC_MSYS)
505 reg = MVEBU_DFX_DIV_CLK_CTRL(8);
507 reg = MVEBU_CORE_DIV_CLK_CTRL(1);
509 return CONFIG_SYS_MVEBU_PLL_CLOCK /
511 NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
515 * SOC specific misc init
517 #if defined(CONFIG_ARCH_MISC_INIT)
518 int arch_misc_init(void)
520 /* Nothing yet, perhaps we need something here later */
523 #endif /* CONFIG_ARCH_MISC_INIT */
525 #if defined(CONFIG_MMC_SDHCI_MV) && !defined(CONFIG_DM_MMC)
526 int board_mmc_init(bd_t *bis)
528 mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
529 SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
535 #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
536 #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
538 #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
539 #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
540 #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
542 static void ahci_mvebu_mbus_config(void __iomem *base)
544 const struct mbus_dram_target_info *dram;
547 /* mbus is not initialized in SPL; keep the ROM settings */
548 if (IS_ENABLED(CONFIG_SPL_BUILD))
551 dram = mvebu_mbus_dram_info();
553 for (i = 0; i < 4; i++) {
554 writel(0, base + AHCI_WINDOW_CTRL(i));
555 writel(0, base + AHCI_WINDOW_BASE(i));
556 writel(0, base + AHCI_WINDOW_SIZE(i));
559 for (i = 0; i < dram->num_cs; i++) {
560 const struct mbus_dram_window *cs = dram->cs + i;
562 writel((cs->mbus_attr << 8) |
563 (dram->mbus_dram_target_id << 4) | 1,
564 base + AHCI_WINDOW_CTRL(i));
565 writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
566 writel(((cs->size - 1) & 0xffff0000),
567 base + AHCI_WINDOW_SIZE(i));
571 static void ahci_mvebu_regret_option(void __iomem *base)
574 * Enable the regret bit to allow the SATA unit to regret a
575 * request that didn't receive an acknowlegde and avoid a
578 writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
579 writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
582 int board_ahci_enable(void)
584 ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
585 ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
590 #ifdef CONFIG_SCSI_AHCI_PLAT
593 printf("MVEBU SATA INIT\n");
595 ahci_init((void __iomem *)MVEBU_SATA0_BASE);
599 #ifdef CONFIG_USB_XHCI_MVEBU
600 #define USB3_MAX_WINDOWS 4
601 #define USB3_WIN_CTRL(w) (0x0 + ((w) * 8))
602 #define USB3_WIN_BASE(w) (0x4 + ((w) * 8))
604 static void xhci_mvebu_mbus_config(void __iomem *base,
605 const struct mbus_dram_target_info *dram)
609 for (i = 0; i < USB3_MAX_WINDOWS; i++) {
610 writel(0, base + USB3_WIN_CTRL(i));
611 writel(0, base + USB3_WIN_BASE(i));
614 for (i = 0; i < dram->num_cs; i++) {
615 const struct mbus_dram_window *cs = dram->cs + i;
617 /* Write size, attributes and target id to control register */
618 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
619 (dram->mbus_dram_target_id << 4) | 1,
620 base + USB3_WIN_CTRL(i));
622 /* Write base address to base register */
623 writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(i));
627 int board_xhci_enable(fdt_addr_t base)
629 const struct mbus_dram_target_info *dram;
631 printf("MVEBU XHCI INIT controller @ 0x%lx\n", base);
633 dram = mvebu_mbus_dram_info();
634 xhci_mvebu_mbus_config((void __iomem *)base, dram);
640 void enable_caches(void)
642 /* Avoid problem with e.g. neta ethernet driver */
643 invalidate_dcache_all();
646 * Armada 375 still has some problems with d-cache enabled in the
647 * ethernet driver (mvpp2). So lets keep the d-cache disabled
648 * until this is solved.
650 if (mvebu_soc_family() != MVEBU_SOC_A375) {
651 /* Enable D-cache. I-cache is already enabled in start.S */
656 void v7_outer_cache_enable(void)
658 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
659 struct pl310_regs *const pl310 =
660 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
663 /* The L2 cache is already disabled at this point */
666 * For Aurora cache in no outer mode, enable via the CP15
667 * coprocessor broadcasting of cache commands to L2.
669 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
670 u |= BIT(8); /* Set the FW bit */
671 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
675 /* Enable the L2 cache */
676 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
680 void v7_outer_cache_disable(void)
682 struct pl310_regs *const pl310 =
683 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
685 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);