1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4 * Copyright (C) 2020 Marek Behun <marek.behun@nic.cz>
11 #include <fdt_support.h>
13 #include <asm/global_data.h>
14 #include <linux/bitops.h>
15 #include <linux/libfdt.h>
17 #include <asm/system.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/soc.h>
20 #include <asm/armv8/mmu.h>
24 #define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800))
26 #define MVEBU_TEST_PIN_LATCH_N (MVEBU_GPIO_NB_REG_BASE + 0x8)
27 #define MVEBU_XTAL_MODE_MASK BIT(9)
28 #define MVEBU_XTAL_MODE_OFFS 9
29 #define MVEBU_XTAL_CLOCK_25MHZ 0x0
30 #define MVEBU_XTAL_CLOCK_40MHZ 0x1
32 #define MVEBU_NB_WARM_RST_REG (MVEBU_GPIO_NB_REG_BASE + 0x40)
33 #define MVEBU_NB_WARM_RST_MAGIC_NUM 0x1d1e
35 /* Armada 3700 CPU Address Decoder registers */
36 #define MVEBU_CPU_DEC_WIN_REG_BASE (size_t)(MVEBU_REGISTER(0xcf00))
37 #define MVEBU_CPU_DEC_WIN_CTRL(w) \
38 (MVEBU_CPU_DEC_WIN_REG_BASE + ((w) << 4))
39 #define MVEBU_CPU_DEC_WIN_CTRL_EN BIT(0)
40 #define MVEBU_CPU_DEC_WIN_CTRL_TGT_MASK 0xf
41 #define MVEBU_CPU_DEC_WIN_CTRL_TGT_OFFS 4
42 #define MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM 0
43 #define MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE 2
44 #define MVEBU_CPU_DEC_WIN_SIZE(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0x4)
45 #define MVEBU_CPU_DEC_WIN_BASE(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0x8)
46 #define MVEBU_CPU_DEC_WIN_REMAP(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0xc)
47 #define MVEBU_CPU_DEC_WIN_GRANULARITY 16
48 #define MVEBU_CPU_DEC_WINS 5
50 #define MAX_MEM_MAP_REGIONS (MVEBU_CPU_DEC_WINS + 2)
52 #define A3700_PTE_BLOCK_NORMAL \
53 (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE)
54 #define A3700_PTE_BLOCK_DEVICE \
55 (PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE)
57 DECLARE_GLOBAL_DATA_PTR;
59 static struct mm_region mvebu_mem_map[MAX_MEM_MAP_REGIONS] = {
63 * Don't remove this, a3700_build_mem_map needs it.
65 .phys = SOC_REGS_PHY_BASE,
66 .virt = SOC_REGS_PHY_BASE,
67 .size = 0x02000000UL, /* 32MiB internal registers */
68 .attrs = A3700_PTE_BLOCK_DEVICE
72 struct mm_region *mem_map = mvebu_mem_map;
74 static int get_cpu_dec_win(int win, u32 *tgt, u32 *base, u32 *size)
78 reg = readl(MVEBU_CPU_DEC_WIN_CTRL(win));
79 if (!(reg & MVEBU_CPU_DEC_WIN_CTRL_EN))
83 reg >>= MVEBU_CPU_DEC_WIN_CTRL_TGT_OFFS;
84 reg &= MVEBU_CPU_DEC_WIN_CTRL_TGT_MASK;
89 reg = readl(MVEBU_CPU_DEC_WIN_BASE(win));
90 *base = reg << MVEBU_CPU_DEC_WIN_GRANULARITY;
95 * Window size is encoded as the number of 1s from LSB to MSB,
96 * followed by 0s. The number of 1s specifies the size in 64 KiB
99 reg = readl(MVEBU_CPU_DEC_WIN_SIZE(win));
100 *size = ((reg + 1) << MVEBU_CPU_DEC_WIN_GRANULARITY);
107 * Builds mem_map according to CPU Address Decoder settings, which were set by
108 * the TIMH image on the Cortex-M3 secure processor, or by ARM Trusted Firmware
110 static void build_mem_map(void)
115 for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
119 /* skip disabled windows */
120 if (get_cpu_dec_win(win, &tgt, &base, &size))
123 if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
124 attrs = A3700_PTE_BLOCK_NORMAL;
125 else if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE)
126 attrs = A3700_PTE_BLOCK_DEVICE;
128 /* skip windows with other targets */
131 mvebu_mem_map[region].phys = base;
132 mvebu_mem_map[region].virt = base;
133 mvebu_mem_map[region].size = size;
134 mvebu_mem_map[region].attrs = attrs;
138 /* add list terminator */
139 mvebu_mem_map[region].size = 0;
140 mvebu_mem_map[region].attrs = 0;
143 void enable_caches(void)
151 int a3700_dram_init(void)
156 for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
159 /* skip disabled windows */
160 if (get_cpu_dec_win(win, &tgt, &base, &size))
163 /* skip non-DRAM windows */
164 if (tgt != MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
168 * It is possible that one image was built for boards with
169 * different RAM sizes, for example 512 MiB and 1 GiB.
170 * We therefore try to determine the actual RAM size in the
171 * window with get_ram_size.
173 gd->ram_size += get_ram_size((void *)(size_t)base, size);
179 struct a3700_dram_window {
183 static int dram_win_cmp(const void *a, const void *b)
187 ab = ((const struct a3700_dram_window *)a)->base;
188 bb = ((const struct a3700_dram_window *)b)->base;
198 int a3700_dram_init_banksize(void)
200 struct a3700_dram_window dram_wins[MVEBU_CPU_DEC_WINS];
201 int bank, win, ndram_wins;
206 for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
209 /* skip disabled windows */
210 if (get_cpu_dec_win(win, &tgt, &base, &size))
213 /* skip non-DRAM windows */
214 if (tgt != MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
217 dram_wins[win].base = base;
218 dram_wins[win].size = size;
222 qsort(dram_wins, ndram_wins, sizeof(dram_wins[0]), dram_win_cmp);
227 for (win = 0; win < ndram_wins; ++win) {
228 /* again determining actual RAM size as in a3700_dram_init */
229 size = get_ram_size((void *)dram_wins[win].base,
230 dram_wins[win].size);
233 * Check if previous window ends as the current starts. If yes,
234 * merge these windows into one "bank". This is possible by this
235 * simple check thanks to mem_map regions being qsorted in
238 if (last_end == dram_wins[win].base) {
239 gd->bd->bi_dram[bank - 1].size += size;
242 if (bank == CONFIG_NR_DRAM_BANKS) {
243 printf("Need more CONFIG_NR_DRAM_BANKS\n");
247 gd->bd->bi_dram[bank].start = dram_wins[win].base;
248 gd->bd->bi_dram[bank].size = size;
249 last_end = dram_wins[win].base + size;
255 * If there is more place for DRAM BANKS definitions than needed, fill
256 * the rest with zeros.
258 for (; bank < CONFIG_NR_DRAM_BANKS; ++bank) {
259 gd->bd->bi_dram[bank].start = 0;
260 gd->bd->bi_dram[bank].size = 0;
266 static u32 find_pcie_window_base(void)
270 for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
273 /* skip disabled windows */
274 if (get_cpu_dec_win(win, &tgt, &base, NULL))
277 if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE)
284 static int fdt_setprop_inplace_u32_partial(void *blob, int node,
288 val = cpu_to_fdt32(val);
290 return fdt_setprop_inplace_namelen_partial(blob, node, name,
296 int a3700_fdt_fix_pcie_regions(void *blob)
298 int acells, pacells, scells;
299 u32 base, fix_offset;
304 base = find_pcie_window_base();
308 node = fdt_node_offset_by_compatible(blob, -1, "marvell,armada-3700-pcie");
312 ranges = fdt_getprop(blob, node, "ranges", &len);
313 if (!ranges || len % sizeof(u32))
317 * The "ranges" property is an array of
318 * { <child address> <parent address> <size in child address space> }
320 * All 3 elements can span a diffent number of cells. Fetch their sizes.
322 pnode = fdt_parent_offset(blob, node);
323 acells = fdt_address_cells(blob, node);
324 pacells = fdt_address_cells(blob, pnode);
325 scells = fdt_size_cells(blob, node);
327 /* Child PCI addresses always use 3 cells */
331 /* Calculate fixup offset from first child address (in last cell) */
332 fix_offset = base - fdt32_to_cpu(ranges[2]);
334 /* If fixup offset is zero then there is nothing to fix */
339 * Fix address (last cell) of each child address and each parent
342 for (i = 0; i < len / sizeof(u32); i += acells + pacells + scells) {
345 /* fix child address */
346 idx = i + acells - 1;
347 ret = fdt_setprop_inplace_u32_partial(blob, node, "ranges", idx,
348 fdt32_to_cpu(ranges[idx]) +
353 /* fix parent address */
354 idx = i + acells + pacells - 1;
355 ret = fdt_setprop_inplace_u32_partial(blob, node, "ranges", idx,
356 fdt32_to_cpu(ranges[idx]) +
368 * Write magic number of 0x1d1e to North Bridge Warm Reset register
369 * to trigger warm reset
371 writel(MVEBU_NB_WARM_RST_MAGIC_NUM, MVEBU_NB_WARM_RST_REG);
377 * return: reference clock in MHz (25 or 40)
379 u32 get_ref_clk(void)
383 regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
384 MVEBU_XTAL_MODE_OFFS;
386 if (regval == MVEBU_XTAL_CLOCK_25MHZ)