1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
10 #include <asm/cache.h>
11 #include <asm/global_data.h>
12 #include <asm/ptrace.h>
13 #include <linux/libfdt.h>
14 #include <linux/sizes.h>
17 #include <asm/system.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/soc.h>
20 #include <asm/armv8/mmu.h>
22 DECLARE_GLOBAL_DATA_PTR;
25 * Not all memory is mapped in the MMU. So we need to restrict the
26 * memory size so that U-Boot does not try to access it. Also, the
27 * internal registers are located at 0xf000.0000 - 0xffff.ffff.
28 * Currently only 2GiB are mapped for system memory. This is what
29 * we pass to the U-Boot subsystem here.
31 #define USABLE_RAM_SIZE 0x80000000
33 ulong board_get_usable_ram_top(ulong total_size)
35 if (gd->ram_size > USABLE_RAM_SIZE)
36 return USABLE_RAM_SIZE;
42 * On ARMv8, MBus is not configured in U-Boot. To enable compilation
43 * of the already implemented drivers, lets add a dummy version of
44 * this function so that linking does not fail.
46 const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
51 __weak int dram_init_banksize(void)
53 if (CONFIG_IS_ENABLED(ARMADA_8K))
54 return a8k_dram_init_banksize();
55 else if (CONFIG_IS_ENABLED(ARMADA_3700))
56 return a3700_dram_init_banksize();
58 return fdtdec_setup_memory_banksize();
61 __weak int dram_init(void)
63 if (CONFIG_IS_ENABLED(ARMADA_8K)) {
64 gd->ram_size = a8k_dram_scan_ap_sz();
65 if (gd->ram_size != 0)
69 if (CONFIG_IS_ENABLED(ARMADA_3700))
70 return a3700_dram_init();
72 if (fdtdec_setup_mem_size_base() != 0)
78 int arch_cpu_init(void)
80 /* Nothing to do (yet) */
84 int arch_early_init_r(void)
91 * Loop over all MISC uclass drivers to call the comphy code
92 * and init all CP110 devices enabled in the DT
96 /* Call the comphy code via the MISC uclass driver */
97 ret = uclass_get_device(UCLASS_MISC, i++, &dev);
99 /* We're done, once no further CP110 device is found */
104 /* Cause the SATA device to do its early init */
105 uclass_first_device(UCLASS_AHCI, &dev);
108 /* Trigger PCIe devices detection */