arch/arm/mach-meson/eth.c

   1 /*
   2  * Copyright (C) 2016 BayLibre, SAS
   3  * Author: Neil Armstrong <narmstrong@baylibre.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/gxbb.h>
  12 #include <asm/arch/eth.h>
  13 #include <phy.h>
  14
  15 /* Configure the Ethernet MAC with the requested interface mode
  16  * with some optional flags.
  17  */
  18 void meson_gx_eth_init(phy_interface_t mode, unsigned int flags)
  19 {
  20         switch (mode) {
  21         case PHY_INTERFACE_MODE_RGMII:
  22         case PHY_INTERFACE_MODE_RGMII_ID:
  23         case PHY_INTERFACE_MODE_RGMII_RXID:
  24         case PHY_INTERFACE_MODE_RGMII_TXID:
  25                 /* Set RGMII mode */
  26                 setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF |
  27                              GXBB_ETH_REG_0_TX_PHASE(1) |
  28                              GXBB_ETH_REG_0_TX_RATIO(4) |
  29                              GXBB_ETH_REG_0_PHY_CLK_EN |
  30                              GXBB_ETH_REG_0_CLK_EN);
  31                 break;
  32
  33         case PHY_INTERFACE_MODE_RMII:
  34                 /* Set RMII mode */
  35                 out_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_INVERT_RMII_CLK |
  36                                          GXBB_ETH_REG_0_CLK_EN);
  37
  38                 /* Use GXL RMII Internal PHY */
  39                 if (IS_ENABLED(CONFIG_MESON_GXL) &&
  40                     (flags & MESON_GXL_USE_INTERNAL_RMII_PHY)) {
  41                         writel(0x10110181, GXBB_ETH_REG_2);
  42                         writel(0xe40908ff, GXBB_ETH_REG_3);
  43                 }
  44
  45                 break;
  46
  47         default:
  48                 printf("Invalid Ethernet interface mode\n");
  49                 return;
  50         }
  51
  52         /* Enable power and clock gate */
  53         setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
  54         clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
  55 }