1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
4 * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
8 #include <asm/arch/boot.h>
9 #include <asm/arch/eth.h>
10 #include <asm/arch/gx.h>
11 #include <asm/arch/mem.h>
13 #include <asm/armv8/mmu.h>
14 #include <linux/sizes.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 int meson_get_boot_device(void)
21 return readl(GX_AO_SEC_GP_CFG0) & GX_AO_BOOT_DEVICE;
24 /* Configure the reserved memory zones exported by the secure registers
25 * into EFI and DTB reserved memory entries.
27 void meson_init_reserved_memory(void *fdt)
29 u64 bl31_size, bl31_start;
30 u64 bl32_size, bl32_start;
34 * Get ARM Trusted Firmware reserved memory zones in :
35 * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
36 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
37 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
39 reg = readl(GX_AO_SEC_GP_CFG3);
41 bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK)
42 >> GX_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
43 bl32_size = (reg & GX_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
45 bl31_start = readl(GX_AO_SEC_GP_CFG5);
46 bl32_start = readl(GX_AO_SEC_GP_CFG4);
49 * Early Meson GX Firmware revisions did not provide the reserved
50 * memory zones in the registers, keep fixed memory zone handling.
52 if (IS_ENABLED(CONFIG_MESON_GX) &&
53 !reg && !bl31_start && !bl32_start) {
54 bl31_start = 0x10000000;
58 /* Add first 16MiB reserved zone */
59 meson_board_add_reserved_memory(fdt, 0, GX_FIRMWARE_MEM_SIZE);
61 /* Add BL31 reserved zone */
62 if (bl31_start && bl31_size)
63 meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
65 /* Add BL32 reserved zone */
66 if (bl32_start && bl32_size)
67 meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
70 phys_size_t get_effective_memsize(void)
72 /* Size is reported in MiB, convert it in bytes */
73 return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK)
74 >> GX_AO_MEM_SIZE_SHIFT) * SZ_1M;
77 static struct mm_region gx_mem_map[] = {
82 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
88 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
90 PTE_BLOCK_PXN | PTE_BLOCK_UXN
97 struct mm_region *mem_map = gx_mem_map;
99 /* Configure the Ethernet MAC with the requested interface mode
100 * with some optional flags.
102 void meson_eth_init(phy_interface_t mode, unsigned int flags)
105 case PHY_INTERFACE_MODE_RGMII:
106 case PHY_INTERFACE_MODE_RGMII_ID:
107 case PHY_INTERFACE_MODE_RGMII_RXID:
108 case PHY_INTERFACE_MODE_RGMII_TXID:
110 setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
111 GX_ETH_REG_0_TX_PHASE(1) |
112 GX_ETH_REG_0_TX_RATIO(4) |
113 GX_ETH_REG_0_PHY_CLK_EN |
114 GX_ETH_REG_0_CLK_EN);
117 case PHY_INTERFACE_MODE_RMII:
119 out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
120 GX_ETH_REG_0_CLK_EN);
122 /* Use GXL RMII Internal PHY */
123 if (IS_ENABLED(CONFIG_MESON_GXL) &&
124 (flags & MESON_USE_INTERNAL_RMII_PHY)) {
125 writel(0x10110181, GX_ETH_REG_2);
126 writel(0xe40908ff, GX_ETH_REG_3);
132 printf("Invalid Ethernet interface mode\n");
136 /* Enable power gate */
137 clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);