arch/arm/mach-meson/board-gx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
   4  * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
   5  */
   6
   7 #include <common.h>
   8 #include <init.h>
   9 #include <asm/arch/boot.h>
  10 #include <asm/arch/eth.h>
  11 #include <asm/arch/gx.h>
  12 #include <asm/arch/mem.h>
  13 #include <asm/arch/meson-vpu.h>
  14 #include <asm/io.h>
  15 #include <asm/armv8/mmu.h>
  16 #include <linux/sizes.h>
  17 #include <phy.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 int meson_get_boot_device(void)
  22 {
  23         return readl(GX_AO_SEC_GP_CFG0) & GX_AO_BOOT_DEVICE;
  24 }
  25
  26 /* Configure the reserved memory zones exported by the secure registers
  27  * into EFI and DTB reserved memory entries.
  28  */
  29 void meson_init_reserved_memory(void *fdt)
  30 {
  31         u64 bl31_size, bl31_start;
  32         u64 bl32_size, bl32_start;
  33         u32 reg;
  34
  35         /*
  36          * Get ARM Trusted Firmware reserved memory zones in :
  37          * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
  38          * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
  39          * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
  40          */
  41         reg = readl(GX_AO_SEC_GP_CFG3);
  42
  43         bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK)
  44                         >> GX_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
  45         bl32_size = (reg & GX_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
  46
  47         bl31_start = readl(GX_AO_SEC_GP_CFG5);
  48         bl32_start = readl(GX_AO_SEC_GP_CFG4);
  49
  50         /*
  51          * Early Meson GX Firmware revisions did not provide the reserved
  52          * memory zones in the registers, keep fixed memory zone handling.
  53          */
  54         if (IS_ENABLED(CONFIG_MESON_GX) &&
  55             !reg && !bl31_start && !bl32_start) {
  56                 bl31_start = 0x10000000;
  57                 bl31_size = 0x200000;
  58         }
  59
  60         /* Add first 16MiB reserved zone */
  61         meson_board_add_reserved_memory(fdt, 0, GX_FIRMWARE_MEM_SIZE);
  62
  63         /* Add BL31 reserved zone */
  64         if (bl31_start && bl31_size)
  65                 meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
  66
  67         /* Add BL32 reserved zone */
  68         if (bl32_start && bl32_size)
  69                 meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
  70
  71 #if defined(CONFIG_VIDEO_MESON)
  72         meson_vpu_rsv_fb(fdt);
  73 #endif
  74 }
  75
  76 phys_size_t get_effective_memsize(void)
  77 {
  78         /* Size is reported in MiB, convert it in bytes */
  79         return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK)
  80                         >> GX_AO_MEM_SIZE_SHIFT) * SZ_1M;
  81 }
  82
  83 static struct mm_region gx_mem_map[] = {
  84         {
  85                 .virt = 0x0UL,
  86                 .phys = 0x0UL,
  87                 .size = 0xc0000000UL,
  88                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  89                          PTE_BLOCK_INNER_SHARE
  90         }, {
  91                 .virt = 0xc0000000UL,
  92                 .phys = 0xc0000000UL,
  93                 .size = 0x30000000UL,
  94                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  95                          PTE_BLOCK_NON_SHARE |
  96                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  97         }, {
  98                 /* List terminator */
  99                 0,
 100         }
 101 };
 102
 103 struct mm_region *mem_map = gx_mem_map;
 104
 105 /* Configure the Ethernet MAC with the requested interface mode
 106  * with some optional flags.
 107  */
 108 void meson_eth_init(phy_interface_t mode, unsigned int flags)
 109 {
 110         switch (mode) {
 111         case PHY_INTERFACE_MODE_RGMII:
 112         case PHY_INTERFACE_MODE_RGMII_ID:
 113         case PHY_INTERFACE_MODE_RGMII_RXID:
 114         case PHY_INTERFACE_MODE_RGMII_TXID:
 115                 /* Set RGMII mode */
 116                 setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
 117                              GX_ETH_REG_0_TX_PHASE(1) |
 118                              GX_ETH_REG_0_TX_RATIO(4) |
 119                              GX_ETH_REG_0_PHY_CLK_EN |
 120                              GX_ETH_REG_0_CLK_EN);
 121
 122                 /* Reset to external PHY */
 123                 if(!IS_ENABLED(CONFIG_MESON_GXBB))
 124                         writel(0x2009087f, GX_ETH_REG_3);
 125
 126                 break;
 127
 128         case PHY_INTERFACE_MODE_RMII:
 129                 /* Set RMII mode */
 130                 out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
 131                                          GX_ETH_REG_0_CLK_EN);
 132
 133                 /* Use GXL RMII Internal PHY (also on GXM) */
 134                 if (!IS_ENABLED(CONFIG_MESON_GXBB)) {
 135                         if ((flags & MESON_USE_INTERNAL_RMII_PHY)) {
 136                                 writel(0x10110181, GX_ETH_REG_2);
 137                                 writel(0xe40908ff, GX_ETH_REG_3);
 138                         } else
 139                                 writel(0x2009087f, GX_ETH_REG_3);
 140                 }
 141
 142                 break;
 143
 144         default:
 145                 printf("Invalid Ethernet interface mode\n");
 146                 return;
 147         }
 148
 149         /* Enable power gate */
 150         clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
 151 }