1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 MediaTek Inc.
4 * Copyright (C) 2019 BayLibre, SAS
5 * Author: Fabien Parent <fparent@baylibre.com>
14 #include <asm/arch/misc.h>
15 #include <asm/armv8/mmu.h>
16 #include <asm/cache.h>
17 #include <asm/sections.h>
18 #include <dm/uclass.h>
19 #include <dt-bindings/clock/mt8516-clk.h>
21 DECLARE_GLOBAL_DATA_PTR;
27 ret = fdtdec_setup_memory_banksize();
31 return fdtdec_setup_mem_size_base();
34 int dram_init_banksize(void)
36 gd->bd->bi_dram[0].start = gd->ram_base;
37 gd->bd->bi_dram[0].size = gd->ram_size;
42 int mtk_pll_early_init(void)
44 unsigned long pll_rates[] = {
45 [CLK_APMIXED_ARMPLL] = 1300000000,
46 [CLK_APMIXED_MAINPLL] = 1501000000,
47 [CLK_APMIXED_UNIVPLL] = 1248000000,
48 [CLK_APMIXED_MMPLL] = 380000000,
53 ret = uclass_get_device_by_driver(UCLASS_CLK,
54 DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
58 /* configure default rate then enable apmixedsys */
59 for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
60 struct clk clk = { .id = i, .dev = dev };
62 ret = clk_set_rate(&clk, pll_rates[i]);
66 ret = clk_enable(&clk);
74 int mtk_soc_early_init(void)
78 /* initialize early clocks */
79 ret = mtk_pll_early_init();
86 void reset_cpu(ulong addr)
91 int print_cpuinfo(void)
93 printf("CPU: MediaTek MT8516\n");
97 static struct mm_region mt8516_mem_map[] = {
100 .virt = 0x40000000UL,
101 .phys = 0x40000000UL,
102 .size = 0x20000000UL,
103 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
105 .virt = 0x00000000UL,
106 .phys = 0x00000000UL,
107 .size = 0x20000000UL,
108 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
109 PTE_BLOCK_NON_SHARE |
110 PTE_BLOCK_PXN | PTE_BLOCK_UXN
115 struct mm_region *mem_map = mt8516_mem_map;