arch/arm/mach-mediatek/mt8516/init.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 MediaTek Inc.
   4  * Copyright (C) 2019 BayLibre, SAS
   5  * Author: Fabien Parent <fparent@baylibre.com>
   6  */
   7
   8 #include <clk.h>
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <fdtdec.h>
  12 #include <ram.h>
  13 #include <asm/arch/misc.h>
  14 #include <asm/armv8/mmu.h>
  15 #include <asm/sections.h>
  16 #include <dm/uclass.h>
  17 #include <linux/io.h>
  18 #include <dt-bindings/clock/mt8516-clk.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 #define WDOG_SWRST              0x10007014
  23 #define WDOG_SWRST_KEY          0x1209
  24
  25 int dram_init(void)
  26 {
  27         int ret;
  28
  29         ret = fdtdec_setup_memory_banksize();
  30         if (ret)
  31                 return ret;
  32
  33         return fdtdec_setup_mem_size_base();
  34 }
  35
  36 int dram_init_banksize(void)
  37 {
  38         gd->bd->bi_dram[0].start = gd->ram_base;
  39         gd->bd->bi_dram[0].size = gd->ram_size;
  40
  41         return 0;
  42 }
  43
  44 int mtk_pll_early_init(void)
  45 {
  46         unsigned long pll_rates[] = {
  47                 [CLK_APMIXED_ARMPLL] =   1300000000,
  48                 [CLK_APMIXED_MAINPLL] =  1501000000,
  49                 [CLK_APMIXED_UNIVPLL] =  1248000000,
  50                 [CLK_APMIXED_MMPLL] =     380000000,
  51         };
  52         struct udevice *dev;
  53         int ret, i;
  54
  55         ret = uclass_get_device_by_driver(UCLASS_CLK,
  56                         DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
  57         if (ret)
  58                 return ret;
  59
  60         /* configure default rate then enable apmixedsys */
  61         for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
  62                 struct clk clk = { .id = i, .dev = dev };
  63
  64                 ret = clk_set_rate(&clk, pll_rates[i]);
  65                 if (ret)
  66                         return ret;
  67
  68                 ret = clk_enable(&clk);
  69                 if (ret)
  70                         return ret;
  71         }
  72
  73         return 0;
  74 }
  75
  76 int mtk_soc_early_init(void)
  77 {
  78         int ret;
  79
  80         /* initialize early clocks */
  81         ret = mtk_pll_early_init();
  82         if (ret)
  83                 return ret;
  84
  85         return 0;
  86 }
  87
  88 void reset_cpu(ulong addr)
  89 {
  90         while (1) {
  91                 writel(WDOG_SWRST_KEY, WDOG_SWRST);
  92                 mdelay(5);
  93         }
  94 }
  95
  96 int print_cpuinfo(void)
  97 {
  98         printf("CPU:   MediaTek MT8516\n");
  99         return 0;
 100 }
 101
 102 static struct mm_region mt8516_mem_map[] = {
 103         {
 104                 /* DDR */
 105                 .virt = 0x40000000UL,
 106                 .phys = 0x40000000UL,
 107                 .size = 0x20000000UL,
 108                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
 109         }, {
 110                 .virt = 0x00000000UL,
 111                 .phys = 0x00000000UL,
 112                 .size = 0x20000000UL,
 113                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 114                          PTE_BLOCK_NON_SHARE |
 115                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 116         }, {
 117                 0,
 118         }
 119 };
 120 struct mm_region *mem_map = mt8516_mem_map;