1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2018 MediaTek Inc.
6 #include <linux/linkage.h>
8 #define WAIT_CODE_SRAM_BASE 0x0010ff00
10 #define SLAVE_JUMP_REG 0x10202034
11 #define SLAVE1_MAGIC_REG 0x10202038
12 #define SLAVE1_MAGIC_NUM 0x534c4131
14 #define GIC_CPU_BASE 0x10320000
18 #ifndef CONFIG_SPL_BUILD
19 /* Return to U-Boot via saved link register */
24 * set CNTFRQ = 20Mhz, set CNTVOFF = 0
28 mcr p15, 0, r0, c14, c0, 0
31 mrc p15, 0, r0, c1, c0, 1
33 mcr p15, 0, r0, c1, c0, 1
35 /* if MP core, handle secondary cores */
36 mrc p15, 0, r0, c0, c0, 5
37 ands r1, r0, #0x40000000
39 /* read slave CPU number */
41 beq go @ Go if core0 on primary core tile
49 /* enable GIC as cores will be waken up by IPI */
60 /* copy wait code into SRAM */
61 ldr r0, =slave_cpu_wait
62 ldm r0, {r1 - r8} @ slave_cpu_wait has eight insns
63 ldr r0, =WAIT_CODE_SRAM_BASE
66 /* pass args to slave_cpu_wait */
67 ldr r0, =SLAVE1_MAGIC_REG
68 ldr r1, =SLAVE1_MAGIC_NUM
70 /* jump to wait code in SRAM */
71 ldr pc, =WAIT_CODE_SRAM_BASE
74 ENDPROC(lowlevel_init)
76 /* This function will be copied into SRAM */
82 movw r0, #:lower16:SLAVE_JUMP_REG
83 movt r0, #:upper16:SLAVE_JUMP_REG
86 ENDPROC(slave_cpu_wait)