2 * arch/arm/mach-ks8695/time.c
4 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
5 * Copyright (C) 2006 Simtec Electronics
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
29 #include <asm/mach/time.h>
30 #include <asm/system_misc.h>
32 #include <mach/regs-irq.h>
36 #define KS8695_TMR_OFFSET (0xF0000 + 0xE400)
37 #define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET)
38 #define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET)
43 #define KS8695_TMCON (0x00) /* Timer Control Register */
44 #define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */
45 #define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */
46 #define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */
47 #define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */
49 /* Timer Control Register */
50 #define TMCON_T1EN (1 << 1) /* Timer 1 Enable */
51 #define TMCON_T0EN (1 << 0) /* Timer 0 Enable */
53 /* Timer0 Timeout Counter Register */
54 #define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */
57 * Returns number of ms since last clock interrupt. Note that interrupts
58 * will have been disabled by do_gettimeoffset()
60 static unsigned long ks8695_gettimeoffset (void)
62 unsigned long elapsed, tick2, intpending;
65 * Get the current number of ticks. Note that there is a race
66 * condition between us reading the timer and checking for an
67 * interrupt. We solve this by ensuring that the counter has not
68 * reloaded between our two reads.
70 elapsed = readl_relaxed(KS8695_TMR_VA + KS8695_T1TC) + readl_relaxed(KS8695_TMR_VA + KS8695_T1PD);
73 intpending = readl_relaxed(KS8695_IRQ_VA + KS8695_INTST) & (1 << KS8695_IRQ_TIMER1);
74 elapsed = readl_relaxed(KS8695_TMR_VA + KS8695_T1TC) + readl_relaxed(KS8695_TMR_VA + KS8695_T1PD);
75 } while (elapsed > tick2);
77 /* Convert to number of ticks expired (not remaining) */
78 elapsed = (CLOCK_TICK_RATE / HZ) - elapsed;
80 /* Is interrupt pending? If so, then timer has been reloaded already. */
82 elapsed += (CLOCK_TICK_RATE / HZ);
84 /* Convert ticks to usecs */
85 return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH;
89 * IRQ handler for the timer.
91 static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id)
97 static struct irqaction ks8695_timer_irq = {
98 .name = "ks8695_tick",
99 .flags = IRQF_DISABLED | IRQF_TIMER,
100 .handler = ks8695_timer_interrupt,
103 static void ks8695_timer_setup(void)
105 unsigned long tmout = CLOCK_TICK_RATE / HZ;
109 tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
110 writel_relaxed(tmcon & ~TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
112 writel_relaxed(tmout / 2, KS8695_TMR_VA + KS8695_T1TC);
113 writel_relaxed(tmout / 2, KS8695_TMR_VA + KS8695_T1PD);
115 /* re-enable timer1 */
116 writel_relaxed(tmcon | TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
119 static void __init ks8695_timer_init (void)
121 ks8695_timer_setup();
123 /* Enable timer interrupts */
124 setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq);
127 struct sys_timer ks8695_timer = {
128 .init = ks8695_timer_init,
129 .offset = ks8695_gettimeoffset,
132 void ks8695_restart(char mode, const char *cmd)
140 reg = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
141 writel_relaxed(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
143 /* enable watchdog mode */
144 writel_relaxed((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
146 /* re-enable timer0 */
147 writel_relaxed(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);