1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Lei Wen <leiwen@marvell.com>
9 * This file should be included in board config header file.
11 * It supports common definitions for Kirkwood platform
17 #if defined (CONFIG_KW88F6281)
18 #include <asm/arch/kw88f6281.h>
19 #elif defined (CONFIG_KW88F6192)
20 #include <asm/arch/kw88f6192.h>
22 #error "SOC Name not defined"
23 #endif /* CONFIG_KW88F6281 */
25 #include <asm/arch/soc.h>
26 #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
27 #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
28 #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
30 /* Kirkwood has 2k of Security SRAM, use it for SP */
31 #define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
33 #define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE
34 #define MV_UART_CONSOLE_BASE KW_UART0_BASE
35 #define MV_SATA_BASE KW_SATA_BASE
36 #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
37 #define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
42 #ifdef CONFIG_CMD_NAND
43 #define CONFIG_NAND_KIRKWOOD
44 #define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
45 #define NAND_ALLOW_ERASE_ALL 1
49 * Ethernet Driver configuration
52 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
53 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
54 #endif /* CONFIG_CMD_NET */
57 * IDE Support on SATA ports
61 /* Data, registers and alternate blocks are at the same offset */
62 /* Each 8-bit ATA register is aligned to a 4-bytes address */
63 /* Controller supports 48-bits LBA addressing */
65 /* CONFIG_IDE requires some #defines for ATA registers */
66 /* ATA registers base is at SATA controller base */
67 #endif /* CONFIG_IDE */
69 /* Use common timer */
70 #define CONFIG_SYS_TIMER_COUNTS_DOWN
71 #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
72 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK
74 #endif /* _KW_CONFIG_H */