1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * (C) Copyright 2012-2014
6 * Texas Instruments Incorporated, <www.ti.com>
9 #ifndef __ASM_ARCH_HARDWARE_K2L_H
10 #define __ASM_ARCH_HARDWARE_K2L_H
12 #define KS2_ARM_PLL_EN BIT(13)
15 #define KS2_PASS_BASE 0x26000000
17 /* Power and Sleep Controller (PSC) Domains */
18 #define KS2_LPSC_MOD 0
19 #define KS2_LPSC_DFE_IQN_SYS 1
20 #define KS2_LPSC_USB 2
21 #define KS2_LPSC_EMIF25_SPI 3
22 #define KS2_LPSC_TSIP 4
23 #define KS2_LPSC_DEBUGSS_TRC 5
24 #define KS2_LPSC_TETB_TRC 6
25 #define KS2_LPSC_PKTPROC 7
26 #define KS2_LPSC_PA KS2_LPSC_PKTPROC
27 #define KS2_LPSC_SGMII 8
28 #define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
29 #define KS2_LPSC_CRYPTO 9
30 #define KS2_LPSC_PCIE0 10
31 #define KS2_LPSC_PCIE1 11
32 #define KS2_LPSC_JESD_MISC 12
33 #define KS2_LPSC_CHIP_SRSS 13
34 #define KS2_LPSC_MSMC 14
35 #define KS2_LPSC_GEM_1 16
36 #define KS2_LPSC_GEM_2 17
37 #define KS2_LPSC_GEM_3 18
38 #define KS2_LPSC_EMIF4F_DDR3 23
39 #define KS2_LPSC_TAC 25
40 #define KS2_LPSC_RAC 26
41 #define KS2_LPSC_DDUC4X_CFR2X_BB 27
42 #define KS2_LPSC_FFTC_A 28
43 #define KS2_LPSC_OSR 34
44 #define KS2_LPSC_TCP3D_0 35
45 #define KS2_LPSC_TCP3D_1 37
46 #define KS2_LPSC_VCP2X4_A 39
47 #define KS2_LPSC_VCP2X4_B 40
48 #define KS2_LPSC_VCP2X4_C 41
49 #define KS2_LPSC_VCP2X4_D 42
50 #define KS2_LPSC_BCP 47
51 #define KS2_LPSC_DPD4X 48
52 #define KS2_LPSC_FFTC_B 49
53 #define KS2_LPSC_IQN_AIL 50
55 /* Chip Interrupt Controller */
56 #define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
57 #define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
60 #define KS2_OSR_DATA_BASE 0x70000000 /* OSR data base */
61 #define KS2_OSR_CFG_BASE 0x02348c00 /* OSR config base */
62 #define KS2_OSR_ECC_VEC 0x08 /* ECC Vector reg */
63 #define KS2_OSR_ECC_CTRL 0x14 /* ECC control reg */
65 /* OSR ECC Vector register */
66 #define KS2_OSR_ECC_VEC_TRIG_RD BIT(15) /* trigger a read op */
67 #define KS2_OSR_ECC_VEC_RD_DONE BIT(24) /* read complete */
69 #define KS2_OSR_ECC_VEC_RAM_ID_SH 0 /* RAM ID shift */
70 #define KS2_OSR_ECC_VEC_RD_ADDR_SH 16 /* read address shift */
72 /* OSR ECC control register */
73 #define KS2_OSR_ECC_CTRL_EN BIT(0) /* ECC enable bit */
74 #define KS2_OSR_ECC_CTRL_CHK BIT(1) /* ECC check bit */
75 #define KS2_OSR_ECC_CTRL_RMW BIT(2) /* ECC check bit */
77 /* Number of OSR RAM banks */
78 #define KS2_OSR_NUM_RAM_BANKS 4
81 #define KS2_OSR_SIZE 0x100000
84 #define KS2_SGMII_SERDES2_BASE 0x02320000
85 #define KS2_LANES_PER_SGMII_SERDES 2
87 /* Number of DSP cores */
88 #define KS2_NUM_DSPS 4
91 #define KS2_NETCP_PDMA_CTRL_BASE 0x26186000
92 #define KS2_NETCP_PDMA_TX_BASE 0x26187000
93 #define KS2_NETCP_PDMA_TX_CH_NUM 21
94 #define KS2_NETCP_PDMA_RX_BASE 0x26188000
95 #define KS2_NETCP_PDMA_RX_CH_NUM 91
96 #define KS2_NETCP_PDMA_SCHED_BASE 0x26186100
97 #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x26189000
98 #define KS2_NETCP_PDMA_RX_FLOW_NUM 96
99 #define KS2_NETCP_PDMA_TX_SND_QUEUE 896
102 #define KS2_NETCP_BASE 0x26000000
105 static inline int ddr3_get_size(void)
111 #endif /* __ASM_ARCH_HARDWARE_K2L_H */