arch/arm/mach-keystone/include/mach/clock.h

   1 /*
   2  * keystone2: common clock header file
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __ASM_ARCH_CLOCK_H
  11 #define __ASM_ARCH_CLOCK_H
  12
  13 #ifndef __ASSEMBLY__
  14
  15 #ifdef CONFIG_SOC_K2HK
  16 #include <asm/arch/clock-k2hk.h>
  17 #endif
  18
  19 #ifdef CONFIG_SOC_K2E
  20 #include <asm/arch/clock-k2e.h>
  21 #endif
  22
  23 #ifdef CONFIG_SOC_K2L
  24 #include <asm/arch/clock-k2l.h>
  25 #endif
  26
  27 #ifdef CONFIG_SOC_K2G
  28 #include <asm/arch/clock-k2g.h>
  29 #endif
  30
  31 #define CORE_PLL MAIN_PLL
  32 #define DDR3_PLL DDR3A_PLL
  33 #define NSS_PLL PASS_PLL
  34
  35 #define CLK_LIST(CLK)\
  36         CLK(0, core_pll_clk)\
  37         CLK(1, pass_pll_clk)\
  38         CLK(2, tetris_pll_clk)\
  39         CLK(3, ddr3a_pll_clk)\
  40         CLK(4, ddr3b_pll_clk)\
  41         CLK(5, sys_clk0_clk)\
  42         CLK(6, sys_clk0_1_clk)\
  43         CLK(7, sys_clk0_2_clk)\
  44         CLK(8, sys_clk0_3_clk)\
  45         CLK(9, sys_clk0_4_clk)\
  46         CLK(10, sys_clk0_6_clk)\
  47         CLK(11, sys_clk0_8_clk)\
  48         CLK(12, sys_clk0_12_clk)\
  49         CLK(13, sys_clk0_24_clk)\
  50         CLK(14, sys_clk1_clk)\
  51         CLK(15, sys_clk1_3_clk)\
  52         CLK(16, sys_clk1_4_clk)\
  53         CLK(17, sys_clk1_6_clk)\
  54         CLK(18, sys_clk1_12_clk)\
  55         CLK(19, sys_clk2_clk)\
  56         CLK(20, sys_clk3_clk)\
  57         CLK(21, uart_pll_clk)
  58
  59 #include <asm/types.h>
  60
  61 #define GENERATE_ENUM(NUM, ENUM) ENUM = NUM,
  62 #define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n"
  63 #define CLOCK_INDEXES_LIST      CLK_LIST(GENERATE_INDX_STR)
  64
  65 enum {
  66         SPD800,
  67         SPD850,
  68         SPD1000,
  69         SPD1200,
  70         SPD1250,
  71         SPD1350,
  72         SPD1400,
  73         SPD1500,
  74         NUM_SPDS,
  75 };
  76
  77 /* PLL identifiers */
  78 enum {
  79         MAIN_PLL,
  80         TETRIS_PLL,
  81         PASS_PLL,
  82         DDR3A_PLL,
  83         DDR3B_PLL,
  84         UART_PLL,
  85         MAX_PLL_COUNT,
  86 };
  87
  88 enum ext_clk_e {
  89         sys_clk,
  90         alt_core_clk,
  91         pa_clk,
  92         tetris_clk,
  93         ddr3a_clk,
  94         ddr3b_clk,
  95         uart_clk,
  96         ext_clk_count /* number of external clocks */
  97 };
  98
  99 enum clk_e {
 100         CLK_LIST(GENERATE_ENUM)
 101 };
 102
 103 struct keystone_pll_regs {
 104         u32 reg0;
 105         u32 reg1;
 106 };
 107
 108 /* PLL configuration data */
 109 struct pll_init_data {
 110         int pll;
 111         int pll_m;              /* PLL Multiplier */
 112         int pll_d;              /* PLL divider */
 113         int pll_od;             /* PLL output divider */
 114 };
 115
 116 extern unsigned int external_clk[ext_clk_count];
 117 extern const struct keystone_pll_regs keystone_pll_regs[];
 118 extern s16 divn_val[];
 119 extern int speeds[];
 120
 121 void init_plls(void);
 122 void init_pll(const struct pll_init_data *data);
 123 struct pll_init_data *get_pll_init_data(int pll);
 124 unsigned long clk_get_rate(unsigned int clk);
 125 unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
 126 int clk_set_rate(unsigned int clk, unsigned long hz);
 127 int get_max_dev_speed(void);
 128 int get_max_arm_speed(void);
 129 void pll_pa_clk_sel(void);
 130
 131 #endif
 132 #endif