arch/arm/mach-k3/j721s2_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * J721E: SoC specific initialization
   4  *
   5  * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
   6  *      David Huang <d-huang@ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <init.h>
  11 #include <spl.h>
  12 #include <asm/io.h>
  13 #include <asm/armv7_mpu.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sysfw-loader.h>
  16 #include "common.h"
  17 #include <asm/arch/sys_proto.h>
  18 #include <linux/soc/ti/ti_sci_protocol.h>
  19 #include <dm.h>
  20 #include <dm/uclass-internal.h>
  21 #include <dm/pinctrl.h>
  22 #include <mmc.h>
  23 #include <remoteproc.h>
  24
  25 static void ctrl_mmr_unlock(void)
  26 {
  27         /* Unlock all WKUP_CTRL_MMR0 module registers */
  28         mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  29         mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  30         mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  31         mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  32         mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
  33         mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  34         mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  35
  36         /* Unlock all MCU_CTRL_MMR0 module registers */
  37         mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  38         mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  39         mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  40         mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
  41         mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
  42
  43         /* Unlock all CTRL_MMR0 module registers */
  44         mmr_unlock(CTRL_MMR0_BASE, 0);
  45         mmr_unlock(CTRL_MMR0_BASE, 1);
  46         mmr_unlock(CTRL_MMR0_BASE, 2);
  47         mmr_unlock(CTRL_MMR0_BASE, 3);
  48         mmr_unlock(CTRL_MMR0_BASE, 5);
  49         mmr_unlock(CTRL_MMR0_BASE, 7);
  50 }
  51
  52 void k3_mmc_stop_clock(void)
  53 {
  54         if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
  55                 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
  56                         struct mmc *mmc = find_mmc_device(0);
  57
  58                         if (!mmc)
  59                                 return;
  60
  61                         mmc->saved_clock = mmc->clock;
  62                         mmc_set_clock(mmc, 0, true);
  63                 }
  64         }
  65 }
  66
  67 void k3_mmc_restart_clock(void)
  68 {
  69         if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
  70                 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
  71                         struct mmc *mmc = find_mmc_device(0);
  72
  73                         if (!mmc)
  74                                 return;
  75
  76                         mmc_set_clock(mmc, mmc->saved_clock, false);
  77                 }
  78         }
  79 }
  80
  81 /*
  82  * This uninitialized global variable would normal end up in the .bss section,
  83  * but the .bss is cleared between writing and reading this variable, so move
  84  * it to the .data section.
  85  */
  86 u32 bootindex __attribute__((section(".data")));
  87 static struct rom_extended_boot_data bootdata __section(".data");
  88
  89 static void store_boot_info_from_rom(void)
  90 {
  91         bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
  92         memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
  93                sizeof(struct rom_extended_boot_data));
  94 }
  95
  96 void k3_spl_init(void)
  97 {
  98         struct udevice *dev;
  99         int ret;
 100         /*
 101          * Cannot delay this further as there is a chance that
 102          * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
 103          */
 104         store_boot_info_from_rom();
 105
 106         /* Make all control module registers accessible */
 107         ctrl_mmr_unlock();
 108
 109         if (IS_ENABLED(CONFIG_CPU_V7R)) {
 110                 disable_linefill_optimization();
 111                 setup_k3_mpu_regions();
 112         }
 113
 114         /* Init DM early */
 115         spl_early_init();
 116
 117         /* Prepare console output */
 118         preloader_console_init();
 119
 120         if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
 121                 /*
 122                  * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
 123                  * regardless of the result of pinctrl. Do this without probing the
 124                  * device, but instead by searching the device that would request the
 125                  * given sequence number if probed. The UART will be used by the system
 126                  * firmware (SYSFW) image for various purposes and SYSFW depends on us
 127                  * to initialize its pin settings.
 128                  */
 129                 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
 130                 if (!ret)
 131                         pinctrl_select_state(dev, "default");
 132
 133                 /*
 134                  * Load, start up, and configure system controller firmware. Provide
 135                  * the U-Boot console init function to the SYSFW post-PM configuration
 136                  * callback hook, effectively switching on (or over) the console
 137                  * output.
 138                  */
 139                 k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
 140                                 k3_mmc_stop_clock, k3_mmc_restart_clock);
 141
 142                 if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
 143                         /*
 144                          * Force probe of clk_k3 driver here to ensure basic default clock
 145                          * configuration is always done for enabling PM services.
 146                          */
 147                         ret = uclass_get_device_by_driver(UCLASS_CLK,
 148                                                           DM_DRIVER_GET(ti_clk),
 149                                                           &dev);
 150                         if (ret)
 151                                 panic("Failed to initialize clk-k3!\n");
 152                 }
 153         }
 154
 155         /* Output System Firmware version info */
 156         k3_sysfw_print_ver();
 157 }
 158
 159 bool check_rom_loaded_sysfw(void)
 160 {
 161         return is_rom_loaded_sysfw(&bootdata);
 162 }
 163
 164 void k3_mem_init(void)
 165 {
 166         struct udevice *dev;
 167         int ret;
 168
 169         if (IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM)) {
 170                 ret = uclass_get_device_by_name(UCLASS_MISC, "msmc", &dev);
 171                 if (ret)
 172                         panic("Probe of msmc failed: %d\n", ret);
 173
 174                 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 175                 if (ret)
 176                         panic("DRAM 0 init failed: %d\n", ret);
 177
 178                 ret = uclass_next_device_err(&dev);
 179                 if (ret)
 180                         panic("DRAM 1 init failed: %d\n", ret);
 181         }
 182         spl_enable_dcache();
 183 }
 184
 185 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
 186 {
 187         switch (boot_device) {
 188         case BOOT_DEVICE_MMC1:
 189                 return MMCSD_MODE_EMMCBOOT;
 190         case BOOT_DEVICE_MMC2:
 191                 return MMCSD_MODE_FS;
 192         default:
 193                 return MMCSD_MODE_RAW;
 194         }
 195 }
 196
 197 static u32 __get_backup_bootmedia(u32 main_devstat)
 198 {
 199         u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
 200                         MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
 201
 202         switch (bkup_boot) {
 203         case BACKUP_BOOT_DEVICE_USB:
 204                 return BOOT_DEVICE_DFU;
 205         case BACKUP_BOOT_DEVICE_UART:
 206                 return BOOT_DEVICE_UART;
 207         case BACKUP_BOOT_DEVICE_ETHERNET:
 208                 return BOOT_DEVICE_ETHERNET;
 209         case BACKUP_BOOT_DEVICE_MMC2:
 210         {
 211                 u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
 212                             MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
 213                 if (port == 0x0)
 214                         return BOOT_DEVICE_MMC1;
 215                 return BOOT_DEVICE_MMC2;
 216         }
 217         case BACKUP_BOOT_DEVICE_SPI:
 218                 return BOOT_DEVICE_SPI;
 219         case BACKUP_BOOT_DEVICE_I2C:
 220                 return BOOT_DEVICE_I2C;
 221         }
 222
 223         return BOOT_DEVICE_RAM;
 224 }
 225
 226 static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
 227 {
 228         u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
 229                         WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
 230
 231         bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
 232                         BOOT_MODE_B_SHIFT;
 233
 234         if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI ||
 235             bootmode == BOOT_DEVICE_XSPI)
 236                 bootmode = BOOT_DEVICE_SPI;
 237
 238         if (bootmode == BOOT_DEVICE_MMC2) {
 239                 u32 port = (main_devstat &
 240                             MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
 241                            MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
 242                 if (port == 0x0)
 243                         bootmode = BOOT_DEVICE_MMC1;
 244         }
 245
 246         return bootmode;
 247 }
 248
 249 u32 spl_boot_device(void)
 250 {
 251         u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
 252         u32 main_devstat;
 253
 254         if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
 255                 printf("ERROR: MCU only boot is not yet supported\n");
 256                 return BOOT_DEVICE_RAM;
 257         }
 258
 259         /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
 260         main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 261
 262         if (bootindex == K3_PRIMARY_BOOTMODE)
 263                 return __get_primary_bootmedia(main_devstat, wkup_devstat);
 264         else
 265                 return __get_backup_bootmedia(main_devstat);
 266 }
 267
 268 #define J721S2_DEV_MCU_RTI0                     295
 269 #define J721S2_DEV_MCU_RTI1                     296
 270 #define J721S2_DEV_MCU_ARMSS0_CPU0              284
 271 #define J721S2_DEV_MCU_ARMSS0_CPU1              285
 272
 273 void release_resources_for_core_shutdown(void)
 274 {
 275         if (IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)) {
 276                 struct ti_sci_handle *ti_sci;
 277                 struct ti_sci_dev_ops *dev_ops;
 278                 struct ti_sci_proc_ops *proc_ops;
 279                 int ret;
 280                 u32 i;
 281
 282                 const u32 put_device_ids[] = {
 283                         J721S2_DEV_MCU_RTI0,
 284                         J721S2_DEV_MCU_RTI1,
 285                 };
 286
 287                 ti_sci = get_ti_sci_handle();
 288                 dev_ops = &ti_sci->ops.dev_ops;
 289                 proc_ops = &ti_sci->ops.proc_ops;
 290
 291                 /* Iterate through list of devices to put (shutdown) */
 292                 for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
 293                         u32 id = put_device_ids[i];
 294
 295                         ret = dev_ops->put_device(ti_sci, id);
 296                         if (ret)
 297                                 panic("Failed to put device %u (%d)\n", id, ret);
 298                 }
 299
 300                 const u32 put_core_ids[] = {
 301                         J721S2_DEV_MCU_ARMSS0_CPU1,
 302                         J721S2_DEV_MCU_ARMSS0_CPU0,     /* Handle CPU0 after CPU1 */
 303                 };
 304
 305                 /* Iterate through list of cores to put (shutdown) */
 306                 for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
 307                         u32 id = put_core_ids[i];
 308
 309                         /*
 310                          * Queue up the core shutdown request. Note that this call
 311                          * needs to be followed up by an actual invocation of an WFE
 312                          * or WFI CPU instruction.
 313                          */
 314                         ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
 315                         if (ret)
 316                                 panic("Failed sending core %u shutdown message (%d)\n",
 317                                       id, ret);
 318                 }
 319         }
 320 }