arch/arm/mach-k3/j721s2/clk-data.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * J721S2 specific clock platform data
   4  *
   5  * This file is auto generated. Please do not hand edit and report any issues
   6  * to Dave Gerlach <d-gerlach@ti.com>.
   7  *
   8  * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
   9  */
  10
  11 #include <linux/clk-provider.h>
  12 #include "k3-clk.h"
  13
  14 static const char * const gluelogic_hfosc0_clkout_parents[] = {
  15         "osc_19_2_mhz",
  16         "osc_20_mhz",
  17         "osc_24_mhz",
  18         "osc_25_mhz",
  19         "osc_26_mhz",
  20         "osc_27_mhz",
  21 };
  22
  23 static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
  24         "board_0_mcu_ospi0_dqs_out",
  25         "fss_mcu_0_ospi_0_ospi_oclk_clk",
  26 };
  27
  28 static const char * const mcu_ospi1_iclk_sel_out0_parents[] = {
  29         "board_0_mcu_ospi1_dqs_out",
  30         "fss_mcu_0_ospi_1_ospi_oclk_clk",
  31 };
  32
  33 static const char * const wkup_fref_clksel_out0_parents[] = {
  34         "gluelogic_hfosc0_clkout",
  35         NULL,
  36 };
  37
  38 static const char * const main_pll_hfosc_sel_out1_parents[] = {
  39         "gluelogic_hfosc0_clkout",
  40         "board_0_hfosc1_clk_out",
  41 };
  42
  43 static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
  44         "wkup_fref_clksel_out0",
  45         "hsdiv1_16fft_mcu_0_hsdivout0_clk",
  46 };
  47
  48 static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
  49         "hsdiv4_16fft_mcu_1_hsdivout4_clk",
  50         "hsdiv4_16fft_mcu_2_hsdivout4_clk",
  51 };
  52
  53 static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
  54         "hsdiv4_16fft_mcu_1_hsdivout4_clk",
  55         "hsdiv4_16fft_mcu_2_hsdivout4_clk",
  56 };
  57
  58 static const char * const mcu_usart_clksel_out0_parents[] = {
  59         "hsdiv4_16fft_mcu_1_hsdivout3_clk",
  60         "postdiv3_16fft_main_1_hsdivout5_clk",
  61 };
  62
  63 static const char * const wkup_i2c_mcupll_bypass_out0_parents[] = {
  64         "hsdiv4_16fft_mcu_1_hsdivout3_clk",
  65         "gluelogic_hfosc0_clkout",
  66 };
  67
  68 static const char * const main_pll_hfosc_sel_out0_parents[] = {
  69         "gluelogic_hfosc0_clkout",
  70         "board_0_hfosc1_clk_out",
  71 };
  72
  73 static const char * const main_pll_hfosc_sel_out12_parents[] = {
  74         "gluelogic_hfosc0_clkout",
  75         "board_0_hfosc1_clk_out",
  76 };
  77
  78 static const char * const main_pll_hfosc_sel_out19_parents[] = {
  79         "gluelogic_hfosc0_clkout",
  80         "board_0_hfosc1_clk_out",
  81 };
  82
  83 static const char * const main_pll_hfosc_sel_out2_parents[] = {
  84         "gluelogic_hfosc0_clkout",
  85         "board_0_hfosc1_clk_out",
  86 };
  87
  88 static const char * const main_pll_hfosc_sel_out26_0_parents[] = {
  89         "gluelogic_hfosc0_clkout",
  90         "board_0_hfosc1_clk_out",
  91 };
  92
  93 static const char * const main_pll_hfosc_sel_out3_parents[] = {
  94         "gluelogic_hfosc0_clkout",
  95         "board_0_hfosc1_clk_out",
  96 };
  97
  98 static const char * const main_pll_hfosc_sel_out7_parents[] = {
  99         "gluelogic_hfosc0_clkout",
 100         "board_0_hfosc1_clk_out",
 101 };
 102
 103 static const char * const main_pll_hfosc_sel_out8_parents[] = {
 104         "gluelogic_hfosc0_clkout",
 105         "board_0_hfosc1_clk_out",
 106 };
 107
 108 static const char * const usb0_refclk_sel_out0_parents[] = {
 109         "gluelogic_hfosc0_clkout",
 110         "board_0_hfosc1_clk_out",
 111 };
 112
 113 static const char * const emmcsd1_lb_clksel_out0_parents[] = {
 114         "board_0_mmc1_clklb_out",
 115         "board_0_mmc1_clk_out",
 116 };
 117
 118 static const char * const mcu_clkout_mux_out0_parents[] = {
 119         "hsdiv4_16fft_mcu_2_hsdivout0_clk",
 120         "hsdiv4_16fft_mcu_2_hsdivout0_clk",
 121 };
 122
 123 static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
 124         "main_pll_hfosc_sel_out0",
 125         "hsdiv4_16fft_main_0_hsdivout0_clk",
 126 };
 127
 128 static const char * const dpi0_ext_clksel_out0_parents[] = {
 129         "hsdiv1_16fft_main_19_hsdivout0_clk",
 130         "board_0_vout0_extpclkin_out",
 131 };
 132
 133 static const char * const emmcsd_refclk_sel_out0_parents[] = {
 134         "hsdiv4_16fft_main_0_hsdivout2_clk",
 135         "hsdiv4_16fft_main_1_hsdivout2_clk",
 136         "hsdiv4_16fft_main_2_hsdivout2_clk",
 137         "hsdiv4_16fft_main_3_hsdivout2_clk",
 138 };
 139
 140 static const char * const emmcsd_refclk_sel_out1_parents[] = {
 141         "hsdiv4_16fft_main_0_hsdivout2_clk",
 142         "hsdiv4_16fft_main_1_hsdivout2_clk",
 143         "hsdiv4_16fft_main_2_hsdivout2_clk",
 144         "hsdiv4_16fft_main_3_hsdivout2_clk",
 145 };
 146
 147 static const char * const gtc_clk_mux_out0_parents[] = {
 148         "hsdiv4_16fft_main_3_hsdivout1_clk",
 149         "postdiv3_16fft_main_0_hsdivout6_clk",
 150         "board_0_mcu_cpts0_rft_clk_out",
 151         "board_0_cpts0_rft_clk_out",
 152         "board_0_mcu_ext_refclk0_out",
 153         "board_0_ext_refclk1_out",
 154         NULL,
 155         NULL,
 156         NULL,
 157         NULL,
 158         NULL,
 159         NULL,
 160         NULL,
 161         NULL,
 162         "hsdiv4_16fft_mcu_2_hsdivout1_clk",
 163         "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
 164 };
 165
 166 static const struct clk_data clk_list[] = {
 167         CLK_FIXED_RATE("osc_27_mhz", 27000000, 0),
 168         CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
 169         CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
 170         CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
 171         CLK_FIXED_RATE("osc_20_mhz", 20000000, 0),
 172         CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0),
 173         CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
 174         CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
 175         CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
 176         CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
 177         CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
 178         CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
 179         CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
 180         CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
 181         CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0),
 182         CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0),
 183         CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 2, 0x40f08034, 4, 1, 0),
 184         CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
 185         CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
 186         CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
 187         CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
 188         CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
 189         CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
 190         CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
 191         CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
 192         CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
 193         CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
 194         CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0),
 195         CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0),
 196         CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0),
 197         CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666),
 198         CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
 199         CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0),
 200         CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
 201         CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
 202         CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
 203         CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
 204         CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
 205         CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
 206         CLK_MUX("main_pll_hfosc_sel_out19", main_pll_hfosc_sel_out19_parents, 2, 0x430080cc, 0, 1, 0),
 207         CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0),
 208         CLK_MUX("main_pll_hfosc_sel_out26_0", main_pll_hfosc_sel_out26_0_parents, 2, 0x430080e8, 0, 1, 0),
 209         CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0),
 210         CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0),
 211         CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0),
 212         CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0),
 213         CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0),
 214         CLK_FIXED_RATE("board_0_ddr0_ckn_out", 0, 0),
 215         CLK_FIXED_RATE("board_0_ddr0_ckp_out", 0, 0),
 216         CLK_FIXED_RATE("board_0_ddr1_ckn_out", 0, 0),
 217         CLK_FIXED_RATE("board_0_ddr1_ckp_out", 0, 0),
 218         CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
 219         CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0),
 220         CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
 221         CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
 222         CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
 223         CLK_FIXED_RATE("board_0_vout0_extpclkin_out", 0, 0),
 224         CLK_FIXED_RATE("emmc8ss_16ffc_main_0_emmcss_io_clk", 0, 0),
 225         CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
 226         CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
 227         CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
 228         CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0),
 229         CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0),
 230         CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck", 0, 0),
 231         CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n", 0, 0),
 232         CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck", 0, 0),
 233         CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n", 0, 0),
 234         CLK_PLL("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0),
 235         CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
 236         CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
 237         CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
 238         CLK_PLL("pllfracf2_ssmod_16fft_main_19_foutvcop_clk", "main_pll_hfosc_sel_out19", 0x693000, 0),
 239         CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),
 240         CLK_PLL("pllfracf2_ssmod_16fft_main_26_foutvcop_clk", "main_pll_hfosc_sel_out26_0", 0x69a000, 0),
 241         CLK_PLL("pllfracf2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0),
 242         CLK_PLL("pllfracf2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),
 243         CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0),
 244         CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
 245         CLK_DIV("postdiv3_16fft_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
 246         CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0),
 247         CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0),
 248         CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
 249         CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000),
 250         CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0),
 251         CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
 252         CLK_DIV("hsdiv0_16fft_main_26_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_26_foutvcop_clk", 0x69a080, 0, 7, 0, 0),
 253         CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0),
 254         CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
 255         CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0, 0),
 256         CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
 257         CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
 258         CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
 259         CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
 260         CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
 261         CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0),
 262         CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0),
 263         CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
 264         CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
 265         CLK_MUX("dpi0_ext_clksel_out0", dpi0_ext_clksel_out0_parents, 2, 0x108300, 0, 1, 0),
 266         CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),
 267         CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),
 268         CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0),
 269         CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
 270         CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0),
 271 };
 272
 273 static const struct dev_clk soc_dev_clk_data[] = {
 274         DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
 275         DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
 276         DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 277         DEV_CLK(43, 0, "postdiv3_16fft_main_0_hsdivout8_clk"),
 278         DEV_CLK(43, 1, "hsdiv4_16fft_main_0_hsdivout3_clk"),
 279         DEV_CLK(43, 2, "gluelogic_hfosc0_clkout"),
 280         DEV_CLK(43, 3, "board_0_hfosc1_clk_out"),
 281         DEV_CLK(43, 5, "hsdiv4_16fft_main_0_hsdivout2_clk"),
 282         DEV_CLK(43, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 283         DEV_CLK(43, 7, "board_0_hfosc1_clk_out"),
 284         DEV_CLK(43, 9, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 285         DEV_CLK(43, 10, "hsdiv4_16fft_main_0_hsdivout4_clk"),
 286         DEV_CLK(43, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 287         DEV_CLK(43, 12, "gluelogic_hfosc0_clkout"),
 288         DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 289         DEV_CLK(61, 1, "gtc_clk_mux_out0"),
 290         DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"),
 291         DEV_CLK(61, 3, "postdiv3_16fft_main_0_hsdivout6_clk"),
 292         DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"),
 293         DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"),
 294         DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"),
 295         DEV_CLK(61, 7, "board_0_ext_refclk1_out"),
 296         DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
 297         DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 298         DEV_CLK(98, 1, "emmcsd_refclk_sel_out0"),
 299         DEV_CLK(98, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"),
 300         DEV_CLK(98, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"),
 301         DEV_CLK(98, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
 302         DEV_CLK(98, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
 303         DEV_CLK(98, 6, "emmcsd1_lb_clksel_out0"),
 304         DEV_CLK(98, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 305         DEV_CLK(99, 1, "emmcsd_refclk_sel_out1"),
 306         DEV_CLK(99, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"),
 307         DEV_CLK(99, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"),
 308         DEV_CLK(99, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
 309         DEV_CLK(99, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
 310         DEV_CLK(99, 7, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
 311         DEV_CLK(99, 8, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 312         DEV_CLK(108, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
 313         DEV_CLK(108, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
 314         DEV_CLK(108, 3, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
 315         DEV_CLK(108, 6, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
 316         DEV_CLK(108, 11, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 317         DEV_CLK(109, 0, "mcu_ospi0_iclk_sel_out0"),
 318         DEV_CLK(109, 1, "board_0_mcu_ospi0_dqs_out"),
 319         DEV_CLK(109, 2, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
 320         DEV_CLK(109, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 321         DEV_CLK(109, 5, "mcu_ospi_ref_clk_sel_out0"),
 322         DEV_CLK(109, 6, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
 323         DEV_CLK(109, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
 324         DEV_CLK(109, 8, "board_0_mcu_ospi0_dqs_out"),
 325         DEV_CLK(109, 9, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 326         DEV_CLK(110, 0, "mcu_ospi1_iclk_sel_out0"),
 327         DEV_CLK(110, 1, "board_0_mcu_ospi1_dqs_out"),
 328         DEV_CLK(110, 2, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
 329         DEV_CLK(110, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 330         DEV_CLK(110, 5, "mcu_ospi_ref_clk_sel_out1"),
 331         DEV_CLK(110, 6, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
 332         DEV_CLK(110, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
 333         DEV_CLK(110, 8, "board_0_mcu_ospi1_dqs_out"),
 334         DEV_CLK(110, 9, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 335         DEV_CLK(115, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 336         DEV_CLK(126, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 337         DEV_CLK(126, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 338         DEV_CLK(138, 0, "hsdiv0_16fft_main_12_hsdivout0_clk"),
 339         DEV_CLK(138, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
 340         DEV_CLK(138, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 341         DEV_CLK(138, 3, "board_0_ddr0_ckn_out"),
 342         DEV_CLK(138, 5, "board_0_ddr0_ckp_out"),
 343         DEV_CLK(138, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 344         DEV_CLK(139, 0, "hsdiv0_16fft_main_26_hsdivout0_clk"),
 345         DEV_CLK(139, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
 346         DEV_CLK(139, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 347         DEV_CLK(139, 3, "board_0_ddr1_ckn_out"),
 348         DEV_CLK(139, 5, "board_0_ddr1_ckp_out"),
 349         DEV_CLK(139, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 350         DEV_CLK(143, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 351         DEV_CLK(143, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 352         DEV_CLK(146, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 353         DEV_CLK(146, 3, "usart_programmable_clock_divider_out0"),
 354         DEV_CLK(149, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 355         DEV_CLK(149, 3, "mcu_usart_clksel_out0"),
 356         DEV_CLK(149, 4, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
 357         DEV_CLK(149, 5, "postdiv3_16fft_main_1_hsdivout5_clk"),
 358         DEV_CLK(157, 9, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
 359         DEV_CLK(157, 103, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
 360         DEV_CLK(157, 104, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck"),
 361         DEV_CLK(157, 111, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 362         DEV_CLK(157, 174, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck"),
 363         DEV_CLK(157, 177, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 364         DEV_CLK(157, 179, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
 365         DEV_CLK(157, 182, "mshsi2c_wkup_0_porscl"),
 366         DEV_CLK(157, 187, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
 367         DEV_CLK(157, 194, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
 368         DEV_CLK(157, 197, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n"),
 369         DEV_CLK(157, 208, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n"),
 370         DEV_CLK(157, 214, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
 371         DEV_CLK(157, 221, "mcu_clkout_mux_out0"),
 372         DEV_CLK(157, 222, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
 373         DEV_CLK(157, 223, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
 374         DEV_CLK(157, 225, "emmc8ss_16ffc_main_0_emmcss_io_clk"),
 375         DEV_CLK(157, 231, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
 376         DEV_CLK(157, 352, "dpi0_ext_clksel_out0"),
 377         DEV_CLK(180, 0, "gluelogic_hfosc0_clkout"),
 378         DEV_CLK(180, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 379         DEV_CLK(202, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
 380         DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
 381         DEV_CLK(223, 1, "wkup_i2c_mcupll_bypass_out0"),
 382         DEV_CLK(223, 2, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
 383         DEV_CLK(223, 3, "gluelogic_hfosc0_clkout"),
 384         DEV_CLK(223, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 385         DEV_CLK(223, 5, "board_0_wkup_i2c0_scl_out"),
 386         DEV_CLK(357, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 387         DEV_CLK(357, 3, "usart_programmable_clock_divider_out8"),
 388         DEV_CLK(360, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 389         DEV_CLK(360, 13, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 390         DEV_CLK(360, 15, "postdiv3_16fft_main_1_hsdivout7_clk"),
 391         DEV_CLK(360, 16, "usb0_refclk_sel_out0"),
 392         DEV_CLK(360, 17, "gluelogic_hfosc0_clkout"),
 393         DEV_CLK(360, 18, "board_0_hfosc1_clk_out"),
 394         DEV_CLK(360, 22, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 395         DEV_CLK(360, 23, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 396 };
 397
 398 const struct ti_k3_clk_platdata j721s2_clk_platdata = {
 399         .clk_list = clk_list,
 400         .clk_list_cnt = 104,
 401         .soc_dev_clk_data = soc_dev_clk_data,
 402         .soc_dev_clk_data_cnt = 122,
 403 };