arch/arm/mach-k3/j721e_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * J721E: SoC specific initialization
   4  *
   5  * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
   6  *      Lokesh Vutla <lokeshvutla@ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <init.h>
  11 #include <spl.h>
  12 #include <asm/io.h>
  13 #include <asm/armv7_mpu.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sysfw-loader.h>
  16 #include "common.h"
  17 #include <asm/arch/sys_proto.h>
  18 #include <linux/soc/ti/ti_sci_protocol.h>
  19 #include <dm.h>
  20 #include <dm/uclass-internal.h>
  21 #include <dm/pinctrl.h>
  22 #include <dm/root.h>
  23 #include <fdtdec.h>
  24 #include <mmc.h>
  25 #include <remoteproc.h>
  26
  27 #ifdef CONFIG_SPL_BUILD
  28 #ifdef CONFIG_K3_LOAD_SYSFW
  29 #ifdef CONFIG_TI_SECURE_DEVICE
  30 struct fwl_data cbass_hc_cfg0_fwls[] = {
  31         { "PCIE0_CFG", 2560, 8 },
  32         { "PCIE1_CFG", 2561, 8 },
  33         { "USB3SS0_CORE", 2568, 4 },
  34         { "USB3SS1_CORE", 2570, 4 },
  35         { "EMMC8SS0_CFG", 2576, 4 },
  36         { "UFS_HCI0_CFG", 2580, 4 },
  37         { "SERDES0", 2584, 1 },
  38         { "SERDES1", 2585, 1 },
  39 }, cbass_hc0_fwls[] = {
  40         { "PCIE0_HP", 2528, 24 },
  41         { "PCIE0_LP", 2529, 24 },
  42         { "PCIE1_HP", 2530, 24 },
  43         { "PCIE1_LP", 2531, 24 },
  44 }, cbass_rc_cfg0_fwls[] = {
  45         { "EMMCSD4SS0_CFG", 2380, 4 },
  46 }, cbass_rc0_fwls[] = {
  47         { "GPMC0", 2310, 8 },
  48 }, infra_cbass0_fwls[] = {
  49         { "PLL_MMR0", 8, 26 },
  50         { "CTRL_MMR0", 9, 16 },
  51 }, mcu_cbass0_fwls[] = {
  52         { "MCU_R5FSS0_CORE0", 1024, 4 },
  53         { "MCU_R5FSS0_CORE0_CFG", 1025, 2 },
  54         { "MCU_R5FSS0_CORE1", 1028, 4 },
  55         { "MCU_FSS0_CFG", 1032, 12 },
  56         { "MCU_FSS0_S1", 1033, 8 },
  57         { "MCU_FSS0_S0", 1036, 8 },
  58         { "MCU_PSROM49152X32", 1048, 1 },
  59         { "MCU_MSRAM128KX64", 1050, 8 },
  60         { "MCU_CTRL_MMR0", 1200, 8 },
  61         { "MCU_PLL_MMR0", 1201, 3 },
  62         { "MCU_CPSW0", 1220, 2 },
  63 }, wkup_cbass0_fwls[] = {
  64         { "WKUP_CTRL_MMR0", 131, 16 },
  65 };
  66 #endif
  67 #endif
  68
  69 static void ctrl_mmr_unlock(void)
  70 {
  71         /* Unlock all WKUP_CTRL_MMR0 module registers */
  72         mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  73         mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  74         mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  75         mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  76         mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
  77         mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  78         mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  79
  80         /* Unlock all MCU_CTRL_MMR0 module registers */
  81         mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  82         mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  83         mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  84         mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
  85         mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
  86
  87         /* Unlock all CTRL_MMR0 module registers */
  88         mmr_unlock(CTRL_MMR0_BASE, 0);
  89         mmr_unlock(CTRL_MMR0_BASE, 1);
  90         mmr_unlock(CTRL_MMR0_BASE, 2);
  91         mmr_unlock(CTRL_MMR0_BASE, 3);
  92         mmr_unlock(CTRL_MMR0_BASE, 5);
  93         if (soc_is_j721e())
  94                 mmr_unlock(CTRL_MMR0_BASE, 6);
  95         mmr_unlock(CTRL_MMR0_BASE, 7);
  96 }
  97
  98 #if defined(CONFIG_K3_LOAD_SYSFW)
  99 void k3_mmc_stop_clock(void)
 100 {
 101         if (spl_boot_device() == BOOT_DEVICE_MMC1) {
 102                 struct mmc *mmc = find_mmc_device(0);
 103
 104                 if (!mmc)
 105                         return;
 106
 107                 mmc->saved_clock = mmc->clock;
 108                 mmc_set_clock(mmc, 0, true);
 109         }
 110 }
 111
 112 void k3_mmc_restart_clock(void)
 113 {
 114         if (spl_boot_device() == BOOT_DEVICE_MMC1) {
 115                 struct mmc *mmc = find_mmc_device(0);
 116
 117                 if (!mmc)
 118                         return;
 119
 120                 mmc_set_clock(mmc, mmc->saved_clock, false);
 121         }
 122 }
 123 #endif
 124
 125 /*
 126  * This uninitialized global variable would normal end up in the .bss section,
 127  * but the .bss is cleared between writing and reading this variable, so move
 128  * it to the .data section.
 129  */
 130 u32 bootindex __section(".data");
 131 static struct rom_extended_boot_data bootdata __section(".data");
 132
 133 static void store_boot_info_from_rom(void)
 134 {
 135         bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
 136         memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
 137                sizeof(struct rom_extended_boot_data));
 138 }
 139
 140 #ifdef CONFIG_SPL_OF_LIST
 141 void do_dt_magic(void)
 142 {
 143         int ret, rescan, mmc_dev = -1;
 144         static struct mmc *mmc;
 145
 146         if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
 147                 do_board_detect();
 148
 149         /*
 150          * Board detection has been done.
 151          * Let us see if another dtb wouldn't be a better match
 152          * for our board
 153          */
 154         if (IS_ENABLED(CONFIG_CPU_V7R)) {
 155                 ret = fdtdec_resetup(&rescan);
 156                 if (!ret && rescan) {
 157                         dm_uninit();
 158                         dm_init_and_scan(true);
 159                 }
 160         }
 161
 162         /*
 163          * Because of multi DTB configuration, the MMC device has
 164          * to be re-initialized after reconfiguring FDT inorder to
 165          * boot from MMC. Do this when boot mode is MMC and ROM has
 166          * not loaded SYSFW.
 167          */
 168         switch (spl_boot_device()) {
 169         case BOOT_DEVICE_MMC1:
 170                 mmc_dev = 0;
 171                 break;
 172         case BOOT_DEVICE_MMC2:
 173         case BOOT_DEVICE_MMC2_2:
 174                 mmc_dev = 1;
 175                 break;
 176         }
 177
 178         if (mmc_dev > 0 && !is_rom_loaded_sysfw(&bootdata)) {
 179                 ret = mmc_init_device(mmc_dev);
 180                 if (!ret) {
 181                         mmc = find_mmc_device(mmc_dev);
 182                         if (mmc) {
 183                                 ret = mmc_init(mmc);
 184                                 if (ret) {
 185                                         printf("mmc init failed with error: %d\n", ret);
 186                                 }
 187                         }
 188                 }
 189         }
 190 }
 191 #endif
 192
 193 void board_init_f(ulong dummy)
 194 {
 195 #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
 196         struct udevice *dev;
 197         int ret;
 198 #endif
 199         /*
 200          * Cannot delay this further as there is a chance that
 201          * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
 202          */
 203         store_boot_info_from_rom();
 204
 205         /* Make all control module registers accessible */
 206         ctrl_mmr_unlock();
 207
 208 #ifdef CONFIG_CPU_V7R
 209         disable_linefill_optimization();
 210         setup_k3_mpu_regions();
 211 #endif
 212
 213         /* Init DM early */
 214         spl_early_init();
 215
 216 #ifdef CONFIG_K3_LOAD_SYSFW
 217         /*
 218          * Process pinctrl for the serial0 a.k.a. MCU_UART0 module and continue
 219          * regardless of the result of pinctrl. Do this without probing the
 220          * device, but instead by searching the device that would request the
 221          * given sequence number if probed. The UART will be used by the system
 222          * firmware (SYSFW) image for various purposes and SYSFW depends on us
 223          * to initialize its pin settings.
 224          */
 225         ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
 226         if (!ret)
 227                 pinctrl_select_state(dev, "default");
 228
 229         /*
 230          * Load, start up, and configure system controller firmware. Provide
 231          * the U-Boot console init function to the SYSFW post-PM configuration
 232          * callback hook, effectively switching on (or over) the console
 233          * output.
 234          */
 235         k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
 236                         k3_mmc_stop_clock, k3_mmc_restart_clock);
 237
 238 #ifdef CONFIG_SPL_OF_LIST
 239         do_dt_magic();
 240 #endif
 241
 242         /*
 243          * Force probe of clk_k3 driver here to ensure basic default clock
 244          * configuration is always done.
 245          */
 246         if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
 247                 ret = uclass_get_device_by_driver(UCLASS_CLK,
 248                                                   DM_DRIVER_GET(ti_clk),
 249                                                   &dev);
 250                 if (ret)
 251                         panic("Failed to initialize clk-k3!\n");
 252         }
 253
 254         /* Prepare console output */
 255         preloader_console_init();
 256
 257         /* Disable ROM configured firewalls right after loading sysfw */
 258 #ifdef CONFIG_TI_SECURE_DEVICE
 259         remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
 260         remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls));
 261         remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
 262         remove_fwl_configs(cbass_rc0_fwls, ARRAY_SIZE(cbass_rc0_fwls));
 263         remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
 264         remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
 265         remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
 266 #endif
 267 #else
 268         /* Prepare console output */
 269         preloader_console_init();
 270 #endif
 271
 272         /* Output System Firmware version info */
 273         k3_sysfw_print_ver();
 274
 275         /* Perform EEPROM-based board detection */
 276         if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
 277                 do_board_detect();
 278
 279 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
 280         ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
 281                                           &dev);
 282         if (ret)
 283                 printf("AVS init failed: %d\n", ret);
 284 #endif
 285
 286 #if defined(CONFIG_K3_J721E_DDRSS)
 287         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 288         if (ret)
 289                 panic("DRAM init failed: %d\n", ret);
 290 #endif
 291         spl_enable_dcache();
 292 }
 293
 294 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
 295 {
 296         switch (boot_device) {
 297         case BOOT_DEVICE_MMC1:
 298                 return MMCSD_MODE_EMMCBOOT;
 299         case BOOT_DEVICE_MMC2:
 300                 return MMCSD_MODE_FS;
 301         default:
 302                 return MMCSD_MODE_RAW;
 303         }
 304 }
 305
 306 static u32 __get_backup_bootmedia(u32 main_devstat)
 307 {
 308         u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
 309                         MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
 310
 311         switch (bkup_boot) {
 312         case BACKUP_BOOT_DEVICE_USB:
 313                 return BOOT_DEVICE_DFU;
 314         case BACKUP_BOOT_DEVICE_UART:
 315                 return BOOT_DEVICE_UART;
 316         case BACKUP_BOOT_DEVICE_ETHERNET:
 317                 return BOOT_DEVICE_ETHERNET;
 318         case BACKUP_BOOT_DEVICE_MMC2:
 319         {
 320                 u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
 321                             MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
 322                 if (port == 0x0)
 323                         return BOOT_DEVICE_MMC1;
 324                 return BOOT_DEVICE_MMC2;
 325         }
 326         case BACKUP_BOOT_DEVICE_SPI:
 327                 return BOOT_DEVICE_SPI;
 328         case BACKUP_BOOT_DEVICE_I2C:
 329                 return BOOT_DEVICE_I2C;
 330         }
 331
 332         return BOOT_DEVICE_RAM;
 333 }
 334
 335 static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
 336 {
 337
 338         u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
 339                         WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
 340
 341         bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
 342                         BOOT_MODE_B_SHIFT;
 343
 344         if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
 345                 bootmode = BOOT_DEVICE_SPI;
 346
 347         if (bootmode == BOOT_DEVICE_MMC2) {
 348                 u32 port = (main_devstat &
 349                             MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
 350                            MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
 351                 if (port == 0x0)
 352                         bootmode = BOOT_DEVICE_MMC1;
 353         }
 354
 355         return bootmode;
 356 }
 357
 358 u32 spl_boot_device(void)
 359 {
 360         u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
 361         u32 main_devstat;
 362
 363         if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
 364                 printf("ERROR: MCU only boot is not yet supported\n");
 365                 return BOOT_DEVICE_RAM;
 366         }
 367
 368         /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
 369         main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 370
 371         if (bootindex == K3_PRIMARY_BOOTMODE)
 372                 return __get_primary_bootmedia(main_devstat, wkup_devstat);
 373         else
 374                 return __get_backup_bootmedia(main_devstat);
 375 }
 376 #endif
 377
 378 #ifdef CONFIG_SYS_K3_SPL_ATF
 379
 380 #define J721E_DEV_MCU_RTI0                      262
 381 #define J721E_DEV_MCU_RTI1                      263
 382 #define J721E_DEV_MCU_ARMSS0_CPU0               250
 383 #define J721E_DEV_MCU_ARMSS0_CPU1               251
 384
 385 void release_resources_for_core_shutdown(void)
 386 {
 387         struct ti_sci_handle *ti_sci;
 388         struct ti_sci_dev_ops *dev_ops;
 389         struct ti_sci_proc_ops *proc_ops;
 390         int ret;
 391         u32 i;
 392
 393         const u32 put_device_ids[] = {
 394                 J721E_DEV_MCU_RTI0,
 395                 J721E_DEV_MCU_RTI1,
 396         };
 397
 398         ti_sci = get_ti_sci_handle();
 399         dev_ops = &ti_sci->ops.dev_ops;
 400         proc_ops = &ti_sci->ops.proc_ops;
 401
 402         /* Iterate through list of devices to put (shutdown) */
 403         for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
 404                 u32 id = put_device_ids[i];
 405
 406                 ret = dev_ops->put_device(ti_sci, id);
 407                 if (ret)
 408                         panic("Failed to put device %u (%d)\n", id, ret);
 409         }
 410
 411         const u32 put_core_ids[] = {
 412                 J721E_DEV_MCU_ARMSS0_CPU1,
 413                 J721E_DEV_MCU_ARMSS0_CPU0,      /* Handle CPU0 after CPU1 */
 414         };
 415
 416         /* Iterate through list of cores to put (shutdown) */
 417         for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
 418                 u32 id = put_core_ids[i];
 419
 420                 /*
 421                  * Queue up the core shutdown request. Note that this call
 422                  * needs to be followed up by an actual invocation of an WFE
 423                  * or WFI CPU instruction.
 424                  */
 425                 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
 426                 if (ret)
 427                         panic("Failed sending core %u shutdown message (%d)\n",
 428                               id, ret);
 429         }
 430 }
 431 #endif