arch/arm/mach-k3/j721e_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * J721E: SoC specific initialization
   4  *
   5  * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
   6  *      Lokesh Vutla <lokeshvutla@ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <init.h>
  11 #include <spl.h>
  12 #include <asm/io.h>
  13 #include <asm/armv7_mpu.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sysfw-loader.h>
  16 #include "common.h"
  17 #include <asm/arch/sys_proto.h>
  18 #include <linux/soc/ti/ti_sci_protocol.h>
  19 #include <dm.h>
  20 #include <dm/uclass-internal.h>
  21 #include <dm/pinctrl.h>
  22 #include <mmc.h>
  23 #include <remoteproc.h>
  24
  25 #ifdef CONFIG_SPL_BUILD
  26 #ifdef CONFIG_K3_LOAD_SYSFW
  27 #ifdef CONFIG_TI_SECURE_DEVICE
  28 struct fwl_data cbass_hc_cfg0_fwls[] = {
  29         { "PCIE0_CFG", 2560, 8 },
  30         { "PCIE1_CFG", 2561, 8 },
  31         { "USB3SS0_CORE", 2568, 4 },
  32         { "USB3SS1_CORE", 2570, 4 },
  33         { "EMMC8SS0_CFG", 2576, 4 },
  34         { "UFS_HCI0_CFG", 2580, 4 },
  35         { "SERDES0", 2584, 1 },
  36         { "SERDES1", 2585, 1 },
  37 }, cbass_hc0_fwls[] = {
  38         { "PCIE0_HP", 2528, 24 },
  39         { "PCIE0_LP", 2529, 24 },
  40         { "PCIE1_HP", 2530, 24 },
  41         { "PCIE1_LP", 2531, 24 },
  42 }, cbass_rc_cfg0_fwls[] = {
  43         { "EMMCSD4SS0_CFG", 2380, 4 },
  44 }, cbass_rc0_fwls[] = {
  45         { "GPMC0", 2310, 8 },
  46 }, infra_cbass0_fwls[] = {
  47         { "PLL_MMR0", 8, 26 },
  48         { "CTRL_MMR0", 9, 16 },
  49 }, mcu_cbass0_fwls[] = {
  50         { "MCU_R5FSS0_CORE0", 1024, 4 },
  51         { "MCU_R5FSS0_CORE0_CFG", 1025, 2 },
  52         { "MCU_R5FSS0_CORE1", 1028, 4 },
  53         { "MCU_FSS0_CFG", 1032, 12 },
  54         { "MCU_FSS0_S1", 1033, 8 },
  55         { "MCU_FSS0_S0", 1036, 8 },
  56         { "MCU_PSROM49152X32", 1048, 1 },
  57         { "MCU_MSRAM128KX64", 1050, 8 },
  58         { "MCU_CTRL_MMR0", 1200, 8 },
  59         { "MCU_PLL_MMR0", 1201, 3 },
  60         { "MCU_CPSW0", 1220, 2 },
  61 }, wkup_cbass0_fwls[] = {
  62         { "WKUP_CTRL_MMR0", 131, 16 },
  63 };
  64 #endif
  65 #endif
  66
  67 static void ctrl_mmr_unlock(void)
  68 {
  69         /* Unlock all WKUP_CTRL_MMR0 module registers */
  70         mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  71         mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  72         mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  73         mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  74         mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
  75         mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  76         mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  77
  78         /* Unlock all MCU_CTRL_MMR0 module registers */
  79         mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  80         mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  81         mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  82         mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
  83         mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
  84
  85         /* Unlock all CTRL_MMR0 module registers */
  86         mmr_unlock(CTRL_MMR0_BASE, 0);
  87         mmr_unlock(CTRL_MMR0_BASE, 1);
  88         mmr_unlock(CTRL_MMR0_BASE, 2);
  89         mmr_unlock(CTRL_MMR0_BASE, 3);
  90         mmr_unlock(CTRL_MMR0_BASE, 5);
  91         if (soc_is_j721e())
  92                 mmr_unlock(CTRL_MMR0_BASE, 6);
  93         mmr_unlock(CTRL_MMR0_BASE, 7);
  94 }
  95
  96 #if defined(CONFIG_K3_LOAD_SYSFW)
  97 void k3_mmc_stop_clock(void)
  98 {
  99         if (spl_boot_device() == BOOT_DEVICE_MMC1) {
 100                 struct mmc *mmc = find_mmc_device(0);
 101
 102                 if (!mmc)
 103                         return;
 104
 105                 mmc->saved_clock = mmc->clock;
 106                 mmc_set_clock(mmc, 0, true);
 107         }
 108 }
 109
 110 void k3_mmc_restart_clock(void)
 111 {
 112         if (spl_boot_device() == BOOT_DEVICE_MMC1) {
 113                 struct mmc *mmc = find_mmc_device(0);
 114
 115                 if (!mmc)
 116                         return;
 117
 118                 mmc_set_clock(mmc, mmc->saved_clock, false);
 119         }
 120 }
 121 #endif
 122
 123 /*
 124  * This uninitialized global variable would normal end up in the .bss section,
 125  * but the .bss is cleared between writing and reading this variable, so move
 126  * it to the .data section.
 127  */
 128 u32 bootindex __section(".data");
 129 static struct rom_extended_boot_data bootdata __section(".data");
 130
 131 static void store_boot_info_from_rom(void)
 132 {
 133         bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
 134         memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
 135                sizeof(struct rom_extended_boot_data));
 136 }
 137
 138 void board_init_f(ulong dummy)
 139 {
 140 #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
 141         struct udevice *dev;
 142         int ret;
 143 #endif
 144         /*
 145          * Cannot delay this further as there is a chance that
 146          * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
 147          */
 148         store_boot_info_from_rom();
 149
 150         /* Make all control module registers accessible */
 151         ctrl_mmr_unlock();
 152
 153 #ifdef CONFIG_CPU_V7R
 154         disable_linefill_optimization();
 155         setup_k3_mpu_regions();
 156 #endif
 157
 158         /* Init DM early */
 159         spl_early_init();
 160
 161 #ifdef CONFIG_K3_LOAD_SYSFW
 162         /*
 163          * Process pinctrl for the serial0 a.k.a. MCU_UART0 module and continue
 164          * regardless of the result of pinctrl. Do this without probing the
 165          * device, but instead by searching the device that would request the
 166          * given sequence number if probed. The UART will be used by the system
 167          * firmware (SYSFW) image for various purposes and SYSFW depends on us
 168          * to initialize its pin settings.
 169          */
 170         ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
 171         if (!ret)
 172                 pinctrl_select_state(dev, "default");
 173
 174         /*
 175          * Load, start up, and configure system controller firmware. Provide
 176          * the U-Boot console init function to the SYSFW post-PM configuration
 177          * callback hook, effectively switching on (or over) the console
 178          * output.
 179          */
 180         k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
 181                         k3_mmc_stop_clock, k3_mmc_restart_clock);
 182
 183         /*
 184          * Force probe of clk_k3 driver here to ensure basic default clock
 185          * configuration is always done.
 186          */
 187         if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
 188                 ret = uclass_get_device_by_driver(UCLASS_CLK,
 189                                                   DM_DRIVER_GET(ti_clk),
 190                                                   &dev);
 191                 if (ret)
 192                         panic("Failed to initialize clk-k3!\n");
 193         }
 194
 195         /* Prepare console output */
 196         preloader_console_init();
 197
 198         /* Disable ROM configured firewalls right after loading sysfw */
 199 #ifdef CONFIG_TI_SECURE_DEVICE
 200         remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
 201         remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls));
 202         remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
 203         remove_fwl_configs(cbass_rc0_fwls, ARRAY_SIZE(cbass_rc0_fwls));
 204         remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
 205         remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
 206         remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
 207 #endif
 208 #else
 209         /* Prepare console output */
 210         preloader_console_init();
 211 #endif
 212
 213         /* Output System Firmware version info */
 214         k3_sysfw_print_ver();
 215
 216         /* Perform EEPROM-based board detection */
 217         if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
 218                 do_board_detect();
 219
 220 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
 221         ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
 222                                           &dev);
 223         if (ret)
 224                 printf("AVS init failed: %d\n", ret);
 225 #endif
 226
 227 #if defined(CONFIG_K3_J721E_DDRSS)
 228         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 229         if (ret)
 230                 panic("DRAM init failed: %d\n", ret);
 231 #endif
 232         spl_enable_dcache();
 233 }
 234
 235 u32 spl_mmc_boot_mode(const u32 boot_device)
 236 {
 237         switch (boot_device) {
 238         case BOOT_DEVICE_MMC1:
 239                 return MMCSD_MODE_EMMCBOOT;
 240         case BOOT_DEVICE_MMC2:
 241                 return MMCSD_MODE_FS;
 242         default:
 243                 return MMCSD_MODE_RAW;
 244         }
 245 }
 246
 247 static u32 __get_backup_bootmedia(u32 main_devstat)
 248 {
 249         u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
 250                         MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
 251
 252         switch (bkup_boot) {
 253         case BACKUP_BOOT_DEVICE_USB:
 254                 return BOOT_DEVICE_DFU;
 255         case BACKUP_BOOT_DEVICE_UART:
 256                 return BOOT_DEVICE_UART;
 257         case BACKUP_BOOT_DEVICE_ETHERNET:
 258                 return BOOT_DEVICE_ETHERNET;
 259         case BACKUP_BOOT_DEVICE_MMC2:
 260         {
 261                 u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
 262                             MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
 263                 if (port == 0x0)
 264                         return BOOT_DEVICE_MMC1;
 265                 return BOOT_DEVICE_MMC2;
 266         }
 267         case BACKUP_BOOT_DEVICE_SPI:
 268                 return BOOT_DEVICE_SPI;
 269         case BACKUP_BOOT_DEVICE_I2C:
 270                 return BOOT_DEVICE_I2C;
 271         }
 272
 273         return BOOT_DEVICE_RAM;
 274 }
 275
 276 static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
 277 {
 278
 279         u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
 280                         WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
 281
 282         bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
 283                         BOOT_MODE_B_SHIFT;
 284
 285         if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
 286                 bootmode = BOOT_DEVICE_SPI;
 287
 288         if (bootmode == BOOT_DEVICE_MMC2) {
 289                 u32 port = (main_devstat &
 290                             MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
 291                            MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
 292                 if (port == 0x0)
 293                         bootmode = BOOT_DEVICE_MMC1;
 294         }
 295
 296         return bootmode;
 297 }
 298
 299 u32 spl_boot_device(void)
 300 {
 301         u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
 302         u32 main_devstat;
 303
 304         if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
 305                 printf("ERROR: MCU only boot is not yet supported\n");
 306                 return BOOT_DEVICE_RAM;
 307         }
 308
 309         /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
 310         main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 311
 312         if (bootindex == K3_PRIMARY_BOOTMODE)
 313                 return __get_primary_bootmedia(main_devstat, wkup_devstat);
 314         else
 315                 return __get_backup_bootmedia(main_devstat);
 316 }
 317 #endif
 318
 319 #ifdef CONFIG_SYS_K3_SPL_ATF
 320
 321 #define J721E_DEV_MCU_RTI0                      262
 322 #define J721E_DEV_MCU_RTI1                      263
 323 #define J721E_DEV_MCU_ARMSS0_CPU0               250
 324 #define J721E_DEV_MCU_ARMSS0_CPU1               251
 325
 326 void release_resources_for_core_shutdown(void)
 327 {
 328         struct ti_sci_handle *ti_sci;
 329         struct ti_sci_dev_ops *dev_ops;
 330         struct ti_sci_proc_ops *proc_ops;
 331         int ret;
 332         u32 i;
 333
 334         const u32 put_device_ids[] = {
 335                 J721E_DEV_MCU_RTI0,
 336                 J721E_DEV_MCU_RTI1,
 337         };
 338
 339         ti_sci = get_ti_sci_handle();
 340         dev_ops = &ti_sci->ops.dev_ops;
 341         proc_ops = &ti_sci->ops.proc_ops;
 342
 343         /* Iterate through list of devices to put (shutdown) */
 344         for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
 345                 u32 id = put_device_ids[i];
 346
 347                 ret = dev_ops->put_device(ti_sci, id);
 348                 if (ret)
 349                         panic("Failed to put device %u (%d)\n", id, ret);
 350         }
 351
 352         const u32 put_core_ids[] = {
 353                 J721E_DEV_MCU_ARMSS0_CPU1,
 354                 J721E_DEV_MCU_ARMSS0_CPU0,      /* Handle CPU0 after CPU1 */
 355         };
 356
 357         /* Iterate through list of cores to put (shutdown) */
 358         for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
 359                 u32 id = put_core_ids[i];
 360
 361                 /*
 362                  * Queue up the core shutdown request. Note that this call
 363                  * needs to be followed up by an actual invocation of an WFE
 364                  * or WFI CPU instruction.
 365                  */
 366                 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
 367                 if (ret)
 368                         panic("Failed sending core %u shutdown message (%d)\n",
 369                               id, ret);
 370         }
 371 }
 372 #endif
 373
 374 #ifdef CONFIG_SYS_K3_SPL_ATF
 375 void start_non_linux_remote_cores(void)
 376 {
 377         int size = 0, ret;
 378         u32 loadaddr = 0;
 379
 380         if (!soc_is_j721e())
 381                 return;
 382
 383         size = load_firmware("name_mainr5f0_0fw", "addr_mainr5f0_0load",
 384                              &loadaddr);
 385         if (size <= 0)
 386                 goto err_load;
 387
 388         /* assuming remoteproc 2 is aliased for the needed remotecore */
 389         ret = rproc_load(2, loadaddr, size);
 390         if (ret) {
 391                 printf("Firmware failed to start on rproc (%d)\n", ret);
 392                 goto err_load;
 393         }
 394
 395         ret = rproc_start(2);
 396         if (ret) {
 397                 printf("Firmware init failed on rproc (%d)\n", ret);
 398                 goto err_load;
 399         }
 400
 401         printf("Remoteproc 2 started successfully\n");
 402
 403         return;
 404
 405 err_load:
 406         rproc_reset(2);
 407 }
 408 #endif