arch/arm/mach-k3/j721e_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * J721E: SoC specific initialization
   4  *
   5  * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
   6  *      Lokesh Vutla <lokeshvutla@ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <init.h>
  11 #include <spl.h>
  12 #include <asm/io.h>
  13 #include <asm/armv7_mpu.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sysfw-loader.h>
  16 #include "common.h"
  17 #include <asm/arch/sys_proto.h>
  18 #include <linux/soc/ti/ti_sci_protocol.h>
  19 #include <dm.h>
  20 #include <dm/uclass-internal.h>
  21 #include <dm/pinctrl.h>
  22 #include <dm/root.h>
  23 #include <fdtdec.h>
  24 #include <mmc.h>
  25 #include <remoteproc.h>
  26
  27 #ifdef CONFIG_K3_LOAD_SYSFW
  28 struct fwl_data cbass_hc_cfg0_fwls[] = {
  29         { "PCIE0_CFG", 2560, 8 },
  30         { "PCIE1_CFG", 2561, 8 },
  31         { "USB3SS0_CORE", 2568, 4 },
  32         { "USB3SS1_CORE", 2570, 4 },
  33         { "EMMC8SS0_CFG", 2576, 4 },
  34         { "UFS_HCI0_CFG", 2580, 4 },
  35         { "SERDES0", 2584, 1 },
  36         { "SERDES1", 2585, 1 },
  37 }, cbass_hc0_fwls[] = {
  38         { "PCIE0_HP", 2528, 24 },
  39         { "PCIE0_LP", 2529, 24 },
  40         { "PCIE1_HP", 2530, 24 },
  41         { "PCIE1_LP", 2531, 24 },
  42 }, cbass_rc_cfg0_fwls[] = {
  43         { "EMMCSD4SS0_CFG", 2380, 4 },
  44 }, cbass_rc0_fwls[] = {
  45         { "GPMC0", 2310, 8 },
  46 }, infra_cbass0_fwls[] = {
  47         { "PLL_MMR0", 8, 26 },
  48         { "CTRL_MMR0", 9, 16 },
  49 }, mcu_cbass0_fwls[] = {
  50         { "MCU_R5FSS0_CORE0", 1024, 4 },
  51         { "MCU_R5FSS0_CORE0_CFG", 1025, 2 },
  52         { "MCU_R5FSS0_CORE1", 1028, 4 },
  53         { "MCU_FSS0_CFG", 1032, 12 },
  54         { "MCU_FSS0_S1", 1033, 8 },
  55         { "MCU_FSS0_S0", 1036, 8 },
  56         { "MCU_PSROM49152X32", 1048, 1 },
  57         { "MCU_MSRAM128KX64", 1050, 8 },
  58         { "MCU_CTRL_MMR0", 1200, 8 },
  59         { "MCU_PLL_MMR0", 1201, 3 },
  60         { "MCU_CPSW0", 1220, 2 },
  61 }, wkup_cbass0_fwls[] = {
  62         { "WKUP_CTRL_MMR0", 131, 16 },
  63 };
  64 #endif
  65
  66 static void ctrl_mmr_unlock(void)
  67 {
  68         /* Unlock all WKUP_CTRL_MMR0 module registers */
  69         mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
  70         mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
  71         mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
  72         mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
  73         mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
  74         mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
  75         mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
  76
  77         /* Unlock all MCU_CTRL_MMR0 module registers */
  78         mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
  79         mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
  80         mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
  81         mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
  82         mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
  83
  84         /* Unlock all CTRL_MMR0 module registers */
  85         mmr_unlock(CTRL_MMR0_BASE, 0);
  86         mmr_unlock(CTRL_MMR0_BASE, 1);
  87         mmr_unlock(CTRL_MMR0_BASE, 2);
  88         mmr_unlock(CTRL_MMR0_BASE, 3);
  89         mmr_unlock(CTRL_MMR0_BASE, 5);
  90         if (soc_is_j721e())
  91                 mmr_unlock(CTRL_MMR0_BASE, 6);
  92         mmr_unlock(CTRL_MMR0_BASE, 7);
  93 }
  94
  95 #if defined(CONFIG_K3_LOAD_SYSFW)
  96 void k3_mmc_stop_clock(void)
  97 {
  98         if (spl_boot_device() == BOOT_DEVICE_MMC1) {
  99                 struct mmc *mmc = find_mmc_device(0);
 100
 101                 if (!mmc)
 102                         return;
 103
 104                 mmc->saved_clock = mmc->clock;
 105                 mmc_set_clock(mmc, 0, true);
 106         }
 107 }
 108
 109 void k3_mmc_restart_clock(void)
 110 {
 111         if (spl_boot_device() == BOOT_DEVICE_MMC1) {
 112                 struct mmc *mmc = find_mmc_device(0);
 113
 114                 if (!mmc)
 115                         return;
 116
 117                 mmc_set_clock(mmc, mmc->saved_clock, false);
 118         }
 119 }
 120 #endif
 121
 122 /*
 123  * This uninitialized global variable would normal end up in the .bss section,
 124  * but the .bss is cleared between writing and reading this variable, so move
 125  * it to the .data section.
 126  */
 127 u32 bootindex __section(".data");
 128 static struct rom_extended_boot_data bootdata __section(".data");
 129
 130 static void store_boot_info_from_rom(void)
 131 {
 132         bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
 133         memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
 134                sizeof(struct rom_extended_boot_data));
 135 }
 136
 137 #ifdef CONFIG_SPL_OF_LIST
 138 void do_dt_magic(void)
 139 {
 140         int ret, rescan, mmc_dev = -1;
 141         static struct mmc *mmc;
 142
 143         if (IS_ENABLED(CONFIG_K3_BOARD_DETECT))
 144                 do_board_detect();
 145
 146         /*
 147          * Board detection has been done.
 148          * Let us see if another dtb wouldn't be a better match
 149          * for our board
 150          */
 151         if (IS_ENABLED(CONFIG_CPU_V7R)) {
 152                 ret = fdtdec_resetup(&rescan);
 153                 if (!ret && rescan) {
 154                         dm_uninit();
 155                         dm_init_and_scan(true);
 156                 }
 157         }
 158
 159         /*
 160          * Because of multi DTB configuration, the MMC device has
 161          * to be re-initialized after reconfiguring FDT inorder to
 162          * boot from MMC. Do this when boot mode is MMC and ROM has
 163          * not loaded SYSFW.
 164          */
 165         switch (spl_boot_device()) {
 166         case BOOT_DEVICE_MMC1:
 167                 mmc_dev = 0;
 168                 break;
 169         case BOOT_DEVICE_MMC2:
 170         case BOOT_DEVICE_MMC2_2:
 171                 mmc_dev = 1;
 172                 break;
 173         }
 174
 175         if (mmc_dev > 0 && !is_rom_loaded_sysfw(&bootdata)) {
 176                 ret = mmc_init_device(mmc_dev);
 177                 if (!ret) {
 178                         mmc = find_mmc_device(mmc_dev);
 179                         if (mmc) {
 180                                 ret = mmc_init(mmc);
 181                                 if (ret) {
 182                                         printf("mmc init failed with error: %d\n", ret);
 183                                 }
 184                         }
 185                 }
 186         }
 187 }
 188 #endif
 189
 190 void board_init_f(ulong dummy)
 191 {
 192 #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
 193         struct udevice *dev;
 194         int ret;
 195 #endif
 196         /*
 197          * Cannot delay this further as there is a chance that
 198          * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
 199          */
 200         store_boot_info_from_rom();
 201
 202         /* Make all control module registers accessible */
 203         ctrl_mmr_unlock();
 204
 205 #ifdef CONFIG_CPU_V7R
 206         disable_linefill_optimization();
 207         setup_k3_mpu_regions();
 208 #endif
 209
 210         /* Init DM early */
 211         spl_early_init();
 212
 213 #ifdef CONFIG_K3_LOAD_SYSFW
 214         /*
 215          * Process pinctrl for the serial0 a.k.a. MCU_UART0 module and continue
 216          * regardless of the result of pinctrl. Do this without probing the
 217          * device, but instead by searching the device that would request the
 218          * given sequence number if probed. The UART will be used by the system
 219          * firmware (SYSFW) image for various purposes and SYSFW depends on us
 220          * to initialize its pin settings.
 221          */
 222         ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
 223         if (!ret)
 224                 pinctrl_select_state(dev, "default");
 225
 226         /*
 227          * Load, start up, and configure system controller firmware. Provide
 228          * the U-Boot console init function to the SYSFW post-PM configuration
 229          * callback hook, effectively switching on (or over) the console
 230          * output.
 231          */
 232         k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
 233                         k3_mmc_stop_clock, k3_mmc_restart_clock);
 234
 235 #ifdef CONFIG_SPL_OF_LIST
 236         do_dt_magic();
 237 #endif
 238
 239         /*
 240          * Force probe of clk_k3 driver here to ensure basic default clock
 241          * configuration is always done.
 242          */
 243         if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
 244                 ret = uclass_get_device_by_driver(UCLASS_CLK,
 245                                                   DM_DRIVER_GET(ti_clk),
 246                                                   &dev);
 247                 if (ret)
 248                         panic("Failed to initialize clk-k3!\n");
 249         }
 250
 251         /* Prepare console output */
 252         preloader_console_init();
 253
 254         /* Disable ROM configured firewalls right after loading sysfw */
 255         remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
 256         remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls));
 257         remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
 258         remove_fwl_configs(cbass_rc0_fwls, ARRAY_SIZE(cbass_rc0_fwls));
 259         remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
 260         remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
 261         remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
 262 #else
 263         /* Prepare console output */
 264         preloader_console_init();
 265 #endif
 266
 267         /* Output System Firmware version info */
 268         k3_sysfw_print_ver();
 269
 270         if (IS_ENABLED(CONFIG_K3_BOARD_DETECT))
 271                 do_board_detect();
 272
 273 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
 274         ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
 275                                           &dev);
 276         if (ret)
 277                 printf("AVS init failed: %d\n", ret);
 278 #endif
 279
 280 #if defined(CONFIG_K3_J721E_DDRSS)
 281         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 282         if (ret)
 283                 panic("DRAM init failed: %d\n", ret);
 284 #endif
 285         spl_enable_dcache();
 286 }
 287
 288 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
 289 {
 290         switch (boot_device) {
 291         case BOOT_DEVICE_MMC1:
 292                 return MMCSD_MODE_EMMCBOOT;
 293         case BOOT_DEVICE_MMC2:
 294                 return MMCSD_MODE_FS;
 295         default:
 296                 return MMCSD_MODE_RAW;
 297         }
 298 }
 299
 300 static u32 __get_backup_bootmedia(u32 main_devstat)
 301 {
 302         u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
 303                         MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
 304
 305         switch (bkup_boot) {
 306         case BACKUP_BOOT_DEVICE_USB:
 307                 return BOOT_DEVICE_DFU;
 308         case BACKUP_BOOT_DEVICE_UART:
 309                 return BOOT_DEVICE_UART;
 310         case BACKUP_BOOT_DEVICE_ETHERNET:
 311                 return BOOT_DEVICE_ETHERNET;
 312         case BACKUP_BOOT_DEVICE_MMC2:
 313         {
 314                 u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
 315                             MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
 316                 if (port == 0x0)
 317                         return BOOT_DEVICE_MMC1;
 318                 return BOOT_DEVICE_MMC2;
 319         }
 320         case BACKUP_BOOT_DEVICE_SPI:
 321                 return BOOT_DEVICE_SPI;
 322         case BACKUP_BOOT_DEVICE_I2C:
 323                 return BOOT_DEVICE_I2C;
 324         }
 325
 326         return BOOT_DEVICE_RAM;
 327 }
 328
 329 static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
 330 {
 331
 332         u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
 333                         WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
 334
 335         bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
 336                         BOOT_MODE_B_SHIFT;
 337
 338         if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
 339                 bootmode = BOOT_DEVICE_SPI;
 340
 341         if (bootmode == BOOT_DEVICE_MMC2) {
 342                 u32 port = (main_devstat &
 343                             MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
 344                            MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
 345                 if (port == 0x0)
 346                         bootmode = BOOT_DEVICE_MMC1;
 347         }
 348
 349         return bootmode;
 350 }
 351
 352 u32 spl_spi_boot_bus(void)
 353 {
 354         u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
 355         u32 main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 356         u32 bootmode = ((wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
 357                         WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT) |
 358                         ((main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) << BOOT_MODE_B_SHIFT);
 359
 360         return (bootmode == BOOT_DEVICE_QSPI) ? 1 : 0;
 361 }
 362
 363 u32 spl_boot_device(void)
 364 {
 365         u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
 366         u32 main_devstat;
 367
 368         if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
 369                 printf("ERROR: MCU only boot is not yet supported\n");
 370                 return BOOT_DEVICE_RAM;
 371         }
 372
 373         /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
 374         main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
 375
 376         if (bootindex == K3_PRIMARY_BOOTMODE)
 377                 return __get_primary_bootmedia(main_devstat, wkup_devstat);
 378         else
 379                 return __get_backup_bootmedia(main_devstat);
 380 }
 381
 382 #ifdef CONFIG_SYS_K3_SPL_ATF
 383
 384 #define J721E_DEV_MCU_RTI0                      262
 385 #define J721E_DEV_MCU_RTI1                      263
 386 #define J721E_DEV_MCU_ARMSS0_CPU0               250
 387 #define J721E_DEV_MCU_ARMSS0_CPU1               251
 388
 389 void release_resources_for_core_shutdown(void)
 390 {
 391         struct ti_sci_handle *ti_sci;
 392         struct ti_sci_dev_ops *dev_ops;
 393         struct ti_sci_proc_ops *proc_ops;
 394         int ret;
 395         u32 i;
 396
 397         const u32 put_device_ids[] = {
 398                 J721E_DEV_MCU_RTI0,
 399                 J721E_DEV_MCU_RTI1,
 400         };
 401
 402         ti_sci = get_ti_sci_handle();
 403         dev_ops = &ti_sci->ops.dev_ops;
 404         proc_ops = &ti_sci->ops.proc_ops;
 405
 406         /* Iterate through list of devices to put (shutdown) */
 407         for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
 408                 u32 id = put_device_ids[i];
 409
 410                 ret = dev_ops->put_device(ti_sci, id);
 411                 if (ret)
 412                         panic("Failed to put device %u (%d)\n", id, ret);
 413         }
 414
 415         const u32 put_core_ids[] = {
 416                 J721E_DEV_MCU_ARMSS0_CPU1,
 417                 J721E_DEV_MCU_ARMSS0_CPU0,      /* Handle CPU0 after CPU1 */
 418         };
 419
 420         /* Iterate through list of cores to put (shutdown) */
 421         for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
 422                 u32 id = put_core_ids[i];
 423
 424                 /*
 425                  * Queue up the core shutdown request. Note that this call
 426                  * needs to be followed up by an actual invocation of an WFE
 427                  * or WFI CPU instruction.
 428                  */
 429                 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
 430                 if (ret)
 431                         panic("Failed sending core %u shutdown message (%d)\n",
 432                               id, ret);
 433         }
 434 }
 435 #endif