1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * K3: AM62 SoC definitions, structures etc.
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
6 * Suman Anna <s-anna@ti.com>
9 #ifndef __ASM_ARCH_AM62_HARDWARE_H
10 #define __ASM_ARCH_AM62_HARDWARE_H
14 #include <linux/bitops.h>
17 #define PADCFG_MMR0_BASE 0x04080000
18 #define PADCFG_MMR1_BASE 0x000f0000
19 #define CTRL_MMR0_BASE 0x00100000
20 #define MCU_CTRL_MMR0_BASE 0x04500000
21 #define WKUP_CTRL_MMR0_BASE 0x43000000
23 #define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
24 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3)
25 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
26 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7)
27 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7
28 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK GENMASK(12, 10)
29 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
30 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK BIT(13)
31 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
33 /* Primary Bootmode MMC Config macros */
34 #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4
35 #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2
36 #define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK 0x1
37 #define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT 0
39 /* Primary Bootmode USB Config macros */
40 #define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1
41 #define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02
43 /* Backup Bootmode USB Config macros */
44 #define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01
47 * The CTRL_MMR0 memory space is divided into several equally-spaced
48 * partitions, so defining the partition size allows us to determine
49 * register addresses common to those partitions.
51 #define CTRL_MMR0_PARTITION_SIZE 0x4000
54 * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism
55 * shared register definitions. The same registers are also used for
56 * PADCFG_MMR lock/kick-mechanism.
58 #define CTRLMMR_LOCK_KICK0 0x1008
59 #define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
60 #define CTRLMMR_LOCK_KICK1 0x100c
61 #define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
63 #define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038)
64 #define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c)
65 #define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7)
67 #define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058)
68 #define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3)
70 #define ROM_ENTENDED_BOOT_DATA_INFO 0x43c3f1e0
72 /* Use Last 2K as Scratch pad */
73 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x70000000
75 #endif /* __ASM_ARCH_AM62_HARDWARE_H */