1 // SPDX-License-Identifier: GPL-2.0+
3 * K3: Common Architecture initialization
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
15 #include <asm/global_data.h>
18 #include <remoteproc.h>
19 #include <asm/cache.h>
20 #include <linux/soc/ti/ti_sci_protocol.h>
21 #include <fdt_support.h>
22 #include <asm/arch/sys_proto.h>
23 #include <asm/hardware.h>
25 #include <fs_loader.h>
31 struct ti_sci_handle *get_ti_sci_handle(void)
36 ret = uclass_get_device_by_driver(UCLASS_FIRMWARE,
37 DM_DRIVER_GET(ti_sci), &dev);
39 panic("Failed to get SYSFW (%d)\n", ret);
41 return (struct ti_sci_handle *)ti_sci_get_handle_from_sysfw(dev);
44 void k3_sysfw_print_ver(void)
46 struct ti_sci_handle *ti_sci = get_ti_sci_handle();
47 char fw_desc[sizeof(ti_sci->version.firmware_description) + 1];
50 * Output System Firmware version info. Note that since the
51 * 'firmware_description' field is not guaranteed to be zero-
52 * terminated we manually add a \0 terminator if needed. Further
53 * note that we intentionally no longer rely on the extended
54 * printf() formatter '%.*s' to not having to require a more
55 * full-featured printf() implementation.
57 strncpy(fw_desc, ti_sci->version.firmware_description,
58 sizeof(ti_sci->version.firmware_description));
59 fw_desc[sizeof(fw_desc) - 1] = '\0';
61 printf("SYSFW ABI: %d.%d (firmware rev 0x%04x '%s')\n",
62 ti_sci->version.abi_major, ti_sci->version.abi_minor,
63 ti_sci->version.firmware_revision, fw_desc);
66 void mmr_unlock(phys_addr_t base, u32 partition)
68 /* Translate the base address */
69 phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
71 /* Unlock the requested partition if locked using two-step sequence */
72 writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
73 writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
76 bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data)
78 if (strncmp(data->header, K3_ROM_BOOT_HEADER_MAGIC, 7))
81 return data->num_components > 1;
84 DECLARE_GLOBAL_DATA_PTR;
86 #ifdef CONFIG_K3_EARLY_CONS
87 int early_console_init(void)
92 gd->baudrate = CONFIG_BAUDRATE;
94 ret = uclass_get_device_by_seq(UCLASS_SERIAL, CONFIG_K3_EARLY_CONS_IDX,
97 printf("Error getting serial dev for early console! (%d)\n",
102 gd->cur_serial_dev = dev;
103 gd->flags |= GD_FLG_SERIAL_READY;
104 gd->have_console = 1;
110 #ifdef CONFIG_SYS_K3_SPL_ATF
114 #ifdef CONFIG_SPL_ENV_SUPPORT
119 switch (spl_boot_device()) {
120 case BOOT_DEVICE_MMC2:
121 part = env_get("bootpart");
122 env_set("storage_interface", "mmc");
123 env_set("fw_dev_part", part);
125 case BOOT_DEVICE_SPI:
126 env_set("storage_interface", "ubi");
127 env_set("fw_ubi_mtdpart", "UBI");
128 env_set("fw_ubi_volume", "UBI0");
131 printf("%s from device %u not supported!\n",
132 __func__, spl_boot_device());
138 #ifdef CONFIG_FS_LOADER
139 int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
141 struct udevice *fsdev;
146 #ifdef CONFIG_SPL_ENV_SUPPORT
147 switch (spl_boot_device()) {
148 case BOOT_DEVICE_MMC2:
149 name = env_get(name_fw);
150 *loadaddr = env_get_hex(name_loadaddr, *loadaddr);
153 printf("Loading rproc fw image from device %u not supported!\n",
161 if (!uclass_get_device(UCLASS_FS_FIRMWARE_LOADER, 0, &fsdev)) {
162 size = request_firmware_into_buf(fsdev, name, (void *)*loadaddr,
169 int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
175 __weak void start_non_linux_remote_cores(void)
179 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
181 typedef void __noreturn (*image_entry_noargs_t)(void);
182 struct ti_sci_handle *ti_sci = get_ti_sci_handle();
186 /* Release all the exclusive devices held by SPL before starting ATF */
187 ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
191 panic("rproc failed to be initialized (%d)\n", ret);
194 start_non_linux_remote_cores();
195 size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
200 * It is assumed that remoteproc device 1 is the corresponding
201 * Cortex-A core which runs ATF. Make sure DT reflects the same.
203 ret = rproc_load(1, spl_image->entry_point, 0x200);
205 panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
207 /* Add an extra newline to differentiate the ATF logs from SPL */
208 printf("Starting ATF on ARM64 core...\n\n");
210 ret = rproc_start(1);
212 panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
213 if (!(size > 0 && valid_elf_image(loadaddr))) {
214 debug("Shutting down...\n");
215 release_resources_for_core_shutdown();
221 image_entry_noargs_t image_entry =
222 (image_entry_noargs_t)load_elf_image_phdr(loadaddr);
228 #if defined(CONFIG_OF_LIBFDT)
229 int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
231 u64 msmc_start = 0, msmc_end = 0, msmc_size, reg[2];
232 struct ti_sci_handle *ti_sci = get_ti_sci_handle();
233 int ret, node, subnode, len, prev_node;
234 u32 range[4], addr, size;
235 const fdt32_t *sub_reg;
237 ti_sci->ops.core_ops.query_msmc(ti_sci, &msmc_start, &msmc_end);
238 msmc_size = msmc_end - msmc_start + 1;
239 debug("%s: msmc_start = 0x%llx, msmc_size = 0x%llx\n", __func__,
240 msmc_start, msmc_size);
242 /* find or create "msmc_sram node */
243 ret = fdt_path_offset(blob, parent_path);
247 node = fdt_find_or_add_subnode(blob, ret, node_name);
251 ret = fdt_setprop_string(blob, node, "compatible", "mmio-sram");
255 reg[0] = cpu_to_fdt64(msmc_start);
256 reg[1] = cpu_to_fdt64(msmc_size);
257 ret = fdt_setprop(blob, node, "reg", reg, sizeof(reg));
261 fdt_setprop_cell(blob, node, "#address-cells", 1);
262 fdt_setprop_cell(blob, node, "#size-cells", 1);
265 range[1] = cpu_to_fdt32(msmc_start >> 32);
266 range[2] = cpu_to_fdt32(msmc_start & 0xffffffff);
267 range[3] = cpu_to_fdt32(msmc_size);
268 ret = fdt_setprop(blob, node, "ranges", range, sizeof(range));
272 subnode = fdt_first_subnode(blob, node);
275 /* Look for invalid subnodes and delete them */
276 while (subnode >= 0) {
277 sub_reg = fdt_getprop(blob, subnode, "reg", &len);
278 addr = fdt_read_number(sub_reg, 1);
280 size = fdt_read_number(sub_reg, 1);
281 debug("%s: subnode = %d, addr = 0x%x. size = 0x%x\n", __func__,
282 subnode, addr, size);
283 if (addr + size > msmc_size ||
284 !strncmp(fdt_get_name(blob, subnode, &len), "sysfw", 5) ||
285 !strncmp(fdt_get_name(blob, subnode, &len), "l3cache", 7)) {
286 fdt_del_node(blob, subnode);
287 debug("%s: deleting subnode %d\n", __func__, subnode);
289 subnode = fdt_first_subnode(blob, node);
291 subnode = fdt_next_subnode(blob, prev_node);
294 subnode = fdt_next_subnode(blob, prev_node);
301 int fdt_disable_node(void *blob, char *node_path)
306 offs = fdt_path_offset(blob, node_path);
308 printf("Node %s not found.\n", node_path);
311 ret = fdt_setprop_string(blob, offs, "status", "disabled");
313 printf("Could not add status property to node %s: %s\n",
314 node_path, fdt_strerror(ret));
322 #ifndef CONFIG_SYSRESET
323 void reset_cpu(ulong ignored)
328 #if defined(CONFIG_DISPLAY_CPUINFO)
329 int print_cpuinfo(void)
343 ret = soc_get_family(soc, name, 64);
348 ret = soc_get_revision(soc, name, 64);
350 printf("%s\n", name);
357 bool soc_is_j721e(void)
361 soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
362 JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
367 bool soc_is_j7200(void)
371 soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
372 JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
378 void board_prep_linux(bootm_headers_t *images)
380 debug("Linux kernel Image start = 0x%lx end = 0x%lx\n",
381 images->os.start, images->os.end);
382 __asm_flush_dcache_range(images->os.start,
383 ROUND(images->os.end,
384 CONFIG_SYS_CACHELINE_SIZE));
388 #ifdef CONFIG_CPU_V7R
389 void disable_linefill_optimization(void)
394 * On K3 devices there are 2 conditions where R5F can deadlock:
395 * 1.When software is performing series of store operations to
396 * cacheable write back/write allocate memory region and later
397 * on software execute barrier operation (DSB or DMB). R5F may
398 * hang at the barrier instruction.
399 * 2.When software is performing a mix of load and store operations
400 * within a tight loop and store operations are all writing to
401 * cacheable write back/write allocates memory regions, R5F may
402 * hang at one of the load instruction.
404 * To avoid the above two conditions disable linefill optimization
407 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
408 actlr |= (1 << 13); /* Set DLFO bit */
409 asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
413 void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
415 struct ti_sci_msg_fwl_region region;
416 struct ti_sci_fwl_ops *fwl_ops;
417 struct ti_sci_handle *ti_sci;
420 ti_sci = get_ti_sci_handle();
421 fwl_ops = &ti_sci->ops.fwl_ops;
422 for (i = 0; i < fwl_data_size; i++) {
423 for (j = 0; j < fwl_data[i].regions; j++) {
424 region.fwl_id = fwl_data[i].fwl_id;
426 region.n_permission_regs = 3;
428 fwl_ops->get_fwl_region(ti_sci, ®ion);
430 if (region.control != 0) {
431 pr_debug("Attempting to disable firewall %5d (%25s)\n",
432 region.fwl_id, fwl_data[i].name);
435 if (fwl_ops->set_fwl_region(ti_sci, ®ion))
436 pr_err("Could not disable firewall %5d (%25s)\n",
437 region.fwl_id, fwl_data[i].name);
443 void spl_enable_dcache(void)
445 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
446 phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
448 dram_init_banksize();
450 /* reserve TLB table */
451 gd->arch.tlb_size = PGTABLE_SIZE;
453 ram_top += get_effective_memsize();
454 /* keep ram_top in the 32-bit address space */
455 if (ram_top >= 0x100000000)
456 ram_top = (phys_addr_t) 0x100000000;
458 gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
459 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
460 gd->arch.tlb_addr + gd->arch.tlb_size);
466 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
467 void spl_board_prepare_for_boot(void)
472 void spl_board_prepare_for_linux(void)