arch/arm/mach-k3/common.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * K3: Common Architecture initialization
   4  *
   5  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
   6  *      Lokesh Vutla <lokeshvutla@ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <image.h>
  12 #include <init.h>
  13 #include <log.h>
  14 #include <spl.h>
  15 #include <asm/global_data.h>
  16 #include "common.h"
  17 #include <dm.h>
  18 #include <remoteproc.h>
  19 #include <asm/cache.h>
  20 #include <linux/soc/ti/ti_sci_protocol.h>
  21 #include <fdt_support.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/hardware.h>
  24 #include <asm/io.h>
  25 #include <fs_loader.h>
  26 #include <fs.h>
  27 #include <env.h>
  28 #include <elf.h>
  29 #include <soc.h>
  30
  31 #if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
  32 enum {
  33         IMAGE_ID_ATF,
  34         IMAGE_ID_OPTEE,
  35         IMAGE_ID_SPL,
  36         IMAGE_ID_DM_FW,
  37         IMAGE_AMT,
  38 };
  39
  40 #if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
  41 static const char *image_os_match[IMAGE_AMT] = {
  42         "arm-trusted-firmware",
  43         "tee",
  44         "U-Boot",
  45         "DM",
  46 };
  47 #endif
  48
  49 static struct image_info fit_image_info[IMAGE_AMT];
  50 #endif
  51
  52 struct ti_sci_handle *get_ti_sci_handle(void)
  53 {
  54         struct udevice *dev;
  55         int ret;
  56
  57         ret = uclass_get_device_by_driver(UCLASS_FIRMWARE,
  58                                           DM_DRIVER_GET(ti_sci), &dev);
  59         if (ret)
  60                 panic("Failed to get SYSFW (%d)\n", ret);
  61
  62         return (struct ti_sci_handle *)ti_sci_get_handle_from_sysfw(dev);
  63 }
  64
  65 void k3_sysfw_print_ver(void)
  66 {
  67         struct ti_sci_handle *ti_sci = get_ti_sci_handle();
  68         char fw_desc[sizeof(ti_sci->version.firmware_description) + 1];
  69
  70         /*
  71          * Output System Firmware version info. Note that since the
  72          * 'firmware_description' field is not guaranteed to be zero-
  73          * terminated we manually add a \0 terminator if needed. Further
  74          * note that we intentionally no longer rely on the extended
  75          * printf() formatter '%.*s' to not having to require a more
  76          * full-featured printf() implementation.
  77          */
  78         strncpy(fw_desc, ti_sci->version.firmware_description,
  79                 sizeof(ti_sci->version.firmware_description));
  80         fw_desc[sizeof(fw_desc) - 1] = '\0';
  81
  82         printf("SYSFW ABI: %d.%d (firmware rev 0x%04x '%s')\n",
  83                ti_sci->version.abi_major, ti_sci->version.abi_minor,
  84                ti_sci->version.firmware_revision, fw_desc);
  85 }
  86
  87 void mmr_unlock(phys_addr_t base, u32 partition)
  88 {
  89         /* Translate the base address */
  90         phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
  91
  92         /* Unlock the requested partition if locked using two-step sequence */
  93         writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
  94         writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
  95 }
  96
  97 bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data)
  98 {
  99         if (strncmp(data->header, K3_ROM_BOOT_HEADER_MAGIC, 7))
 100                 return false;
 101
 102         return data->num_components > 1;
 103 }
 104
 105 DECLARE_GLOBAL_DATA_PTR;
 106
 107 #ifdef CONFIG_K3_EARLY_CONS
 108 int early_console_init(void)
 109 {
 110         struct udevice *dev;
 111         int ret;
 112
 113         gd->baudrate = CONFIG_BAUDRATE;
 114
 115         ret = uclass_get_device_by_seq(UCLASS_SERIAL, CONFIG_K3_EARLY_CONS_IDX,
 116                                        &dev);
 117         if (ret) {
 118                 printf("Error getting serial dev for early console! (%d)\n",
 119                        ret);
 120                 return ret;
 121         }
 122
 123         gd->cur_serial_dev = dev;
 124         gd->flags |= GD_FLG_SERIAL_READY;
 125         gd->have_console = 1;
 126
 127         return 0;
 128 }
 129 #endif
 130
 131 #if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
 132
 133 void init_env(void)
 134 {
 135 #ifdef CONFIG_SPL_ENV_SUPPORT
 136         char *part;
 137
 138         env_init();
 139         env_relocate();
 140         switch (spl_boot_device()) {
 141         case BOOT_DEVICE_MMC2:
 142                 part = env_get("bootpart");
 143                 env_set("storage_interface", "mmc");
 144                 env_set("fw_dev_part", part);
 145                 break;
 146         case BOOT_DEVICE_SPI:
 147                 env_set("storage_interface", "ubi");
 148                 env_set("fw_ubi_mtdpart", "UBI");
 149                 env_set("fw_ubi_volume", "UBI0");
 150                 break;
 151         default:
 152                 printf("%s from device %u not supported!\n",
 153                        __func__, spl_boot_device());
 154                 return;
 155         }
 156 #endif
 157 }
 158
 159 int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
 160 {
 161         struct udevice *fsdev;
 162         char *name = NULL;
 163         int size = 0;
 164
 165         if (!IS_ENABLED(CONFIG_FS_LOADER))
 166                 return 0;
 167
 168         *loadaddr = 0;
 169 #ifdef CONFIG_SPL_ENV_SUPPORT
 170         switch (spl_boot_device()) {
 171         case BOOT_DEVICE_MMC2:
 172                 name = env_get(name_fw);
 173                 *loadaddr = env_get_hex(name_loadaddr, *loadaddr);
 174                 break;
 175         default:
 176                 printf("Loading rproc fw image from device %u not supported!\n",
 177                        spl_boot_device());
 178                 return 0;
 179         }
 180 #endif
 181         if (!*loadaddr)
 182                 return 0;
 183
 184         if (!uclass_get_device(UCLASS_FS_FIRMWARE_LOADER, 0, &fsdev)) {
 185                 size = request_firmware_into_buf(fsdev, name, (void *)*loadaddr,
 186                                                  0, 0);
 187         }
 188
 189         return size;
 190 }
 191
 192 __weak void release_resources_for_core_shutdown(void)
 193 {
 194         debug("%s not implemented...\n", __func__);
 195 }
 196
 197 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 198 {
 199         typedef void __noreturn (*image_entry_noargs_t)(void);
 200         struct ti_sci_handle *ti_sci = get_ti_sci_handle();
 201         u32 loadaddr = 0;
 202         int ret, size = 0, shut_cpu = 0;
 203
 204         /* Release all the exclusive devices held by SPL before starting ATF */
 205         ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
 206
 207         ret = rproc_init();
 208         if (ret)
 209                 panic("rproc failed to be initialized (%d)\n", ret);
 210
 211         init_env();
 212
 213         if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
 214                 size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
 215                                      &loadaddr);
 216         }
 217
 218         /*
 219          * It is assumed that remoteproc device 1 is the corresponding
 220          * Cortex-A core which runs ATF. Make sure DT reflects the same.
 221          */
 222         if (!fit_image_info[IMAGE_ID_ATF].image_start)
 223                 fit_image_info[IMAGE_ID_ATF].image_start =
 224                         spl_image->entry_point;
 225
 226         ret = rproc_load(1, fit_image_info[IMAGE_ID_ATF].image_start, 0x200);
 227         if (ret)
 228                 panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
 229
 230         if (!fit_image_info[IMAGE_ID_DM_FW].image_len &&
 231             !(size > 0 && valid_elf_image(loadaddr))) {
 232                 shut_cpu = 1;
 233                 goto start_arm64;
 234         }
 235
 236         if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
 237                 loadaddr = load_elf_image_phdr(loadaddr);
 238         } else {
 239                 loadaddr = fit_image_info[IMAGE_ID_DM_FW].image_start;
 240                 if (valid_elf_image(loadaddr))
 241                         loadaddr = load_elf_image_phdr(loadaddr);
 242         }
 243
 244         debug("%s: jumping to address %x\n", __func__, loadaddr);
 245
 246 start_arm64:
 247         /* Add an extra newline to differentiate the ATF logs from SPL */
 248         printf("Starting ATF on ARM64 core...\n\n");
 249
 250         ret = rproc_start(1);
 251         if (ret)
 252                 panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
 253
 254         if (shut_cpu) {
 255                 debug("Shutting down...\n");
 256                 release_resources_for_core_shutdown();
 257
 258                 while (1)
 259                         asm volatile("wfe");
 260         }
 261         image_entry_noargs_t image_entry = (image_entry_noargs_t)loadaddr;
 262
 263         image_entry();
 264 }
 265 #endif
 266
 267 #if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
 268 void board_fit_image_post_process(const void *fit, int node, void **p_image,
 269                                   size_t *p_size)
 270 {
 271 #if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
 272         int len;
 273         int i;
 274         const char *os;
 275         u32 addr;
 276
 277         os = fdt_getprop(fit, node, "os", &len);
 278         addr = fdt_getprop_u32_default_node(fit, node, 0, "entry", -1);
 279
 280         debug("%s: processing image: addr=%x, size=%d, os=%s\n", __func__,
 281               addr, *p_size, os);
 282
 283         for (i = 0; i < IMAGE_AMT; i++) {
 284                 if (!strcmp(os, image_os_match[i])) {
 285                         fit_image_info[i].image_start = addr;
 286                         fit_image_info[i].image_len = *p_size;
 287                         debug("%s: matched image for ID %d\n", __func__, i);
 288                         break;
 289                 }
 290         }
 291 #endif
 292
 293 #if IS_ENABLED(CONFIG_TI_SECURE_DEVICE)
 294         ti_secure_image_post_process(p_image, p_size);
 295 #endif
 296 }
 297 #endif
 298
 299 #if defined(CONFIG_OF_LIBFDT)
 300 int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
 301 {
 302         u64 msmc_start = 0, msmc_end = 0, msmc_size, reg[2];
 303         struct ti_sci_handle *ti_sci = get_ti_sci_handle();
 304         int ret, node, subnode, len, prev_node;
 305         u32 range[4], addr, size;
 306         const fdt32_t *sub_reg;
 307
 308         ti_sci->ops.core_ops.query_msmc(ti_sci, &msmc_start, &msmc_end);
 309         msmc_size = msmc_end - msmc_start + 1;
 310         debug("%s: msmc_start = 0x%llx, msmc_size = 0x%llx\n", __func__,
 311               msmc_start, msmc_size);
 312
 313         /* find or create "msmc_sram node */
 314         ret = fdt_path_offset(blob, parent_path);
 315         if (ret < 0)
 316                 return ret;
 317
 318         node = fdt_find_or_add_subnode(blob, ret, node_name);
 319         if (node < 0)
 320                 return node;
 321
 322         ret = fdt_setprop_string(blob, node, "compatible", "mmio-sram");
 323         if (ret < 0)
 324                 return ret;
 325
 326         reg[0] = cpu_to_fdt64(msmc_start);
 327         reg[1] = cpu_to_fdt64(msmc_size);
 328         ret = fdt_setprop(blob, node, "reg", reg, sizeof(reg));
 329         if (ret < 0)
 330                 return ret;
 331
 332         fdt_setprop_cell(blob, node, "#address-cells", 1);
 333         fdt_setprop_cell(blob, node, "#size-cells", 1);
 334
 335         range[0] = 0;
 336         range[1] = cpu_to_fdt32(msmc_start >> 32);
 337         range[2] = cpu_to_fdt32(msmc_start & 0xffffffff);
 338         range[3] = cpu_to_fdt32(msmc_size);
 339         ret = fdt_setprop(blob, node, "ranges", range, sizeof(range));
 340         if (ret < 0)
 341                 return ret;
 342
 343         subnode = fdt_first_subnode(blob, node);
 344         prev_node = 0;
 345
 346         /* Look for invalid subnodes and delete them */
 347         while (subnode >= 0) {
 348                 sub_reg = fdt_getprop(blob, subnode, "reg", &len);
 349                 addr = fdt_read_number(sub_reg, 1);
 350                 sub_reg++;
 351                 size = fdt_read_number(sub_reg, 1);
 352                 debug("%s: subnode = %d, addr = 0x%x. size = 0x%x\n", __func__,
 353                       subnode, addr, size);
 354                 if (addr + size > msmc_size ||
 355                     !strncmp(fdt_get_name(blob, subnode, &len), "sysfw", 5) ||
 356                     !strncmp(fdt_get_name(blob, subnode, &len), "l3cache", 7)) {
 357                         fdt_del_node(blob, subnode);
 358                         debug("%s: deleting subnode %d\n", __func__, subnode);
 359                         if (!prev_node)
 360                                 subnode = fdt_first_subnode(blob, node);
 361                         else
 362                                 subnode = fdt_next_subnode(blob, prev_node);
 363                 } else {
 364                         prev_node = subnode;
 365                         subnode = fdt_next_subnode(blob, prev_node);
 366                 }
 367         }
 368
 369         return 0;
 370 }
 371
 372 int fdt_disable_node(void *blob, char *node_path)
 373 {
 374         int offs;
 375         int ret;
 376
 377         offs = fdt_path_offset(blob, node_path);
 378         if (offs < 0) {
 379                 printf("Node %s not found.\n", node_path);
 380                 return offs;
 381         }
 382         ret = fdt_setprop_string(blob, offs, "status", "disabled");
 383         if (ret < 0) {
 384                 printf("Could not add status property to node %s: %s\n",
 385                        node_path, fdt_strerror(ret));
 386                 return ret;
 387         }
 388         return 0;
 389 }
 390
 391 #endif
 392
 393 #ifndef CONFIG_SYSRESET
 394 void reset_cpu(void)
 395 {
 396 }
 397 #endif
 398
 399 #if defined(CONFIG_DISPLAY_CPUINFO)
 400 int print_cpuinfo(void)
 401 {
 402         struct udevice *soc;
 403         char name[64];
 404         int ret;
 405
 406         printf("SoC:   ");
 407
 408         ret = soc_get(&soc);
 409         if (ret) {
 410                 printf("UNKNOWN\n");
 411                 return 0;
 412         }
 413
 414         ret = soc_get_family(soc, name, 64);
 415         if (!ret) {
 416                 printf("%s ", name);
 417         }
 418
 419         ret = soc_get_revision(soc, name, 64);
 420         if (!ret) {
 421                 printf("%s\n", name);
 422         }
 423
 424         return 0;
 425 }
 426 #endif
 427
 428 bool soc_is_j721e(void)
 429 {
 430         u32 soc;
 431
 432         soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
 433                 JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
 434
 435         return soc == J721E;
 436 }
 437
 438 bool soc_is_j7200(void)
 439 {
 440         u32 soc;
 441
 442         soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
 443                 JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
 444
 445         return soc == J7200;
 446 }
 447
 448 #ifdef CONFIG_ARM64
 449 void board_prep_linux(bootm_headers_t *images)
 450 {
 451         debug("Linux kernel Image start = 0x%lx end = 0x%lx\n",
 452               images->os.start, images->os.end);
 453         __asm_flush_dcache_range(images->os.start,
 454                                  ROUND(images->os.end,
 455                                        CONFIG_SYS_CACHELINE_SIZE));
 456 }
 457 #endif
 458
 459 #ifdef CONFIG_CPU_V7R
 460 void disable_linefill_optimization(void)
 461 {
 462         u32 actlr;
 463
 464         /*
 465          * On K3 devices there are 2 conditions where R5F can deadlock:
 466          * 1.When software is performing series of store operations to
 467          *   cacheable write back/write allocate memory region and later
 468          *   on software execute barrier operation (DSB or DMB). R5F may
 469          *   hang at the barrier instruction.
 470          * 2.When software is performing a mix of load and store operations
 471          *   within a tight loop and store operations are all writing to
 472          *   cacheable write back/write allocates memory regions, R5F may
 473          *   hang at one of the load instruction.
 474          *
 475          * To avoid the above two conditions disable linefill optimization
 476          * inside Cortex R5F.
 477          */
 478         asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
 479         actlr |= (1 << 13); /* Set DLFO bit  */
 480         asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
 481 }
 482 #endif
 483
 484 void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
 485 {
 486         struct ti_sci_msg_fwl_region region;
 487         struct ti_sci_fwl_ops *fwl_ops;
 488         struct ti_sci_handle *ti_sci;
 489         size_t i, j;
 490
 491         ti_sci = get_ti_sci_handle();
 492         fwl_ops = &ti_sci->ops.fwl_ops;
 493         for (i = 0; i < fwl_data_size; i++) {
 494                 for (j = 0; j <  fwl_data[i].regions; j++) {
 495                         region.fwl_id = fwl_data[i].fwl_id;
 496                         region.region = j;
 497                         region.n_permission_regs = 3;
 498
 499                         fwl_ops->get_fwl_region(ti_sci, &region);
 500
 501                         if (region.control != 0) {
 502                                 pr_debug("Attempting to disable firewall %5d (%25s)\n",
 503                                          region.fwl_id, fwl_data[i].name);
 504                                 region.control = 0;
 505
 506                                 if (fwl_ops->set_fwl_region(ti_sci, &region))
 507                                         pr_err("Could not disable firewall %5d (%25s)\n",
 508                                                region.fwl_id, fwl_data[i].name);
 509                         }
 510                 }
 511         }
 512 }
 513
 514 void spl_enable_dcache(void)
 515 {
 516 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 517         phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
 518
 519         dram_init();
 520
 521         /* reserve TLB table */
 522         gd->arch.tlb_size = PGTABLE_SIZE;
 523
 524         ram_top += get_effective_memsize();
 525         /* keep ram_top in the 32-bit address space */
 526         if (ram_top >= 0x100000000)
 527                 ram_top = (phys_addr_t) 0x100000000;
 528
 529         gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
 530         debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
 531               gd->arch.tlb_addr + gd->arch.tlb_size);
 532
 533         dcache_enable();
 534 #endif
 535 }
 536
 537 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 538 void spl_board_prepare_for_boot(void)
 539 {
 540         dcache_disable();
 541 }
 542
 543 void spl_board_prepare_for_linux(void)
 544 {
 545         dcache_disable();
 546 }
 547 #endif
 548
 549 int misc_init_r(void)
 550 {
 551         if (IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS)) {
 552                 struct udevice *dev;
 553                 int ret;
 554
 555                 ret = uclass_get_device_by_driver(UCLASS_MISC,
 556                                                   DM_DRIVER_GET(am65_cpsw_nuss),
 557                                                   &dev);
 558                 if (ret)
 559                         printf("Failed to probe am65_cpsw_nuss driver\n");
 560         }
 561
 562         return 0;
 563 }