1 // SPDX-License-Identifier: GPL-2.0+
3 * AM6: SoC specific initialization
5 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
10 #include <fdt_support.h>
12 #include <asm/global_data.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/sysfw-loader.h>
17 #include <asm/arch/sys_proto.h>
20 #include <dm/uclass-internal.h>
21 #include <dm/pinctrl.h>
22 #include <linux/soc/ti/ti_sci_protocol.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #ifdef CONFIG_K3_LOAD_SYSFW
30 struct fwl_data main_cbass_fwls[] = {
31 { "MMCSD1_CFG", 2057, 1 },
32 { "MMCSD0_CFG", 2058, 1 },
33 { "USB3SS0_SLV0", 2176, 2 },
34 { "PCIE0_SLV", 2336, 8 },
35 { "PCIE1_SLV", 2337, 8 },
36 { "PCIE0_CFG", 2688, 1 },
37 { "PCIE1_CFG", 2689, 1 },
38 }, mcu_cbass_fwls[] = {
39 { "MCU_ARMSS0_CORE0_SLV", 1024, 1 },
40 { "MCU_ARMSS0_CORE1_SLV", 1028, 1 },
41 { "MCU_FSS0_S1", 1033, 8 },
42 { "MCU_FSS0_S0", 1036, 8 },
43 { "MCU_CPSW0", 1220, 1 },
47 static void ctrl_mmr_unlock(void)
49 /* Unlock all WKUP_CTRL_MMR0 module registers */
50 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
51 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
52 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
53 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
54 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
55 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
57 /* Unlock all MCU_CTRL_MMR0 module registers */
58 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
59 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
60 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
61 mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
63 /* Unlock all CTRL_MMR0 module registers */
64 mmr_unlock(CTRL_MMR0_BASE, 0);
65 mmr_unlock(CTRL_MMR0_BASE, 1);
66 mmr_unlock(CTRL_MMR0_BASE, 2);
67 mmr_unlock(CTRL_MMR0_BASE, 3);
68 mmr_unlock(CTRL_MMR0_BASE, 6);
69 mmr_unlock(CTRL_MMR0_BASE, 7);
73 * This uninitialized global variable would normal end up in the .bss section,
74 * but the .bss is cleared between writing and reading this variable, so move
75 * it to the .data section.
77 u32 bootindex __section(".data");
79 static void store_boot_index_from_rom(void)
81 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
84 #if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
85 void k3_mmc_stop_clock(void)
87 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
88 struct mmc *mmc = find_mmc_device(0);
93 mmc->saved_clock = mmc->clock;
94 mmc_set_clock(mmc, 0, true);
98 void k3_mmc_restart_clock(void)
100 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
101 struct mmc *mmc = find_mmc_device(0);
106 mmc_set_clock(mmc, mmc->saved_clock, false);
110 void k3_mmc_stop_clock(void) {}
111 void k3_mmc_restart_clock(void) {}
113 #if CONFIG_IS_ENABLED(DFU) || CONFIG_IS_ENABLED(USB_STORAGE)
114 #define CTRLMMR_SERDES0_CTRL 0x00104080
115 #define PCIE_LANE0 0x1
116 static int fixup_usb_boot(void)
120 switch (spl_boot_device()) {
121 case BOOT_DEVICE_USB:
123 * If bootmode is Host bootmode, fixup the dr_mode to host
124 * before the dwc3 bind takes place
126 ret = fdt_find_and_setprop((void *)gd->fdt_blob,
127 "/bus@100000/dwc3@4000000/usb@10000",
128 "dr_mode", "host", 5, 0);
130 printf("%s: fdt_find_and_setprop() failed:%d\n", __func__,
133 case BOOT_DEVICE_DFU:
135 * The serdes mux between PCIe and USB3 needs to be set to PCIe for
136 * accessing the interface at USB 2.0
138 writel(PCIE_LANE0, CTRLMMR_SERDES0_CTRL);
146 int fdtdec_board_setup(const void *fdt_blob)
148 return fixup_usb_boot();
152 static void setup_am654_navss_northbridge(void)
155 * NB0 is bridge to SRAM and NB1 is bridge to DDR.
156 * To ensure that SRAM transfers are not stalled due to
157 * delays during DDR refreshes, SRAM traffic should be higher
158 * priority (threadmap=2) than DDR traffic (threadmap=0).
160 writel(0x2, NAVSS0_NBSS_NB0_CFG_BASE + NAVSS_NBSS_THREADMAP);
161 writel(0x0, NAVSS0_NBSS_NB1_CFG_BASE + NAVSS_NBSS_THREADMAP);
164 void board_init_f(ulong dummy)
166 #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
173 * Cannot delay this further as there is a chance that
174 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
176 store_boot_index_from_rom();
178 /* Make all control module registers accessible */
181 setup_am654_navss_northbridge();
183 #ifdef CONFIG_CPU_V7R
184 disable_linefill_optimization();
185 setup_k3_mpu_regions();
188 /* Init DM early in-order to invoke system controller */
191 #ifdef CONFIG_K3_EARLY_CONS
193 * Allow establishing an early console as required for example when
194 * doing a UART-based boot. Note that this console may not "survive"
195 * through a SYSFW PM-init step and will need a re-init in some way
196 * due to changing module clock frequencies.
198 early_console_init();
201 #ifdef CONFIG_K3_LOAD_SYSFW
203 * Initialize an early full malloc environment. Do so by allocating a
204 * new malloc area inside the currently active pre-relocation "first"
205 * malloc pool of which we use all that's left.
207 pool_size = CONFIG_VAL(SYS_MALLOC_F_LEN) - gd->malloc_ptr;
208 pool_addr = malloc(pool_size);
210 panic("ERROR: Can't allocate full malloc pool!\n");
212 mem_malloc_init((ulong)pool_addr, (ulong)pool_size);
213 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
214 debug("%s: initialized an early full malloc pool at 0x%08lx of 0x%lx bytes\n",
215 __func__, (unsigned long)pool_addr, (unsigned long)pool_size);
217 * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
218 * regardless of the result of pinctrl. Do this without probing the
219 * device, but instead by searching the device that would request the
220 * given sequence number if probed. The UART will be used by the system
221 * firmware (SYSFW) image for various purposes and SYSFW depends on us
222 * to initialize its pin settings.
224 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
226 pinctrl_select_state(dev, "default");
229 * Load, start up, and configure system controller firmware while
230 * also populating the SYSFW post-PM configuration callback hook.
232 k3_sysfw_loader(false, k3_mmc_stop_clock, k3_mmc_restart_clock);
234 /* Prepare console output */
235 preloader_console_init();
237 /* Disable ROM configured firewalls right after loading sysfw */
238 remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls));
239 remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls));
241 /* Prepare console output */
242 preloader_console_init();
245 /* Output System Firmware version info */
246 k3_sysfw_print_ver();
248 if (IS_ENABLED(CONFIG_K3_BOARD_DETECT))
251 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
252 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
255 printf("AVS init failed: %d\n", ret);
258 #ifdef CONFIG_K3_AM654_DDRSS
259 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
261 panic("DRAM init failed: %d\n", ret);
266 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
268 #if defined(CONFIG_SUPPORT_EMMC_BOOT)
269 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
271 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
272 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
274 /* eMMC boot0 mode is only supported for primary boot */
275 if (bootindex == K3_PRIMARY_BOOTMODE &&
276 bootmode == BOOT_DEVICE_MMC1)
277 return MMCSD_MODE_EMMCBOOT;
280 /* Everything else use filesystem if available */
281 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
282 return MMCSD_MODE_FS;
284 return MMCSD_MODE_RAW;
288 static u32 __get_backup_bootmedia(u32 devstat)
290 u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
291 CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
294 case BACKUP_BOOT_DEVICE_USB:
295 return BOOT_DEVICE_USB;
296 case BACKUP_BOOT_DEVICE_UART:
297 return BOOT_DEVICE_UART;
298 case BACKUP_BOOT_DEVICE_ETHERNET:
299 return BOOT_DEVICE_ETHERNET;
300 case BACKUP_BOOT_DEVICE_MMC2:
302 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
303 CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
305 return BOOT_DEVICE_MMC1;
306 return BOOT_DEVICE_MMC2;
308 case BACKUP_BOOT_DEVICE_SPI:
309 return BOOT_DEVICE_SPI;
310 case BACKUP_BOOT_DEVICE_HYPERFLASH:
311 return BOOT_DEVICE_HYPERFLASH;
312 case BACKUP_BOOT_DEVICE_I2C:
313 return BOOT_DEVICE_I2C;
316 return BOOT_DEVICE_RAM;
319 static u32 __get_primary_bootmedia(u32 devstat)
321 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
322 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
324 if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
325 bootmode = BOOT_DEVICE_SPI;
327 if (bootmode == BOOT_DEVICE_MMC2) {
328 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
329 CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
331 bootmode = BOOT_DEVICE_MMC1;
332 } else if (bootmode == BOOT_DEVICE_MMC1) {
333 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
334 CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
336 bootmode = BOOT_DEVICE_MMC2;
337 } else if (bootmode == BOOT_DEVICE_DFU) {
338 u32 mode = (devstat & CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK) >>
339 CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT;
341 bootmode = BOOT_DEVICE_USB;
347 u32 spl_boot_device(void)
349 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
351 if (bootindex == K3_PRIMARY_BOOTMODE)
352 return __get_primary_bootmedia(devstat);
354 return __get_backup_bootmedia(devstat);
357 #ifdef CONFIG_SYS_K3_SPL_ATF
359 #define AM6_DEV_MCU_RTI0 134
360 #define AM6_DEV_MCU_RTI1 135
361 #define AM6_DEV_MCU_ARMSS0_CPU0 159
362 #define AM6_DEV_MCU_ARMSS0_CPU1 245
364 void release_resources_for_core_shutdown(void)
366 struct ti_sci_handle *ti_sci = get_ti_sci_handle();
367 struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
368 struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
372 const u32 put_device_ids[] = {
377 /* Iterate through list of devices to put (shutdown) */
378 for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
379 u32 id = put_device_ids[i];
381 ret = dev_ops->put_device(ti_sci, id);
383 panic("Failed to put device %u (%d)\n", id, ret);
386 const u32 put_core_ids[] = {
387 AM6_DEV_MCU_ARMSS0_CPU1,
388 AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
391 /* Iterate through list of cores to put (shutdown) */
392 for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
393 u32 id = put_core_ids[i];
396 * Queue up the core shutdown request. Note that this call
397 * needs to be followed up by an actual invocation of an WFE
398 * or WFI CPU instruction.
400 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
402 panic("Failed sending core %u shutdown message (%d)\n",