1 // SPDX-License-Identifier: GPL-2.0
3 * AM642: SoC specific initialization
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 * Keerthy <j-keerthy@ti.com>
7 * Dave Gerlach <d-gerlach@ti.com>
11 #include <fdt_support.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sysfw-loader.h>
16 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/sys_proto.h>
19 #include <linux/soc/ti/ti_sci_protocol.h>
21 #include <dm/uclass-internal.h>
22 #include <dm/pinctrl.h>
26 #define CTRLMMR_MCU_RST_CTRL 0x04518170
28 static void ctrl_mmr_unlock(void)
30 /* Unlock all PADCFG_MMR1 module registers */
31 mmr_unlock(PADCFG_MMR1_BASE, 1);
33 /* Unlock all MCU_CTRL_MMR0 module registers */
34 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
35 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
36 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
37 mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
38 mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
39 mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
41 /* Unlock all CTRL_MMR0 module registers */
42 mmr_unlock(CTRL_MMR0_BASE, 0);
43 mmr_unlock(CTRL_MMR0_BASE, 1);
44 mmr_unlock(CTRL_MMR0_BASE, 2);
45 mmr_unlock(CTRL_MMR0_BASE, 3);
46 mmr_unlock(CTRL_MMR0_BASE, 5);
47 mmr_unlock(CTRL_MMR0_BASE, 6);
49 /* Unlock all MCU_PADCFG_MMR1 module registers */
50 mmr_unlock(MCU_PADCFG_MMR1_BASE, 1);
54 * This uninitialized global variable would normal end up in the .bss section,
55 * but the .bss is cleared between writing and reading this variable, so move
56 * it to the .data section.
58 u32 bootindex __section(".data");
59 static struct rom_extended_boot_data bootdata __section(".data");
61 static void store_boot_info_from_rom(void)
63 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
64 memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
65 sizeof(struct rom_extended_boot_data));
68 #if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
69 void k3_mmc_stop_clock(void)
71 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
72 struct mmc *mmc = find_mmc_device(0);
77 mmc->saved_clock = mmc->clock;
78 mmc_set_clock(mmc, 0, true);
82 void k3_mmc_restart_clock(void)
84 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
85 struct mmc *mmc = find_mmc_device(0);
90 mmc_set_clock(mmc, mmc->saved_clock, false);
94 void k3_mmc_stop_clock(void) {}
95 void k3_mmc_restart_clock(void) {}
98 #ifdef CONFIG_SPL_OF_LIST
99 void do_dt_magic(void)
103 if (IS_ENABLED(CONFIG_K3_BOARD_DETECT))
107 * Board detection has been done.
108 * Let us see if another dtb wouldn't be a better match
111 if (IS_ENABLED(CONFIG_CPU_V7R)) {
112 ret = fdtdec_resetup(&rescan);
113 if (!ret && rescan) {
115 dm_init_and_scan(true);
121 #if CONFIG_IS_ENABLED(USB_STORAGE)
122 static int fixup_usb_boot(const void *fdt_blob)
126 switch (spl_boot_device()) {
127 case BOOT_DEVICE_USB:
129 * If the boot mode is host, fixup the dr_mode to host
130 * before cdns3 bind takes place
132 ret = fdt_find_and_setprop((void *)fdt_blob,
133 "/bus@f4000/cdns-usb@f900000/usb@f400000",
134 "dr_mode", "host", 5, 0);
136 printf("%s: fdt_find_and_setprop() failed:%d\n",
146 int fdtdec_board_setup(const void *fdt_blob)
148 /* Can use the pointer from the function parameters */
149 return fixup_usb_boot(fdt_blob);
153 #if defined(CONFIG_ESM_K3)
154 static void enable_mcu_esm_reset(void)
156 /* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z to '0' (low active) */
157 u32 stat = readl(CTRLMMR_MCU_RST_CTRL);
160 writel(stat, CTRLMMR_MCU_RST_CTRL);
164 void board_init_f(ulong dummy)
166 #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM64_DDRSS) || defined(CONFIG_ESM_K3)
171 #if defined(CONFIG_CPU_V7R)
172 setup_k3_mpu_regions();
176 * Cannot delay this further as there is a chance that
177 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
179 store_boot_info_from_rom();
186 preloader_console_init();
190 #if defined(CONFIG_K3_LOAD_SYSFW)
192 * Process pinctrl for serial3 a.k.a. MAIN UART1 module and continue
193 * regardless of the result of pinctrl. Do this without probing the
194 * device, but instead by searching the device that would request the
195 * given sequence number if probed. The UART will be used by the system
196 * firmware (SYSFW) image for various purposes and SYSFW depends on us
197 * to initialize its pin settings.
199 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev);
201 pinctrl_select_state(dev, "default");
204 * Load, start up, and configure system controller firmware.
205 * This will determine whether or not ROM has already loaded
206 * system firmware and if so, will only perform needed config
207 * and not attempt to load firmware again.
209 k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata), k3_mmc_stop_clock,
210 k3_mmc_restart_clock);
213 /* Output System Firmware version info */
214 k3_sysfw_print_ver();
216 #if defined(CONFIG_ESM_K3)
217 /* Probe/configure ESM0 */
218 ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev);
220 printf("esm main init failed: %d\n", ret);
222 /* Probe/configure MCUESM */
223 ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev);
225 printf("esm mcu init failed: %d\n", ret);
227 enable_mcu_esm_reset();
230 #if defined(CONFIG_K3_AM64_DDRSS)
231 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
233 panic("DRAM init failed: %d\n", ret);
235 if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) &&
236 spl_boot_device() == BOOT_DEVICE_ETHERNET) {
237 struct udevice *cpswdev;
239 if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss), &cpswdev))
240 printf("Failed to probe am65_cpsw_nuss driver\n");
244 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
246 switch (boot_device) {
247 case BOOT_DEVICE_MMC1:
248 return MMCSD_MODE_EMMCBOOT;
250 case BOOT_DEVICE_MMC2:
251 return MMCSD_MODE_FS;
254 return MMCSD_MODE_RAW;
258 static u32 __get_backup_bootmedia(u32 main_devstat)
261 (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
262 MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
263 u32 bkup_bootmode_cfg =
264 (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
265 MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
267 switch (bkup_bootmode) {
268 case BACKUP_BOOT_DEVICE_UART:
269 return BOOT_DEVICE_UART;
271 case BACKUP_BOOT_DEVICE_DFU:
272 if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
273 return BOOT_DEVICE_USB;
274 return BOOT_DEVICE_DFU;
277 case BACKUP_BOOT_DEVICE_ETHERNET:
278 return BOOT_DEVICE_ETHERNET;
280 case BACKUP_BOOT_DEVICE_MMC:
281 if (bkup_bootmode_cfg)
282 return BOOT_DEVICE_MMC2;
283 return BOOT_DEVICE_MMC1;
285 case BACKUP_BOOT_DEVICE_SPI:
286 return BOOT_DEVICE_SPI;
288 case BACKUP_BOOT_DEVICE_I2C:
289 return BOOT_DEVICE_I2C;
292 return BOOT_DEVICE_RAM;
295 static u32 __get_primary_bootmedia(u32 main_devstat)
297 u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
298 MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
300 (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
301 MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
304 case BOOT_DEVICE_OSPI:
306 case BOOT_DEVICE_QSPI:
308 case BOOT_DEVICE_XSPI:
310 case BOOT_DEVICE_SPI:
311 return BOOT_DEVICE_SPI;
313 case BOOT_DEVICE_ETHERNET_RGMII:
315 case BOOT_DEVICE_ETHERNET_RMII:
316 return BOOT_DEVICE_ETHERNET;
318 case BOOT_DEVICE_EMMC:
319 return BOOT_DEVICE_MMC1;
321 case BOOT_DEVICE_MMC:
322 if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
323 MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
324 return BOOT_DEVICE_MMC2;
325 return BOOT_DEVICE_MMC1;
327 case BOOT_DEVICE_DFU:
328 if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
329 MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
330 return BOOT_DEVICE_USB;
331 return BOOT_DEVICE_DFU;
333 case BOOT_DEVICE_NOBOOT:
334 return BOOT_DEVICE_RAM;
340 u32 spl_boot_device(void)
342 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
344 if (bootindex == K3_PRIMARY_BOOTMODE)
345 return __get_primary_bootmedia(devstat);
347 return __get_backup_bootmedia(devstat);
350 #if defined(CONFIG_SYS_K3_SPL_ATF)
352 #define AM64X_DEV_RTI8 127
353 #define AM64X_DEV_RTI9 128
354 #define AM64X_DEV_R5FSS0_CORE0 121
355 #define AM64X_DEV_R5FSS0_CORE1 122
357 void release_resources_for_core_shutdown(void)
359 struct ti_sci_handle *ti_sci = get_ti_sci_handle();
360 struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
361 struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
365 const u32 put_device_ids[] = {
370 /* Iterate through list of devices to put (shutdown) */
371 for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
372 u32 id = put_device_ids[i];
374 ret = dev_ops->put_device(ti_sci, id);
376 panic("Failed to put device %u (%d)\n", id, ret);
379 const u32 put_core_ids[] = {
380 AM64X_DEV_R5FSS0_CORE1,
381 AM64X_DEV_R5FSS0_CORE0, /* Handle CPU0 after CPU1 */
384 /* Iterate through list of cores to put (shutdown) */
385 for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
386 u32 id = put_core_ids[i];
389 * Queue up the core shutdown request. Note that this call
390 * needs to be followed up by an actual invocation of an WFE
391 * or WFI CPU instruction.
393 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
395 panic("Failed sending core %u shutdown message (%d)\n",