1 // SPDX-License-Identifier: GPL-2.0
3 * AM625: SoC specific initialization
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
6 * Suman Anna <s-anna@ti.com>
11 #include <asm/arch/hardware.h>
12 #include <asm/arch/sysfw-loader.h>
15 #include <dm/uclass-internal.h>
16 #include <dm/pinctrl.h>
18 #if defined(CONFIG_SPL_BUILD)
21 * This uninitialized global variable would normal end up in the .bss section,
22 * but the .bss is cleared between writing and reading this variable, so move
23 * it to the .data section.
25 u32 bootindex __section(".data");
26 static struct rom_extended_boot_data bootdata __section(".data");
28 static void store_boot_info_from_rom(void)
30 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
31 memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
32 sizeof(struct rom_extended_boot_data));
35 static void ctrl_mmr_unlock(void)
37 /* Unlock all WKUP_CTRL_MMR0 module registers */
38 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
39 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
40 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
41 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
42 mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
43 mmr_unlock(WKUP_CTRL_MMR0_BASE, 5);
44 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
45 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
47 /* Unlock all CTRL_MMR0 module registers */
48 mmr_unlock(CTRL_MMR0_BASE, 0);
49 mmr_unlock(CTRL_MMR0_BASE, 1);
50 mmr_unlock(CTRL_MMR0_BASE, 2);
51 mmr_unlock(CTRL_MMR0_BASE, 4);
52 mmr_unlock(CTRL_MMR0_BASE, 6);
54 /* Unlock all MCU_CTRL_MMR0 module registers */
55 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
56 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
57 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
58 mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
59 mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
60 mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
62 /* Unlock PADCFG_CTRL_MMR padconf registers */
63 mmr_unlock(PADCFG_MMR0_BASE, 1);
64 mmr_unlock(PADCFG_MMR1_BASE, 1);
67 static __maybe_unused void enable_mcu_esm_reset(void)
69 /* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z to '0' (low active) */
70 u32 stat = readl(CTRLMMR_MCU_RST_CTRL);
72 stat &= RST_CTRL_ESM_ERROR_RST_EN_Z_MASK;
73 writel(stat, CTRLMMR_MCU_RST_CTRL);
76 void board_init_f(ulong dummy)
81 #if defined(CONFIG_CPU_V7R)
82 setup_k3_mpu_regions();
86 * Cannot delay this further as there is a chance that
87 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
89 store_boot_info_from_rom();
97 * Process pinctrl for the serial0 and serial3, aka WKUP_UART0 and
98 * MAIN_UART1 modules and continue regardless of the result of pinctrl.
99 * Do this without probing the device, but instead by searching the
100 * device that would request the given sequence number if probed. The
101 * UARTs will be used by the DM firmware and TIFS firmware images
102 * respectively and the firmware depend on SPL to initialize the pin
105 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
107 pinctrl_select_state(dev, "default");
109 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev);
111 pinctrl_select_state(dev, "default");
113 preloader_console_init();
115 #ifdef CONFIG_K3_EARLY_CONS
117 * Allow establishing an early console as required for example when
118 * doing a UART-based boot. Note that this console may not "survive"
119 * through a SYSFW PM-init step and will need a re-init in some way
120 * due to changing module clock frequencies.
122 early_console_init();
125 #if defined(CONFIG_K3_LOAD_SYSFW)
127 * Configure and start up system controller firmware. Provide
128 * the U-Boot console init function to the SYSFW post-PM configuration
129 * callback hook, effectively switching on (or over) the console
132 ret = is_rom_loaded_sysfw(&bootdata);
134 panic("ROM has not loaded TIFS firmware\n");
136 k3_sysfw_loader(true, NULL, NULL);
140 * Force probe of clk_k3 driver here to ensure basic default clock
141 * configuration is always done.
143 if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
144 ret = uclass_get_device_by_driver(UCLASS_CLK,
145 DM_DRIVER_GET(ti_clk),
148 printf("Failed to initialize clk-k3!\n");
151 /* Output System Firmware version info */
152 k3_sysfw_print_ver();
154 if (IS_ENABLED(CONFIG_ESM_K3)) {
155 /* Probe/configure ESM0 */
156 ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev);
158 printf("esm main init failed: %d\n", ret);
160 /* Probe/configure MCUESM */
161 ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev);
163 printf("esm mcu init failed: %d\n", ret);
165 enable_mcu_esm_reset();
168 #if defined(CONFIG_K3_AM64_DDRSS)
169 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
171 panic("DRAM init failed: %d\n", ret);
175 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
177 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
178 u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
179 MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
181 switch (boot_device) {
182 case BOOT_DEVICE_MMC1:
183 if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK) >>
184 MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT)
185 return MMCSD_MODE_EMMCBOOT;
186 return MMCSD_MODE_FS;
188 case BOOT_DEVICE_MMC2:
189 return MMCSD_MODE_FS;
192 return MMCSD_MODE_RAW;
196 static u32 __get_backup_bootmedia(u32 devstat)
198 u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
199 MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
200 u32 bkup_bootmode_cfg =
201 (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
202 MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
204 switch (bkup_bootmode) {
205 case BACKUP_BOOT_DEVICE_UART:
206 return BOOT_DEVICE_UART;
208 case BACKUP_BOOT_DEVICE_USB:
209 return BOOT_DEVICE_USB;
211 case BACKUP_BOOT_DEVICE_ETHERNET:
212 return BOOT_DEVICE_ETHERNET;
214 case BACKUP_BOOT_DEVICE_MMC:
215 if (bkup_bootmode_cfg)
216 return BOOT_DEVICE_MMC2;
217 return BOOT_DEVICE_MMC1;
219 case BACKUP_BOOT_DEVICE_SPI:
220 return BOOT_DEVICE_SPI;
222 case BACKUP_BOOT_DEVICE_I2C:
223 return BOOT_DEVICE_I2C;
225 case BACKUP_BOOT_DEVICE_DFU:
226 if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
227 return BOOT_DEVICE_USB;
228 return BOOT_DEVICE_DFU;
231 return BOOT_DEVICE_RAM;
234 static u32 __get_primary_bootmedia(u32 devstat)
236 u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
237 MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
238 u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
239 MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
242 case BOOT_DEVICE_OSPI:
244 case BOOT_DEVICE_QSPI:
246 case BOOT_DEVICE_XSPI:
248 case BOOT_DEVICE_SPI:
249 return BOOT_DEVICE_SPI;
251 case BOOT_DEVICE_ETHERNET_RGMII:
253 case BOOT_DEVICE_ETHERNET_RMII:
254 return BOOT_DEVICE_ETHERNET;
256 case BOOT_DEVICE_EMMC:
257 return BOOT_DEVICE_MMC1;
259 case BOOT_DEVICE_MMC:
260 if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
261 MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
262 return BOOT_DEVICE_MMC2;
263 return BOOT_DEVICE_MMC1;
265 case BOOT_DEVICE_DFU:
266 if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
267 MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
268 return BOOT_DEVICE_USB;
269 return BOOT_DEVICE_DFU;
271 case BOOT_DEVICE_NOBOOT:
272 return BOOT_DEVICE_RAM;
278 u32 spl_boot_device(void)
280 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
283 if (bootindex == K3_PRIMARY_BOOTMODE)
284 bootmedia = __get_primary_bootmedia(devstat);
286 bootmedia = __get_backup_bootmedia(devstat);
288 debug("am625_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n",
289 __func__, devstat, bootmedia, bootindex);
294 #endif /* CONFIG_SPL_BUILD */