arch/arm/mach-ipq40xx/pinctrl-snapdragon.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * TLMM driver for Qualcomm IPQ40xx
   4  *
   5  * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
   6  *
   7  * Copyright (c) 2020 Sartura Ltd.
   8  *
   9  * Author: Robert Marko <robert.marko@sartura.hr>
  10  *
  11  */
  12
  13 #include <common.h>
  14 #include <dm.h>
  15 #include <errno.h>
  16 #include <asm/io.h>
  17 #include <dm/pinctrl.h>
  18 #include <linux/bitops.h>
  19 #include "pinctrl-snapdragon.h"
  20
  21 struct msm_pinctrl_priv {
  22         phys_addr_t base;
  23         struct msm_pinctrl_data *data;
  24 };
  25
  26 #define GPIO_CONFIG_OFFSET(x)         ((x) * 0x1000)
  27 #define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
  28 #define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
  29 #define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
  30 #define TLMM_GPIO_DISABLE BIT(9)
  31
  32 static const struct pinconf_param msm_conf_params[] = {
  33         { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },
  34         { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
  35         { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 2 },
  36 };
  37
  38 static int msm_get_functions_count(struct udevice *dev)
  39 {
  40         struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  41
  42         return priv->data->functions_count;
  43 }
  44
  45 static int msm_get_pins_count(struct udevice *dev)
  46 {
  47         struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  48
  49         return priv->data->pin_count;
  50 }
  51
  52 static const char *msm_get_function_name(struct udevice *dev,
  53                                          unsigned int selector)
  54 {
  55         struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  56
  57         return priv->data->get_function_name(dev, selector);
  58 }
  59
  60 static int msm_pinctrl_probe(struct udevice *dev)
  61 {
  62         struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  63
  64         priv->base = devfdt_get_addr(dev);
  65         priv->data = (struct msm_pinctrl_data *)dev->driver_data;
  66
  67         return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
  68 }
  69
  70 static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector)
  71 {
  72         struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  73
  74         return priv->data->get_pin_name(dev, selector);
  75 }
  76
  77 static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
  78                           unsigned int func_selector)
  79 {
  80         struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  81
  82         clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
  83                         TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
  84                         priv->data->get_function_mux(func_selector) << 2);
  85         return 0;
  86 }
  87
  88 static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
  89                            unsigned int param, unsigned int argument)
  90 {
  91         struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  92
  93         switch (param) {
  94         case PIN_CONFIG_DRIVE_STRENGTH:
  95                 clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
  96                                 TLMM_DRV_STRENGTH_MASK, argument << 6);
  97                 break;
  98         case PIN_CONFIG_BIAS_DISABLE:
  99                 clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
 100                              TLMM_GPIO_PULL_MASK);
 101                 break;
 102         case PIN_CONFIG_BIAS_PULL_UP:
 103                 clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
 104                              TLMM_GPIO_PULL_MASK, argument);
 105                 break;
 106         default:
 107                 return 0;
 108         }
 109
 110         return 0;
 111 }
 112
 113 static struct pinctrl_ops msm_pinctrl_ops = {
 114         .get_pins_count = msm_get_pins_count,
 115         .get_pin_name = msm_get_pin_name,
 116         .set_state = pinctrl_generic_set_state,
 117         .pinmux_set = msm_pinmux_set,
 118         .pinconf_num_params = ARRAY_SIZE(msm_conf_params),
 119         .pinconf_params = msm_conf_params,
 120         .pinconf_set = msm_pinconf_set,
 121         .get_functions_count = msm_get_functions_count,
 122         .get_function_name = msm_get_function_name,
 123 };
 124
 125 static const struct udevice_id msm_pinctrl_ids[] = {
 126         { .compatible = "qcom,tlmm-ipq4019", .data = (ulong)&ipq4019_data },
 127         { }
 128 };
 129
 130 U_BOOT_DRIVER(pinctrl_snapdraon) = {
 131         .name           = "pinctrl_msm",
 132         .id             = UCLASS_PINCTRL,
 133         .of_match       = msm_pinctrl_ids,
 134         .priv_auto      = sizeof(struct msm_pinctrl_priv),
 135         .ops            = &msm_pinctrl_ops,
 136         .probe          = msm_pinctrl_probe,
 137 };