1 // SPDX-License-Identifier: GPL-2.0+
3 * Clock drivers for Qualcomm IPQ40xx
5 * Copyright (c) 2020 Sartura Ltd.
7 * Author: Robert Marko <robert.marko@sartura.hr>
12 #include <clk-uclass.h>
16 #include <dt-bindings/clock/qcom,ipq4019-gcc.h>
22 ulong msm_set_rate(struct clk *clk, ulong rate)
25 case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
26 /* This clock is already initialized by SBL1 */
34 static int msm_clk_probe(struct udevice *dev)
36 struct msm_clk_priv *priv = dev_get_priv(dev);
38 priv->base = devfdt_get_addr(dev);
39 if (priv->base == FDT_ADDR_T_NONE)
45 static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
47 return msm_set_rate(clk, rate);
50 static int msm_enable(struct clk *clk)
53 case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/
54 /* This clock is already initialized by SBL1 */
57 case GCC_PRNG_AHB_CLK: /*PRNG*/
58 /* This clock is already initialized by SBL1 */
66 static struct clk_ops msm_clk_ops = {
67 .set_rate = msm_clk_set_rate,
71 static const struct udevice_id msm_clk_ids[] = {
72 { .compatible = "qcom,gcc-ipq4019" },
76 U_BOOT_DRIVER(clk_msm) = {
79 .of_match = msm_clk_ids,
81 .priv_auto_alloc_size = sizeof(struct msm_clk_priv),
82 .probe = msm_clk_probe,