arch/arm/mach-ipq40xx/clock-ipq4019.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Clock drivers for Qualcomm IPQ40xx
   4  *
   5  * Copyright (c) 2019 Sartura Ltd.
   6  *
   7  * Author: Robert Marko <robert.marko@sartura.hr>
   8  *
   9  */
  10
  11 #include <common.h>
  12 #include <clk-uclass.h>
  13 #include <dm.h>
  14 #include <errno.h>
  15
  16 #include <dt-bindings/clock/qcom,ipq4019-gcc.h>
  17
  18 struct msm_clk_priv {
  19         phys_addr_t base;
  20 };
  21
  22 ulong msm_set_rate(struct clk *clk, ulong rate)
  23 {
  24         switch (clk->id) {
  25         case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
  26                 /* This clock is already initialized by SBL1 */
  27                 return 0;
  28                 break;
  29         default:
  30                 return 0;
  31         }
  32 }
  33
  34 static int msm_clk_probe(struct udevice *dev)
  35 {
  36         struct msm_clk_priv *priv = dev_get_priv(dev);
  37
  38         priv->base = devfdt_get_addr(dev);
  39         if (priv->base == FDT_ADDR_T_NONE)
  40                 return -EINVAL;
  41
  42         return 0;
  43 }
  44
  45 static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
  46 {
  47         return msm_set_rate(clk, rate);
  48 }
  49
  50 static struct clk_ops msm_clk_ops = {
  51         .set_rate = msm_clk_set_rate,
  52 };
  53
  54 static const struct udevice_id msm_clk_ids[] = {
  55         { .compatible = "qcom,gcc-ipq4019" },
  56         { }
  57 };
  58
  59 U_BOOT_DRIVER(clk_msm) = {
  60         .name           = "clk_msm",
  61         .id             = UCLASS_CLK,
  62         .of_match       = msm_clk_ids,
  63         .ops            = &msm_clk_ops,
  64         .priv_auto_alloc_size = sizeof(struct msm_clk_priv),
  65         .probe          = msm_clk_probe,
  66 };