1 // SPDX-License-Identifier: GPL-2.0+
3 * Clock drivers for Qualcomm IPQ40xx
5 * Copyright (c) 2019 Sartura Ltd.
7 * Author: Robert Marko <robert.marko@sartura.hr>
12 #include <clk-uclass.h>
20 ulong msm_set_rate(struct clk *clk, ulong rate)
24 /* This clock is already initialized by SBL1 */
32 static int msm_clk_probe(struct udevice *dev)
34 struct msm_clk_priv *priv = dev_get_priv(dev);
36 priv->base = devfdt_get_addr(dev);
37 if (priv->base == FDT_ADDR_T_NONE)
43 static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
45 return msm_set_rate(clk, rate);
48 static struct clk_ops msm_clk_ops = {
49 .set_rate = msm_clk_set_rate,
52 static const struct udevice_id msm_clk_ids[] = {
53 { .compatible = "qcom,gcc-ipq4019" },
57 U_BOOT_DRIVER(clk_msm) = {
60 .of_match = msm_clk_ids,
62 .priv_auto_alloc_size = sizeof(struct msm_clk_priv),
63 .probe = msm_clk_probe,